1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Hygon Processor Support for Linux 4 * 5 * Copyright (C) 2018 Chengdu Haiguang IC Design Co., Ltd. 6 * 7 * Author: Pu Wen <puwen@hygon.cn> 8 */ 9 #include <linux/io.h> 10 11 #include <asm/apic.h> 12 #include <asm/cpu.h> 13 #include <asm/smp.h> 14 #include <asm/numa.h> 15 #include <asm/cacheinfo.h> 16 #include <asm/spec-ctrl.h> 17 #include <asm/delay.h> 18 #include <asm/msr.h> 19 20 #include "cpu.h" 21 22 #ifdef CONFIG_NUMA 23 /* 24 * To workaround broken NUMA config. Read the comment in 25 * srat_detect_node(). 26 */ 27 static int nearby_node(int apicid) 28 { 29 int i, node; 30 31 for (i = apicid - 1; i >= 0; i--) { 32 node = __apicid_to_node[i]; 33 if (node != NUMA_NO_NODE && node_online(node)) 34 return node; 35 } 36 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 37 node = __apicid_to_node[i]; 38 if (node != NUMA_NO_NODE && node_online(node)) 39 return node; 40 } 41 return first_node(node_online_map); /* Shouldn't happen */ 42 } 43 #endif 44 45 static void srat_detect_node(struct cpuinfo_x86 *c) 46 { 47 #ifdef CONFIG_NUMA 48 int cpu = smp_processor_id(); 49 int node; 50 unsigned int apicid = c->topo.apicid; 51 52 node = numa_cpu_node(cpu); 53 if (node == NUMA_NO_NODE) 54 node = c->topo.llc_id; 55 56 /* 57 * On multi-fabric platform (e.g. Numascale NumaChip) a 58 * platform-specific handler needs to be called to fixup some 59 * IDs of the CPU. 60 */ 61 if (x86_cpuinit.fixup_cpu_id) 62 x86_cpuinit.fixup_cpu_id(c, node); 63 64 if (!node_online(node)) { 65 /* 66 * Two possibilities here: 67 * 68 * - The CPU is missing memory and no node was created. In 69 * that case try picking one from a nearby CPU. 70 * 71 * - The APIC IDs differ from the HyperTransport node IDs. 72 * Assume they are all increased by a constant offset, but 73 * in the same order as the HT nodeids. If that doesn't 74 * result in a usable node fall back to the path for the 75 * previous case. 76 * 77 * This workaround operates directly on the mapping between 78 * APIC ID and NUMA node, assuming certain relationship 79 * between APIC ID, HT node ID and NUMA topology. As going 80 * through CPU mapping may alter the outcome, directly 81 * access __apicid_to_node[]. 82 */ 83 int ht_nodeid = c->topo.initial_apicid; 84 85 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 86 node = __apicid_to_node[ht_nodeid]; 87 /* Pick a nearby node */ 88 if (!node_online(node)) 89 node = nearby_node(apicid); 90 } 91 numa_set_node(cpu, node); 92 #endif 93 } 94 95 static void bsp_init_hygon(struct cpuinfo_x86 *c) 96 { 97 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 98 u64 val; 99 100 rdmsrq(MSR_K7_HWCR, val); 101 if (!(val & BIT(24))) 102 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); 103 } 104 105 if (cpu_has(c, X86_FEATURE_MWAITX)) 106 use_mwaitx_delay(); 107 108 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) && 109 !boot_cpu_has(X86_FEATURE_VIRT_SSBD)) { 110 /* 111 * Try to cache the base value so further operations can 112 * avoid RMW. If that faults, do not enable SSBD. 113 */ 114 if (!rdmsrq_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) { 115 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD); 116 setup_force_cpu_cap(X86_FEATURE_SSBD); 117 x86_amd_ls_cfg_ssbd_mask = 1ULL << 10; 118 } 119 } 120 } 121 122 static void early_init_hygon(struct cpuinfo_x86 *c) 123 { 124 u32 dummy; 125 126 set_cpu_cap(c, X86_FEATURE_K8); 127 128 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); 129 130 /* 131 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 132 * with P/T states and does not stop in deep C-states 133 */ 134 if (c->x86_power & (1 << 8)) { 135 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 136 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 137 } 138 139 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ 140 if (c->x86_power & BIT(12)) 141 set_cpu_cap(c, X86_FEATURE_ACC_POWER); 142 143 /* Bit 14 indicates the Runtime Average Power Limit interface. */ 144 if (c->x86_power & BIT(14)) 145 set_cpu_cap(c, X86_FEATURE_RAPL); 146 147 #ifdef CONFIG_X86_64 148 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 149 #endif 150 151 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 152 /* 153 * ApicID can always be treated as an 8-bit value for Hygon APIC So, we 154 * can safely set X86_FEATURE_EXTD_APICID unconditionally. 155 */ 156 if (boot_cpu_has(X86_FEATURE_APIC)) 157 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 158 #endif 159 160 /* 161 * This is only needed to tell the kernel whether to use VMCALL 162 * and VMMCALL. VMMCALL is never executed except under virt, so 163 * we can set it unconditionally. 164 */ 165 set_cpu_cap(c, X86_FEATURE_VMMCALL); 166 } 167 168 static void init_hygon(struct cpuinfo_x86 *c) 169 { 170 u64 vm_cr; 171 172 early_init_hygon(c); 173 174 /* 175 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 176 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 177 */ 178 clear_cpu_cap(c, 0*32+31); 179 180 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 181 182 /* 183 * XXX someone from Hygon needs to confirm this DTRT 184 * 185 init_spectral_chicken(c); 186 */ 187 188 set_cpu_cap(c, X86_FEATURE_ZEN); 189 set_cpu_cap(c, X86_FEATURE_CPB); 190 191 cpu_detect_cache_sizes(c); 192 193 srat_detect_node(c); 194 195 init_hygon_cacheinfo(c); 196 197 if (cpu_has(c, X86_FEATURE_SVM)) { 198 rdmsrq(MSR_VM_CR, vm_cr); 199 if (vm_cr & SVM_VM_CR_SVM_DIS_MASK) { 200 pr_notice_once("SVM disabled (by BIOS) in MSR_VM_CR\n"); 201 clear_cpu_cap(c, X86_FEATURE_SVM); 202 } 203 } 204 205 if (cpu_has(c, X86_FEATURE_XMM2)) { 206 /* 207 * Use LFENCE for execution serialization. On families which 208 * don't have that MSR, LFENCE is already serializing. 209 * msr_set_bit() uses the safe accessors, too, even if the MSR 210 * is not present. 211 */ 212 msr_set_bit(MSR_AMD64_DE_CFG, 213 MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT); 214 215 /* A serializing LFENCE stops RDTSC speculation */ 216 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 217 } 218 219 /* 220 * Hygon processors have APIC timer running in deep C states. 221 */ 222 set_cpu_cap(c, X86_FEATURE_ARAT); 223 224 /* Hygon CPUs don't reset SS attributes on SYSRET, Xen does. */ 225 if (!cpu_feature_enabled(X86_FEATURE_XENPV)) 226 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); 227 228 check_null_seg_clears_base(c); 229 230 /* Hygon CPUs don't need fencing after x2APIC/TSC_DEADLINE MSR writes. */ 231 clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE); 232 } 233 234 static void cpu_detect_tlb_hygon(struct cpuinfo_x86 *c) 235 { 236 u32 ebx, eax, ecx, edx; 237 u16 mask = 0xfff; 238 239 if (c->extended_cpuid_level < 0x80000006) 240 return; 241 242 cpuid(0x80000006, &eax, &ebx, &ecx, &edx); 243 244 tlb_lld_4k = (ebx >> 16) & mask; 245 tlb_lli_4k = ebx & mask; 246 247 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 248 if (!((eax >> 16) & mask)) 249 tlb_lld_2m = (cpuid_eax(0x80000005) >> 16) & 0xff; 250 else 251 tlb_lld_2m = (eax >> 16) & mask; 252 253 /* a 4M entry uses two 2M entries */ 254 tlb_lld_4m = tlb_lld_2m >> 1; 255 256 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 257 if (!(eax & mask)) { 258 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 259 tlb_lli_2m = eax & 0xff; 260 } else 261 tlb_lli_2m = eax & mask; 262 263 tlb_lli_4m = tlb_lli_2m >> 1; 264 } 265 266 static const struct cpu_dev hygon_cpu_dev = { 267 .c_vendor = "Hygon", 268 .c_ident = { "HygonGenuine" }, 269 .c_early_init = early_init_hygon, 270 .c_detect_tlb = cpu_detect_tlb_hygon, 271 .c_bsp_init = bsp_init_hygon, 272 .c_init = init_hygon, 273 .c_x86_vendor = X86_VENDOR_HYGON, 274 }; 275 276 cpu_dev_register(hygon_cpu_dev); 277