1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Hygon Processor Support for Linux 4 * 5 * Copyright (C) 2018 Chengdu Haiguang IC Design Co., Ltd. 6 * 7 * Author: Pu Wen <puwen@hygon.cn> 8 */ 9 #include <linux/io.h> 10 11 #include <asm/apic.h> 12 #include <asm/cpu.h> 13 #include <asm/cpuid/api.h> 14 #include <asm/smp.h> 15 #include <asm/numa.h> 16 #include <asm/cacheinfo.h> 17 #include <asm/spec-ctrl.h> 18 #include <asm/delay.h> 19 #include <asm/msr.h> 20 #include <asm/resctrl.h> 21 22 #include "cpu.h" 23 24 #ifdef CONFIG_NUMA 25 /* 26 * To workaround broken NUMA config. Read the comment in 27 * srat_detect_node(). 28 */ 29 static int nearby_node(int apicid) 30 { 31 int i, node; 32 33 for (i = apicid - 1; i >= 0; i--) { 34 node = __apicid_to_node[i]; 35 if (node != NUMA_NO_NODE && node_online(node)) 36 return node; 37 } 38 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 39 node = __apicid_to_node[i]; 40 if (node != NUMA_NO_NODE && node_online(node)) 41 return node; 42 } 43 return first_node(node_online_map); /* Shouldn't happen */ 44 } 45 #endif 46 47 static void srat_detect_node(struct cpuinfo_x86 *c) 48 { 49 #ifdef CONFIG_NUMA 50 int cpu = smp_processor_id(); 51 int node; 52 unsigned int apicid = c->topo.apicid; 53 54 node = numa_cpu_node(cpu); 55 if (node == NUMA_NO_NODE) 56 node = c->topo.llc_id; 57 58 /* 59 * On multi-fabric platform (e.g. Numascale NumaChip) a 60 * platform-specific handler needs to be called to fixup some 61 * IDs of the CPU. 62 */ 63 if (x86_cpuinit.fixup_cpu_id) 64 x86_cpuinit.fixup_cpu_id(c, node); 65 66 if (!node_online(node)) { 67 /* 68 * Two possibilities here: 69 * 70 * - The CPU is missing memory and no node was created. In 71 * that case try picking one from a nearby CPU. 72 * 73 * - The APIC IDs differ from the HyperTransport node IDs. 74 * Assume they are all increased by a constant offset, but 75 * in the same order as the HT nodeids. If that doesn't 76 * result in a usable node fall back to the path for the 77 * previous case. 78 * 79 * This workaround operates directly on the mapping between 80 * APIC ID and NUMA node, assuming certain relationship 81 * between APIC ID, HT node ID and NUMA topology. As going 82 * through CPU mapping may alter the outcome, directly 83 * access __apicid_to_node[]. 84 */ 85 int ht_nodeid = c->topo.initial_apicid; 86 87 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 88 node = __apicid_to_node[ht_nodeid]; 89 /* Pick a nearby node */ 90 if (!node_online(node)) 91 node = nearby_node(apicid); 92 } 93 numa_set_node(cpu, node); 94 #endif 95 } 96 97 static void bsp_init_hygon(struct cpuinfo_x86 *c) 98 { 99 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 100 u64 val; 101 102 rdmsrq(MSR_K7_HWCR, val); 103 if (!(val & BIT(24))) 104 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); 105 } 106 107 if (cpu_has(c, X86_FEATURE_MWAITX)) 108 use_mwaitx_delay(); 109 110 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) && 111 !boot_cpu_has(X86_FEATURE_VIRT_SSBD)) { 112 /* 113 * Try to cache the base value so further operations can 114 * avoid RMW. If that faults, do not enable SSBD. 115 */ 116 if (!rdmsrq_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) { 117 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD); 118 setup_force_cpu_cap(X86_FEATURE_SSBD); 119 x86_amd_ls_cfg_ssbd_mask = 1ULL << 10; 120 } 121 } 122 123 resctrl_cpu_detect(c); 124 } 125 126 static void early_init_hygon(struct cpuinfo_x86 *c) 127 { 128 u32 dummy; 129 130 set_cpu_cap(c, X86_FEATURE_K8); 131 132 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); 133 134 /* 135 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 136 * with P/T states and does not stop in deep C-states 137 */ 138 if (c->x86_power & (1 << 8)) { 139 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 140 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 141 } 142 143 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ 144 if (c->x86_power & BIT(12)) 145 set_cpu_cap(c, X86_FEATURE_ACC_POWER); 146 147 /* Bit 14 indicates the Runtime Average Power Limit interface. */ 148 if (c->x86_power & BIT(14)) 149 set_cpu_cap(c, X86_FEATURE_RAPL); 150 151 #ifdef CONFIG_X86_64 152 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 153 #endif 154 155 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 156 /* 157 * ApicID can always be treated as an 8-bit value for Hygon APIC So, we 158 * can safely set X86_FEATURE_EXTD_APICID unconditionally. 159 */ 160 if (boot_cpu_has(X86_FEATURE_APIC)) 161 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 162 #endif 163 164 /* 165 * This is only needed to tell the kernel whether to use VMCALL 166 * and VMMCALL. VMMCALL is never executed except under virt, so 167 * we can set it unconditionally. 168 */ 169 set_cpu_cap(c, X86_FEATURE_VMMCALL); 170 } 171 172 static void init_hygon(struct cpuinfo_x86 *c) 173 { 174 u64 vm_cr; 175 176 early_init_hygon(c); 177 178 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 179 180 /* 181 * XXX someone from Hygon needs to confirm this DTRT 182 * 183 init_spectral_chicken(c); 184 */ 185 186 set_cpu_cap(c, X86_FEATURE_ZEN); 187 set_cpu_cap(c, X86_FEATURE_CPB); 188 189 cpu_detect_cache_sizes(c); 190 191 srat_detect_node(c); 192 193 init_hygon_cacheinfo(c); 194 195 if (cpu_has(c, X86_FEATURE_SVM)) { 196 rdmsrq(MSR_VM_CR, vm_cr); 197 if (vm_cr & SVM_VM_CR_SVM_DIS_MASK) { 198 pr_notice_once("SVM disabled (by BIOS) in MSR_VM_CR\n"); 199 clear_cpu_cap(c, X86_FEATURE_SVM); 200 } 201 } 202 203 if (cpu_has(c, X86_FEATURE_XMM2)) { 204 /* 205 * Use LFENCE for execution serialization. On families which 206 * don't have that MSR, LFENCE is already serializing. 207 * msr_set_bit() uses the safe accessors, too, even if the MSR 208 * is not present. 209 */ 210 msr_set_bit(MSR_AMD64_DE_CFG, 211 MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT); 212 213 /* A serializing LFENCE stops RDTSC speculation */ 214 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 215 } 216 217 /* 218 * Hygon processors have APIC timer running in deep C states. 219 */ 220 set_cpu_cap(c, X86_FEATURE_ARAT); 221 222 /* Hygon CPUs don't reset SS attributes on SYSRET, Xen does. */ 223 if (!cpu_feature_enabled(X86_FEATURE_XENPV)) 224 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); 225 226 check_null_seg_clears_base(c); 227 228 /* Hygon CPUs don't need fencing after x2APIC/TSC_DEADLINE MSR writes. */ 229 clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE); 230 } 231 232 static void cpu_detect_tlb_hygon(struct cpuinfo_x86 *c) 233 { 234 u32 ebx, eax, ecx, edx; 235 u16 mask = 0xfff; 236 237 if (c->extended_cpuid_level < 0x80000006) 238 return; 239 240 cpuid(0x80000006, &eax, &ebx, &ecx, &edx); 241 242 tlb_lld_4k = (ebx >> 16) & mask; 243 tlb_lli_4k = ebx & mask; 244 245 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 246 if (!((eax >> 16) & mask)) 247 tlb_lld_2m = (cpuid_eax(0x80000005) >> 16) & 0xff; 248 else 249 tlb_lld_2m = (eax >> 16) & mask; 250 251 /* a 4M entry uses two 2M entries */ 252 tlb_lld_4m = tlb_lld_2m >> 1; 253 254 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 255 if (!(eax & mask)) { 256 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 257 tlb_lli_2m = eax & 0xff; 258 } else 259 tlb_lli_2m = eax & mask; 260 261 tlb_lli_4m = tlb_lli_2m >> 1; 262 } 263 264 static const struct cpu_dev hygon_cpu_dev = { 265 .c_vendor = "Hygon", 266 .c_ident = { "HygonGenuine" }, 267 .c_early_init = early_init_hygon, 268 .c_detect_tlb = cpu_detect_tlb_hygon, 269 .c_bsp_init = bsp_init_hygon, 270 .c_init = init_hygon, 271 .c_x86_vendor = X86_VENDOR_HYGON, 272 }; 273 274 cpu_dev_register(hygon_cpu_dev); 275