1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Hygon Processor Support for Linux 4 * 5 * Copyright (C) 2018 Chengdu Haiguang IC Design Co., Ltd. 6 * 7 * Author: Pu Wen <puwen@hygon.cn> 8 */ 9 #include <linux/io.h> 10 11 #include <asm/apic.h> 12 #include <asm/cpu.h> 13 #include <asm/smp.h> 14 #include <asm/numa.h> 15 #include <asm/cacheinfo.h> 16 #include <asm/spec-ctrl.h> 17 #include <asm/delay.h> 18 #include <asm/msr.h> 19 #include <asm/resctrl.h> 20 21 #include "cpu.h" 22 23 #ifdef CONFIG_NUMA 24 /* 25 * To workaround broken NUMA config. Read the comment in 26 * srat_detect_node(). 27 */ 28 static int nearby_node(int apicid) 29 { 30 int i, node; 31 32 for (i = apicid - 1; i >= 0; i--) { 33 node = __apicid_to_node[i]; 34 if (node != NUMA_NO_NODE && node_online(node)) 35 return node; 36 } 37 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 38 node = __apicid_to_node[i]; 39 if (node != NUMA_NO_NODE && node_online(node)) 40 return node; 41 } 42 return first_node(node_online_map); /* Shouldn't happen */ 43 } 44 #endif 45 46 static void srat_detect_node(struct cpuinfo_x86 *c) 47 { 48 #ifdef CONFIG_NUMA 49 int cpu = smp_processor_id(); 50 int node; 51 unsigned int apicid = c->topo.apicid; 52 53 node = numa_cpu_node(cpu); 54 if (node == NUMA_NO_NODE) 55 node = c->topo.llc_id; 56 57 /* 58 * On multi-fabric platform (e.g. Numascale NumaChip) a 59 * platform-specific handler needs to be called to fixup some 60 * IDs of the CPU. 61 */ 62 if (x86_cpuinit.fixup_cpu_id) 63 x86_cpuinit.fixup_cpu_id(c, node); 64 65 if (!node_online(node)) { 66 /* 67 * Two possibilities here: 68 * 69 * - The CPU is missing memory and no node was created. In 70 * that case try picking one from a nearby CPU. 71 * 72 * - The APIC IDs differ from the HyperTransport node IDs. 73 * Assume they are all increased by a constant offset, but 74 * in the same order as the HT nodeids. If that doesn't 75 * result in a usable node fall back to the path for the 76 * previous case. 77 * 78 * This workaround operates directly on the mapping between 79 * APIC ID and NUMA node, assuming certain relationship 80 * between APIC ID, HT node ID and NUMA topology. As going 81 * through CPU mapping may alter the outcome, directly 82 * access __apicid_to_node[]. 83 */ 84 int ht_nodeid = c->topo.initial_apicid; 85 86 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 87 node = __apicid_to_node[ht_nodeid]; 88 /* Pick a nearby node */ 89 if (!node_online(node)) 90 node = nearby_node(apicid); 91 } 92 numa_set_node(cpu, node); 93 #endif 94 } 95 96 static void bsp_init_hygon(struct cpuinfo_x86 *c) 97 { 98 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 99 u64 val; 100 101 rdmsrq(MSR_K7_HWCR, val); 102 if (!(val & BIT(24))) 103 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); 104 } 105 106 if (cpu_has(c, X86_FEATURE_MWAITX)) 107 use_mwaitx_delay(); 108 109 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) && 110 !boot_cpu_has(X86_FEATURE_VIRT_SSBD)) { 111 /* 112 * Try to cache the base value so further operations can 113 * avoid RMW. If that faults, do not enable SSBD. 114 */ 115 if (!rdmsrq_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) { 116 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD); 117 setup_force_cpu_cap(X86_FEATURE_SSBD); 118 x86_amd_ls_cfg_ssbd_mask = 1ULL << 10; 119 } 120 } 121 122 resctrl_cpu_detect(c); 123 } 124 125 static void early_init_hygon(struct cpuinfo_x86 *c) 126 { 127 u32 dummy; 128 129 set_cpu_cap(c, X86_FEATURE_K8); 130 131 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); 132 133 /* 134 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 135 * with P/T states and does not stop in deep C-states 136 */ 137 if (c->x86_power & (1 << 8)) { 138 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 139 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 140 } 141 142 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ 143 if (c->x86_power & BIT(12)) 144 set_cpu_cap(c, X86_FEATURE_ACC_POWER); 145 146 /* Bit 14 indicates the Runtime Average Power Limit interface. */ 147 if (c->x86_power & BIT(14)) 148 set_cpu_cap(c, X86_FEATURE_RAPL); 149 150 #ifdef CONFIG_X86_64 151 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 152 #endif 153 154 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 155 /* 156 * ApicID can always be treated as an 8-bit value for Hygon APIC So, we 157 * can safely set X86_FEATURE_EXTD_APICID unconditionally. 158 */ 159 if (boot_cpu_has(X86_FEATURE_APIC)) 160 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 161 #endif 162 163 /* 164 * This is only needed to tell the kernel whether to use VMCALL 165 * and VMMCALL. VMMCALL is never executed except under virt, so 166 * we can set it unconditionally. 167 */ 168 set_cpu_cap(c, X86_FEATURE_VMMCALL); 169 } 170 171 static void init_hygon(struct cpuinfo_x86 *c) 172 { 173 u64 vm_cr; 174 175 early_init_hygon(c); 176 177 /* 178 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 179 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 180 */ 181 clear_cpu_cap(c, 0*32+31); 182 183 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 184 185 /* 186 * XXX someone from Hygon needs to confirm this DTRT 187 * 188 init_spectral_chicken(c); 189 */ 190 191 set_cpu_cap(c, X86_FEATURE_ZEN); 192 set_cpu_cap(c, X86_FEATURE_CPB); 193 194 cpu_detect_cache_sizes(c); 195 196 srat_detect_node(c); 197 198 init_hygon_cacheinfo(c); 199 200 if (cpu_has(c, X86_FEATURE_SVM)) { 201 rdmsrq(MSR_VM_CR, vm_cr); 202 if (vm_cr & SVM_VM_CR_SVM_DIS_MASK) { 203 pr_notice_once("SVM disabled (by BIOS) in MSR_VM_CR\n"); 204 clear_cpu_cap(c, X86_FEATURE_SVM); 205 } 206 } 207 208 if (cpu_has(c, X86_FEATURE_XMM2)) { 209 /* 210 * Use LFENCE for execution serialization. On families which 211 * don't have that MSR, LFENCE is already serializing. 212 * msr_set_bit() uses the safe accessors, too, even if the MSR 213 * is not present. 214 */ 215 msr_set_bit(MSR_AMD64_DE_CFG, 216 MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT); 217 218 /* A serializing LFENCE stops RDTSC speculation */ 219 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 220 } 221 222 /* 223 * Hygon processors have APIC timer running in deep C states. 224 */ 225 set_cpu_cap(c, X86_FEATURE_ARAT); 226 227 /* Hygon CPUs don't reset SS attributes on SYSRET, Xen does. */ 228 if (!cpu_feature_enabled(X86_FEATURE_XENPV)) 229 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); 230 231 check_null_seg_clears_base(c); 232 233 /* Hygon CPUs don't need fencing after x2APIC/TSC_DEADLINE MSR writes. */ 234 clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE); 235 } 236 237 static void cpu_detect_tlb_hygon(struct cpuinfo_x86 *c) 238 { 239 u32 ebx, eax, ecx, edx; 240 u16 mask = 0xfff; 241 242 if (c->extended_cpuid_level < 0x80000006) 243 return; 244 245 cpuid(0x80000006, &eax, &ebx, &ecx, &edx); 246 247 tlb_lld_4k = (ebx >> 16) & mask; 248 tlb_lli_4k = ebx & mask; 249 250 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 251 if (!((eax >> 16) & mask)) 252 tlb_lld_2m = (cpuid_eax(0x80000005) >> 16) & 0xff; 253 else 254 tlb_lld_2m = (eax >> 16) & mask; 255 256 /* a 4M entry uses two 2M entries */ 257 tlb_lld_4m = tlb_lld_2m >> 1; 258 259 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 260 if (!(eax & mask)) { 261 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 262 tlb_lli_2m = eax & 0xff; 263 } else 264 tlb_lli_2m = eax & mask; 265 266 tlb_lli_4m = tlb_lli_2m >> 1; 267 } 268 269 static const struct cpu_dev hygon_cpu_dev = { 270 .c_vendor = "Hygon", 271 .c_ident = { "HygonGenuine" }, 272 .c_early_init = early_init_hygon, 273 .c_detect_tlb = cpu_detect_tlb_hygon, 274 .c_bsp_init = bsp_init_hygon, 275 .c_init = init_hygon, 276 .c_x86_vendor = X86_VENDOR_HYGON, 277 }; 278 279 cpu_dev_register(hygon_cpu_dev); 280