1 // SPDX-License-Identifier: GPL-2.0 2 3 #include <linux/sched.h> 4 #include <linux/sched/clock.h> 5 6 #include <asm/cpu.h> 7 #include <asm/cpufeature.h> 8 #include <asm/cpuid/api.h> 9 #include <asm/e820/api.h> 10 #include <asm/mtrr.h> 11 #include <asm/msr.h> 12 13 #include "cpu.h" 14 15 #define ACE_PRESENT (1 << 6) 16 #define ACE_ENABLED (1 << 7) 17 #define ACE_FCR (1 << 28) /* MSR_VIA_FCR */ 18 19 #define RNG_PRESENT (1 << 2) 20 #define RNG_ENABLED (1 << 3) 21 #define RNG_ENABLE (1 << 6) /* MSR_VIA_RNG */ 22 23 static void init_c3(struct cpuinfo_x86 *c) 24 { 25 u32 lo, hi; 26 27 /* Test for Centaur Extended Feature Flags presence */ 28 if (cpuid_eax(0xC0000000) >= 0xC0000001) { 29 u32 tmp = cpuid_edx(0xC0000001); 30 31 /* enable ACE unit, if present and disabled */ 32 if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) { 33 rdmsr(MSR_VIA_FCR, lo, hi); 34 lo |= ACE_FCR; /* enable ACE unit */ 35 wrmsr(MSR_VIA_FCR, lo, hi); 36 pr_info("CPU: Enabled ACE h/w crypto\n"); 37 } 38 39 /* enable RNG unit, if present and disabled */ 40 if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) { 41 rdmsr(MSR_VIA_RNG, lo, hi); 42 lo |= RNG_ENABLE; /* enable RNG unit */ 43 wrmsr(MSR_VIA_RNG, lo, hi); 44 pr_info("CPU: Enabled h/w RNG\n"); 45 } 46 47 /* store Centaur Extended Feature Flags as 48 * word 5 of the CPU capability bit array 49 */ 50 c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001); 51 } 52 #ifdef CONFIG_X86_32 53 /* Cyrix III family needs CX8 & PGE explicitly enabled. */ 54 if (c->x86_model >= 6 && c->x86_model <= 13) { 55 rdmsr(MSR_VIA_FCR, lo, hi); 56 lo |= (1<<1 | 1<<7); 57 wrmsr(MSR_VIA_FCR, lo, hi); 58 set_cpu_cap(c, X86_FEATURE_CX8); 59 } 60 61 /* Before Nehemiah, the C3's had 3dNOW! */ 62 if (c->x86_model >= 6 && c->x86_model < 9) 63 set_cpu_cap(c, X86_FEATURE_3DNOW); 64 #endif 65 if (c->x86 == 0x6 && c->x86_model >= 0xf) { 66 c->x86_cache_alignment = c->x86_clflush_size * 2; 67 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 68 } 69 70 if (c->x86 >= 7) 71 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 72 } 73 74 enum { 75 ECX8 = 1<<1, 76 EIERRINT = 1<<2, 77 DPM = 1<<3, 78 DMCE = 1<<4, 79 DSTPCLK = 1<<5, 80 ELINEAR = 1<<6, 81 DSMC = 1<<7, 82 DTLOCK = 1<<8, 83 EDCTLB = 1<<8, 84 EMMX = 1<<9, 85 DPDC = 1<<11, 86 EBRPRED = 1<<12, 87 DIC = 1<<13, 88 DDC = 1<<14, 89 DNA = 1<<15, 90 ERETSTK = 1<<16, 91 E2MMX = 1<<19, 92 EAMD3D = 1<<20, 93 }; 94 95 static void early_init_centaur(struct cpuinfo_x86 *c) 96 { 97 #ifdef CONFIG_X86_32 98 /* Emulate MTRRs using Centaur's MCR. */ 99 if (c->x86 == 5) 100 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR); 101 #endif 102 if ((c->x86 == 6 && c->x86_model >= 0xf) || 103 (c->x86 >= 7)) 104 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 105 106 if (c->x86_power & (1 << 8)) { 107 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 108 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 109 } 110 } 111 112 static void init_centaur(struct cpuinfo_x86 *c) 113 { 114 #ifdef CONFIG_X86_32 115 char *name; 116 u32 fcr_set = 0; 117 u32 fcr_clr = 0; 118 u32 lo, hi, newlo; 119 u32 aa, bb, cc, dd; 120 #endif 121 early_init_centaur(c); 122 init_intel_cacheinfo(c); 123 124 if (c->cpuid_level > 9) { 125 unsigned int eax = cpuid_eax(10); 126 127 /* 128 * Check for version and the number of counters 129 * Version(eax[7:0]) can't be 0; 130 * Counters(eax[15:8]) should be greater than 1; 131 */ 132 if ((eax & 0xff) && (((eax >> 8) & 0xff) > 1)) 133 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); 134 } 135 136 #ifdef CONFIG_X86_32 137 if (c->x86 == 5) { 138 switch (c->x86_model) { 139 case 4: 140 name = "C6"; 141 fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK; 142 fcr_clr = DPDC; 143 pr_notice("Disabling bugged TSC.\n"); 144 clear_cpu_cap(c, X86_FEATURE_TSC); 145 break; 146 case 8: 147 switch (c->x86_stepping) { 148 default: 149 name = "2"; 150 break; 151 case 7 ... 9: 152 name = "2A"; 153 break; 154 case 10 ... 15: 155 name = "2B"; 156 break; 157 } 158 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK| 159 E2MMX|EAMD3D; 160 fcr_clr = DPDC; 161 break; 162 case 9: 163 name = "3"; 164 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK| 165 E2MMX|EAMD3D; 166 fcr_clr = DPDC; 167 break; 168 default: 169 name = "??"; 170 } 171 172 rdmsr(MSR_IDT_FCR1, lo, hi); 173 newlo = (lo|fcr_set) & (~fcr_clr); 174 175 if (newlo != lo) { 176 pr_info("Centaur FCR was 0x%X now 0x%X\n", 177 lo, newlo); 178 wrmsr(MSR_IDT_FCR1, newlo, hi); 179 } else { 180 pr_info("Centaur FCR is 0x%X\n", lo); 181 } 182 /* Emulate MTRRs using Centaur's MCR. */ 183 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR); 184 /* Report CX8 */ 185 set_cpu_cap(c, X86_FEATURE_CX8); 186 /* Set 3DNow! on Winchip 2 and above. */ 187 if (c->x86_model >= 8) 188 set_cpu_cap(c, X86_FEATURE_3DNOW); 189 /* See if we can find out some more. */ 190 if (cpuid_eax(0x80000000) >= 0x80000005) { 191 /* Yes, we can. */ 192 cpuid(0x80000005, &aa, &bb, &cc, &dd); 193 /* Add L1 data and code cache sizes. */ 194 c->x86_cache_size = (cc>>24)+(dd>>24); 195 } 196 sprintf(c->x86_model_id, "WinChip %s", name); 197 } 198 #endif 199 if (c->x86 == 6 || c->x86 >= 7) 200 init_c3(c); 201 #ifdef CONFIG_X86_64 202 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 203 #endif 204 205 init_ia32_feat_ctl(c); 206 } 207 208 #ifdef CONFIG_X86_32 209 static unsigned int 210 centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size) 211 { 212 /* VIA C3 CPUs (670-68F) need further shifting. */ 213 if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8))) 214 size >>= 8; 215 216 /* 217 * There's also an erratum in Nehemiah stepping 1, which 218 * returns '65KB' instead of '64KB' 219 * - Note, it seems this may only be in engineering samples. 220 */ 221 if ((c->x86 == 6) && (c->x86_model == 9) && 222 (c->x86_stepping == 1) && (size == 65)) 223 size -= 1; 224 return size; 225 } 226 #endif 227 228 static const struct cpu_dev centaur_cpu_dev = { 229 .c_vendor = "Centaur", 230 .c_ident = { "CentaurHauls" }, 231 .c_early_init = early_init_centaur, 232 .c_init = init_centaur, 233 #ifdef CONFIG_X86_32 234 .legacy_cache_size = centaur_size_cache, 235 #endif 236 .c_x86_vendor = X86_VENDOR_CENTAUR, 237 }; 238 239 cpu_dev_register(centaur_cpu_dev); 240