1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 1994 Linus Torvalds 4 * 5 * Cyrix stuff, June 1998 by: 6 * - Rafael R. Reilova (moved everything from head.S), 7 * <rreilova@ececs.uc.edu> 8 * - Channing Corn (tests & fixes), 9 * - Andrew D. Balsa (code cleanup). 10 */ 11 #include <linux/init.h> 12 #include <linux/cpu.h> 13 #include <linux/module.h> 14 #include <linux/nospec.h> 15 #include <linux/prctl.h> 16 #include <linux/sched/smt.h> 17 #include <linux/pgtable.h> 18 #include <linux/bpf.h> 19 20 #include <asm/spec-ctrl.h> 21 #include <asm/cmdline.h> 22 #include <asm/bugs.h> 23 #include <asm/processor.h> 24 #include <asm/processor-flags.h> 25 #include <asm/fpu/api.h> 26 #include <asm/msr.h> 27 #include <asm/vmx.h> 28 #include <asm/paravirt.h> 29 #include <asm/cpu_device_id.h> 30 #include <asm/e820/api.h> 31 #include <asm/hypervisor.h> 32 #include <asm/tlbflush.h> 33 #include <asm/cpu.h> 34 35 #include "cpu.h" 36 37 static void __init spectre_v1_select_mitigation(void); 38 static void __init spectre_v2_select_mitigation(void); 39 static void __init retbleed_select_mitigation(void); 40 static void __init spectre_v2_user_select_mitigation(void); 41 static void __init ssb_select_mitigation(void); 42 static void __init l1tf_select_mitigation(void); 43 static void __init mds_select_mitigation(void); 44 static void __init md_clear_update_mitigation(void); 45 static void __init md_clear_select_mitigation(void); 46 static void __init taa_select_mitigation(void); 47 static void __init mmio_select_mitigation(void); 48 static void __init srbds_select_mitigation(void); 49 static void __init l1d_flush_select_mitigation(void); 50 static void __init srso_select_mitigation(void); 51 static void __init gds_select_mitigation(void); 52 53 /* The base value of the SPEC_CTRL MSR without task-specific bits set */ 54 u64 x86_spec_ctrl_base; 55 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); 56 57 /* The current value of the SPEC_CTRL MSR with task-specific bits set */ 58 DEFINE_PER_CPU(u64, x86_spec_ctrl_current); 59 EXPORT_PER_CPU_SYMBOL_GPL(x86_spec_ctrl_current); 60 61 u64 x86_pred_cmd __ro_after_init = PRED_CMD_IBPB; 62 EXPORT_SYMBOL_GPL(x86_pred_cmd); 63 64 static u64 __ro_after_init x86_arch_cap_msr; 65 66 static DEFINE_MUTEX(spec_ctrl_mutex); 67 68 void (*x86_return_thunk)(void) __ro_after_init = __x86_return_thunk; 69 70 /* Update SPEC_CTRL MSR and its cached copy unconditionally */ 71 static void update_spec_ctrl(u64 val) 72 { 73 this_cpu_write(x86_spec_ctrl_current, val); 74 wrmsrl(MSR_IA32_SPEC_CTRL, val); 75 } 76 77 /* 78 * Keep track of the SPEC_CTRL MSR value for the current task, which may differ 79 * from x86_spec_ctrl_base due to STIBP/SSB in __speculation_ctrl_update(). 80 */ 81 void update_spec_ctrl_cond(u64 val) 82 { 83 if (this_cpu_read(x86_spec_ctrl_current) == val) 84 return; 85 86 this_cpu_write(x86_spec_ctrl_current, val); 87 88 /* 89 * When KERNEL_IBRS this MSR is written on return-to-user, unless 90 * forced the update can be delayed until that time. 91 */ 92 if (!cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS)) 93 wrmsrl(MSR_IA32_SPEC_CTRL, val); 94 } 95 96 noinstr u64 spec_ctrl_current(void) 97 { 98 return this_cpu_read(x86_spec_ctrl_current); 99 } 100 EXPORT_SYMBOL_GPL(spec_ctrl_current); 101 102 /* 103 * AMD specific MSR info for Speculative Store Bypass control. 104 * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). 105 */ 106 u64 __ro_after_init x86_amd_ls_cfg_base; 107 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; 108 109 /* Control conditional STIBP in switch_to() */ 110 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp); 111 /* Control conditional IBPB in switch_mm() */ 112 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb); 113 /* Control unconditional IBPB in switch_mm() */ 114 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb); 115 116 /* Control IBPB on vCPU load */ 117 DEFINE_STATIC_KEY_FALSE(switch_vcpu_ibpb); 118 EXPORT_SYMBOL_GPL(switch_vcpu_ibpb); 119 120 /* Control MDS CPU buffer clear before idling (halt, mwait) */ 121 DEFINE_STATIC_KEY_FALSE(mds_idle_clear); 122 EXPORT_SYMBOL_GPL(mds_idle_clear); 123 124 /* 125 * Controls whether l1d flush based mitigations are enabled, 126 * based on hw features and admin setting via boot parameter 127 * defaults to false 128 */ 129 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush); 130 131 /* Controls CPU Fill buffer clear before KVM guest MMIO accesses */ 132 DEFINE_STATIC_KEY_FALSE(mmio_stale_data_clear); 133 EXPORT_SYMBOL_GPL(mmio_stale_data_clear); 134 135 void __init cpu_select_mitigations(void) 136 { 137 /* 138 * Read the SPEC_CTRL MSR to account for reserved bits which may 139 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD 140 * init code as it is not enumerated and depends on the family. 141 */ 142 if (cpu_feature_enabled(X86_FEATURE_MSR_SPEC_CTRL)) { 143 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); 144 145 /* 146 * Previously running kernel (kexec), may have some controls 147 * turned ON. Clear them and let the mitigations setup below 148 * rediscover them based on configuration. 149 */ 150 x86_spec_ctrl_base &= ~SPEC_CTRL_MITIGATIONS_MASK; 151 } 152 153 x86_arch_cap_msr = x86_read_arch_cap_msr(); 154 155 /* Select the proper CPU mitigations before patching alternatives: */ 156 spectre_v1_select_mitigation(); 157 spectre_v2_select_mitigation(); 158 /* 159 * retbleed_select_mitigation() relies on the state set by 160 * spectre_v2_select_mitigation(); specifically it wants to know about 161 * spectre_v2=ibrs. 162 */ 163 retbleed_select_mitigation(); 164 /* 165 * spectre_v2_user_select_mitigation() relies on the state set by 166 * retbleed_select_mitigation(); specifically the STIBP selection is 167 * forced for UNRET or IBPB. 168 */ 169 spectre_v2_user_select_mitigation(); 170 ssb_select_mitigation(); 171 l1tf_select_mitigation(); 172 md_clear_select_mitigation(); 173 srbds_select_mitigation(); 174 l1d_flush_select_mitigation(); 175 176 /* 177 * srso_select_mitigation() depends and must run after 178 * retbleed_select_mitigation(). 179 */ 180 srso_select_mitigation(); 181 gds_select_mitigation(); 182 } 183 184 /* 185 * NOTE: This function is *only* called for SVM, since Intel uses 186 * MSR_IA32_SPEC_CTRL for SSBD. 187 */ 188 void 189 x86_virt_spec_ctrl(u64 guest_virt_spec_ctrl, bool setguest) 190 { 191 u64 guestval, hostval; 192 struct thread_info *ti = current_thread_info(); 193 194 /* 195 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update 196 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported. 197 */ 198 if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) && 199 !static_cpu_has(X86_FEATURE_VIRT_SSBD)) 200 return; 201 202 /* 203 * If the host has SSBD mitigation enabled, force it in the host's 204 * virtual MSR value. If its not permanently enabled, evaluate 205 * current's TIF_SSBD thread flag. 206 */ 207 if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE)) 208 hostval = SPEC_CTRL_SSBD; 209 else 210 hostval = ssbd_tif_to_spec_ctrl(ti->flags); 211 212 /* Sanitize the guest value */ 213 guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD; 214 215 if (hostval != guestval) { 216 unsigned long tif; 217 218 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) : 219 ssbd_spec_ctrl_to_tif(hostval); 220 221 speculation_ctrl_update(tif); 222 } 223 } 224 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); 225 226 static void x86_amd_ssb_disable(void) 227 { 228 u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; 229 230 if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) 231 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); 232 else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) 233 wrmsrl(MSR_AMD64_LS_CFG, msrval); 234 } 235 236 #undef pr_fmt 237 #define pr_fmt(fmt) "MDS: " fmt 238 239 /* Default mitigation for MDS-affected CPUs */ 240 static enum mds_mitigations mds_mitigation __ro_after_init = 241 IS_ENABLED(CONFIG_MITIGATION_MDS) ? MDS_MITIGATION_AUTO : MDS_MITIGATION_OFF; 242 static bool mds_nosmt __ro_after_init = false; 243 244 static const char * const mds_strings[] = { 245 [MDS_MITIGATION_OFF] = "Vulnerable", 246 [MDS_MITIGATION_FULL] = "Mitigation: Clear CPU buffers", 247 [MDS_MITIGATION_VMWERV] = "Vulnerable: Clear CPU buffers attempted, no microcode", 248 }; 249 250 enum taa_mitigations { 251 TAA_MITIGATION_OFF, 252 TAA_MITIGATION_AUTO, 253 TAA_MITIGATION_UCODE_NEEDED, 254 TAA_MITIGATION_VERW, 255 TAA_MITIGATION_TSX_DISABLED, 256 }; 257 258 /* Default mitigation for TAA-affected CPUs */ 259 static enum taa_mitigations taa_mitigation __ro_after_init = 260 IS_ENABLED(CONFIG_MITIGATION_TAA) ? TAA_MITIGATION_AUTO : TAA_MITIGATION_OFF; 261 262 enum mmio_mitigations { 263 MMIO_MITIGATION_OFF, 264 MMIO_MITIGATION_AUTO, 265 MMIO_MITIGATION_UCODE_NEEDED, 266 MMIO_MITIGATION_VERW, 267 }; 268 269 /* Default mitigation for Processor MMIO Stale Data vulnerabilities */ 270 static enum mmio_mitigations mmio_mitigation __ro_after_init = 271 IS_ENABLED(CONFIG_MITIGATION_MMIO_STALE_DATA) ? MMIO_MITIGATION_AUTO : MMIO_MITIGATION_OFF; 272 273 enum rfds_mitigations { 274 RFDS_MITIGATION_OFF, 275 RFDS_MITIGATION_AUTO, 276 RFDS_MITIGATION_VERW, 277 RFDS_MITIGATION_UCODE_NEEDED, 278 }; 279 280 /* Default mitigation for Register File Data Sampling */ 281 static enum rfds_mitigations rfds_mitigation __ro_after_init = 282 IS_ENABLED(CONFIG_MITIGATION_RFDS) ? RFDS_MITIGATION_AUTO : RFDS_MITIGATION_OFF; 283 284 static void __init mds_select_mitigation(void) 285 { 286 if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) { 287 mds_mitigation = MDS_MITIGATION_OFF; 288 return; 289 } 290 291 if (mds_mitigation == MDS_MITIGATION_AUTO) 292 mds_mitigation = MDS_MITIGATION_FULL; 293 294 if (mds_mitigation == MDS_MITIGATION_FULL) { 295 if (!boot_cpu_has(X86_FEATURE_MD_CLEAR)) 296 mds_mitigation = MDS_MITIGATION_VMWERV; 297 298 setup_force_cpu_cap(X86_FEATURE_CLEAR_CPU_BUF); 299 300 if (!boot_cpu_has(X86_BUG_MSBDS_ONLY) && 301 (mds_nosmt || cpu_mitigations_auto_nosmt())) 302 cpu_smt_disable(false); 303 } 304 } 305 306 static int __init mds_cmdline(char *str) 307 { 308 if (!boot_cpu_has_bug(X86_BUG_MDS)) 309 return 0; 310 311 if (!str) 312 return -EINVAL; 313 314 if (!strcmp(str, "off")) 315 mds_mitigation = MDS_MITIGATION_OFF; 316 else if (!strcmp(str, "full")) 317 mds_mitigation = MDS_MITIGATION_FULL; 318 else if (!strcmp(str, "full,nosmt")) { 319 mds_mitigation = MDS_MITIGATION_FULL; 320 mds_nosmt = true; 321 } 322 323 return 0; 324 } 325 early_param("mds", mds_cmdline); 326 327 #undef pr_fmt 328 #define pr_fmt(fmt) "TAA: " fmt 329 330 static bool taa_nosmt __ro_after_init; 331 332 static const char * const taa_strings[] = { 333 [TAA_MITIGATION_OFF] = "Vulnerable", 334 [TAA_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode", 335 [TAA_MITIGATION_VERW] = "Mitigation: Clear CPU buffers", 336 [TAA_MITIGATION_TSX_DISABLED] = "Mitigation: TSX disabled", 337 }; 338 339 static void __init taa_select_mitigation(void) 340 { 341 if (!boot_cpu_has_bug(X86_BUG_TAA)) { 342 taa_mitigation = TAA_MITIGATION_OFF; 343 return; 344 } 345 346 /* TSX previously disabled by tsx=off */ 347 if (!boot_cpu_has(X86_FEATURE_RTM)) { 348 taa_mitigation = TAA_MITIGATION_TSX_DISABLED; 349 return; 350 } 351 352 if (cpu_mitigations_off()) { 353 taa_mitigation = TAA_MITIGATION_OFF; 354 return; 355 } 356 357 /* 358 * TAA mitigation via VERW is turned off if both 359 * tsx_async_abort=off and mds=off are specified. 360 */ 361 if (taa_mitigation == TAA_MITIGATION_OFF && 362 mds_mitigation == MDS_MITIGATION_OFF) 363 return; 364 365 if (boot_cpu_has(X86_FEATURE_MD_CLEAR)) 366 taa_mitigation = TAA_MITIGATION_VERW; 367 else 368 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED; 369 370 /* 371 * VERW doesn't clear the CPU buffers when MD_CLEAR=1 and MDS_NO=1. 372 * A microcode update fixes this behavior to clear CPU buffers. It also 373 * adds support for MSR_IA32_TSX_CTRL which is enumerated by the 374 * ARCH_CAP_TSX_CTRL_MSR bit. 375 * 376 * On MDS_NO=1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode 377 * update is required. 378 */ 379 if ( (x86_arch_cap_msr & ARCH_CAP_MDS_NO) && 380 !(x86_arch_cap_msr & ARCH_CAP_TSX_CTRL_MSR)) 381 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED; 382 383 /* 384 * TSX is enabled, select alternate mitigation for TAA which is 385 * the same as MDS. Enable MDS static branch to clear CPU buffers. 386 * 387 * For guests that can't determine whether the correct microcode is 388 * present on host, enable the mitigation for UCODE_NEEDED as well. 389 */ 390 setup_force_cpu_cap(X86_FEATURE_CLEAR_CPU_BUF); 391 392 if (taa_nosmt || cpu_mitigations_auto_nosmt()) 393 cpu_smt_disable(false); 394 } 395 396 static int __init tsx_async_abort_parse_cmdline(char *str) 397 { 398 if (!boot_cpu_has_bug(X86_BUG_TAA)) 399 return 0; 400 401 if (!str) 402 return -EINVAL; 403 404 if (!strcmp(str, "off")) { 405 taa_mitigation = TAA_MITIGATION_OFF; 406 } else if (!strcmp(str, "full")) { 407 taa_mitigation = TAA_MITIGATION_VERW; 408 } else if (!strcmp(str, "full,nosmt")) { 409 taa_mitigation = TAA_MITIGATION_VERW; 410 taa_nosmt = true; 411 } 412 413 return 0; 414 } 415 early_param("tsx_async_abort", tsx_async_abort_parse_cmdline); 416 417 #undef pr_fmt 418 #define pr_fmt(fmt) "MMIO Stale Data: " fmt 419 420 static bool mmio_nosmt __ro_after_init = false; 421 422 static const char * const mmio_strings[] = { 423 [MMIO_MITIGATION_OFF] = "Vulnerable", 424 [MMIO_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode", 425 [MMIO_MITIGATION_VERW] = "Mitigation: Clear CPU buffers", 426 }; 427 428 static void __init mmio_select_mitigation(void) 429 { 430 if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA) || 431 boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN) || 432 cpu_mitigations_off()) { 433 mmio_mitigation = MMIO_MITIGATION_OFF; 434 return; 435 } 436 437 if (mmio_mitigation == MMIO_MITIGATION_OFF) 438 return; 439 440 /* 441 * Enable CPU buffer clear mitigation for host and VMM, if also affected 442 * by MDS or TAA. Otherwise, enable mitigation for VMM only. 443 */ 444 if (boot_cpu_has_bug(X86_BUG_MDS) || (boot_cpu_has_bug(X86_BUG_TAA) && 445 boot_cpu_has(X86_FEATURE_RTM))) 446 setup_force_cpu_cap(X86_FEATURE_CLEAR_CPU_BUF); 447 448 /* 449 * X86_FEATURE_CLEAR_CPU_BUF could be enabled by other VERW based 450 * mitigations, disable KVM-only mitigation in that case. 451 */ 452 if (boot_cpu_has(X86_FEATURE_CLEAR_CPU_BUF)) 453 static_branch_disable(&mmio_stale_data_clear); 454 else 455 static_branch_enable(&mmio_stale_data_clear); 456 457 /* 458 * If Processor-MMIO-Stale-Data bug is present and Fill Buffer data can 459 * be propagated to uncore buffers, clearing the Fill buffers on idle 460 * is required irrespective of SMT state. 461 */ 462 if (!(x86_arch_cap_msr & ARCH_CAP_FBSDP_NO)) 463 static_branch_enable(&mds_idle_clear); 464 465 /* 466 * Check if the system has the right microcode. 467 * 468 * CPU Fill buffer clear mitigation is enumerated by either an explicit 469 * FB_CLEAR or by the presence of both MD_CLEAR and L1D_FLUSH on MDS 470 * affected systems. 471 */ 472 if ((x86_arch_cap_msr & ARCH_CAP_FB_CLEAR) || 473 (boot_cpu_has(X86_FEATURE_MD_CLEAR) && 474 boot_cpu_has(X86_FEATURE_FLUSH_L1D) && 475 !(x86_arch_cap_msr & ARCH_CAP_MDS_NO))) 476 mmio_mitigation = MMIO_MITIGATION_VERW; 477 else 478 mmio_mitigation = MMIO_MITIGATION_UCODE_NEEDED; 479 480 if (mmio_nosmt || cpu_mitigations_auto_nosmt()) 481 cpu_smt_disable(false); 482 } 483 484 static int __init mmio_stale_data_parse_cmdline(char *str) 485 { 486 if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) 487 return 0; 488 489 if (!str) 490 return -EINVAL; 491 492 if (!strcmp(str, "off")) { 493 mmio_mitigation = MMIO_MITIGATION_OFF; 494 } else if (!strcmp(str, "full")) { 495 mmio_mitigation = MMIO_MITIGATION_VERW; 496 } else if (!strcmp(str, "full,nosmt")) { 497 mmio_mitigation = MMIO_MITIGATION_VERW; 498 mmio_nosmt = true; 499 } 500 501 return 0; 502 } 503 early_param("mmio_stale_data", mmio_stale_data_parse_cmdline); 504 505 #undef pr_fmt 506 #define pr_fmt(fmt) "Register File Data Sampling: " fmt 507 508 static const char * const rfds_strings[] = { 509 [RFDS_MITIGATION_OFF] = "Vulnerable", 510 [RFDS_MITIGATION_VERW] = "Mitigation: Clear Register File", 511 [RFDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode", 512 }; 513 514 static void __init rfds_select_mitigation(void) 515 { 516 if (!boot_cpu_has_bug(X86_BUG_RFDS) || cpu_mitigations_off()) { 517 rfds_mitigation = RFDS_MITIGATION_OFF; 518 return; 519 } 520 if (rfds_mitigation == RFDS_MITIGATION_OFF) 521 return; 522 523 if (rfds_mitigation == RFDS_MITIGATION_AUTO) 524 rfds_mitigation = RFDS_MITIGATION_VERW; 525 526 if (x86_arch_cap_msr & ARCH_CAP_RFDS_CLEAR) 527 setup_force_cpu_cap(X86_FEATURE_CLEAR_CPU_BUF); 528 else 529 rfds_mitigation = RFDS_MITIGATION_UCODE_NEEDED; 530 } 531 532 static __init int rfds_parse_cmdline(char *str) 533 { 534 if (!str) 535 return -EINVAL; 536 537 if (!boot_cpu_has_bug(X86_BUG_RFDS)) 538 return 0; 539 540 if (!strcmp(str, "off")) 541 rfds_mitigation = RFDS_MITIGATION_OFF; 542 else if (!strcmp(str, "on")) 543 rfds_mitigation = RFDS_MITIGATION_VERW; 544 545 return 0; 546 } 547 early_param("reg_file_data_sampling", rfds_parse_cmdline); 548 549 #undef pr_fmt 550 #define pr_fmt(fmt) "" fmt 551 552 static void __init md_clear_update_mitigation(void) 553 { 554 if (cpu_mitigations_off()) 555 return; 556 557 if (!boot_cpu_has(X86_FEATURE_CLEAR_CPU_BUF)) 558 goto out; 559 560 /* 561 * X86_FEATURE_CLEAR_CPU_BUF is now enabled. Update MDS, TAA and MMIO 562 * Stale Data mitigation, if necessary. 563 */ 564 if (mds_mitigation == MDS_MITIGATION_OFF && 565 boot_cpu_has_bug(X86_BUG_MDS)) { 566 mds_mitigation = MDS_MITIGATION_FULL; 567 mds_select_mitigation(); 568 } 569 if (taa_mitigation == TAA_MITIGATION_OFF && 570 boot_cpu_has_bug(X86_BUG_TAA)) { 571 taa_mitigation = TAA_MITIGATION_VERW; 572 taa_select_mitigation(); 573 } 574 /* 575 * MMIO_MITIGATION_OFF is not checked here so that mmio_stale_data_clear 576 * gets updated correctly as per X86_FEATURE_CLEAR_CPU_BUF state. 577 */ 578 if (boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) { 579 mmio_mitigation = MMIO_MITIGATION_VERW; 580 mmio_select_mitigation(); 581 } 582 if (rfds_mitigation == RFDS_MITIGATION_OFF && 583 boot_cpu_has_bug(X86_BUG_RFDS)) { 584 rfds_mitigation = RFDS_MITIGATION_VERW; 585 rfds_select_mitigation(); 586 } 587 out: 588 if (boot_cpu_has_bug(X86_BUG_MDS)) 589 pr_info("MDS: %s\n", mds_strings[mds_mitigation]); 590 if (boot_cpu_has_bug(X86_BUG_TAA)) 591 pr_info("TAA: %s\n", taa_strings[taa_mitigation]); 592 if (boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) 593 pr_info("MMIO Stale Data: %s\n", mmio_strings[mmio_mitigation]); 594 else if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN)) 595 pr_info("MMIO Stale Data: Unknown: No mitigations\n"); 596 if (boot_cpu_has_bug(X86_BUG_RFDS)) 597 pr_info("Register File Data Sampling: %s\n", rfds_strings[rfds_mitigation]); 598 } 599 600 static void __init md_clear_select_mitigation(void) 601 { 602 mds_select_mitigation(); 603 taa_select_mitigation(); 604 mmio_select_mitigation(); 605 rfds_select_mitigation(); 606 607 /* 608 * As these mitigations are inter-related and rely on VERW instruction 609 * to clear the microarchitural buffers, update and print their status 610 * after mitigation selection is done for each of these vulnerabilities. 611 */ 612 md_clear_update_mitigation(); 613 } 614 615 #undef pr_fmt 616 #define pr_fmt(fmt) "SRBDS: " fmt 617 618 enum srbds_mitigations { 619 SRBDS_MITIGATION_OFF, 620 SRBDS_MITIGATION_UCODE_NEEDED, 621 SRBDS_MITIGATION_FULL, 622 SRBDS_MITIGATION_TSX_OFF, 623 SRBDS_MITIGATION_HYPERVISOR, 624 }; 625 626 static enum srbds_mitigations srbds_mitigation __ro_after_init = 627 IS_ENABLED(CONFIG_MITIGATION_SRBDS) ? SRBDS_MITIGATION_FULL : SRBDS_MITIGATION_OFF; 628 629 static const char * const srbds_strings[] = { 630 [SRBDS_MITIGATION_OFF] = "Vulnerable", 631 [SRBDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode", 632 [SRBDS_MITIGATION_FULL] = "Mitigation: Microcode", 633 [SRBDS_MITIGATION_TSX_OFF] = "Mitigation: TSX disabled", 634 [SRBDS_MITIGATION_HYPERVISOR] = "Unknown: Dependent on hypervisor status", 635 }; 636 637 static bool srbds_off; 638 639 void update_srbds_msr(void) 640 { 641 u64 mcu_ctrl; 642 643 if (!boot_cpu_has_bug(X86_BUG_SRBDS)) 644 return; 645 646 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) 647 return; 648 649 if (srbds_mitigation == SRBDS_MITIGATION_UCODE_NEEDED) 650 return; 651 652 /* 653 * A MDS_NO CPU for which SRBDS mitigation is not needed due to TSX 654 * being disabled and it hasn't received the SRBDS MSR microcode. 655 */ 656 if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL)) 657 return; 658 659 rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); 660 661 switch (srbds_mitigation) { 662 case SRBDS_MITIGATION_OFF: 663 case SRBDS_MITIGATION_TSX_OFF: 664 mcu_ctrl |= RNGDS_MITG_DIS; 665 break; 666 case SRBDS_MITIGATION_FULL: 667 mcu_ctrl &= ~RNGDS_MITG_DIS; 668 break; 669 default: 670 break; 671 } 672 673 wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); 674 } 675 676 static void __init srbds_select_mitigation(void) 677 { 678 if (!boot_cpu_has_bug(X86_BUG_SRBDS)) 679 return; 680 681 /* 682 * Check to see if this is one of the MDS_NO systems supporting TSX that 683 * are only exposed to SRBDS when TSX is enabled or when CPU is affected 684 * by Processor MMIO Stale Data vulnerability. 685 */ 686 if ((x86_arch_cap_msr & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM) && 687 !boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) 688 srbds_mitigation = SRBDS_MITIGATION_TSX_OFF; 689 else if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) 690 srbds_mitigation = SRBDS_MITIGATION_HYPERVISOR; 691 else if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL)) 692 srbds_mitigation = SRBDS_MITIGATION_UCODE_NEEDED; 693 else if (cpu_mitigations_off() || srbds_off) 694 srbds_mitigation = SRBDS_MITIGATION_OFF; 695 696 update_srbds_msr(); 697 pr_info("%s\n", srbds_strings[srbds_mitigation]); 698 } 699 700 static int __init srbds_parse_cmdline(char *str) 701 { 702 if (!str) 703 return -EINVAL; 704 705 if (!boot_cpu_has_bug(X86_BUG_SRBDS)) 706 return 0; 707 708 srbds_off = !strcmp(str, "off"); 709 return 0; 710 } 711 early_param("srbds", srbds_parse_cmdline); 712 713 #undef pr_fmt 714 #define pr_fmt(fmt) "L1D Flush : " fmt 715 716 enum l1d_flush_mitigations { 717 L1D_FLUSH_OFF = 0, 718 L1D_FLUSH_ON, 719 }; 720 721 static enum l1d_flush_mitigations l1d_flush_mitigation __initdata = L1D_FLUSH_OFF; 722 723 static void __init l1d_flush_select_mitigation(void) 724 { 725 if (!l1d_flush_mitigation || !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) 726 return; 727 728 static_branch_enable(&switch_mm_cond_l1d_flush); 729 pr_info("Conditional flush on switch_mm() enabled\n"); 730 } 731 732 static int __init l1d_flush_parse_cmdline(char *str) 733 { 734 if (!strcmp(str, "on")) 735 l1d_flush_mitigation = L1D_FLUSH_ON; 736 737 return 0; 738 } 739 early_param("l1d_flush", l1d_flush_parse_cmdline); 740 741 #undef pr_fmt 742 #define pr_fmt(fmt) "GDS: " fmt 743 744 enum gds_mitigations { 745 GDS_MITIGATION_OFF, 746 GDS_MITIGATION_UCODE_NEEDED, 747 GDS_MITIGATION_FORCE, 748 GDS_MITIGATION_FULL, 749 GDS_MITIGATION_FULL_LOCKED, 750 GDS_MITIGATION_HYPERVISOR, 751 }; 752 753 static enum gds_mitigations gds_mitigation __ro_after_init = 754 IS_ENABLED(CONFIG_MITIGATION_GDS) ? GDS_MITIGATION_FULL : GDS_MITIGATION_OFF; 755 756 static const char * const gds_strings[] = { 757 [GDS_MITIGATION_OFF] = "Vulnerable", 758 [GDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode", 759 [GDS_MITIGATION_FORCE] = "Mitigation: AVX disabled, no microcode", 760 [GDS_MITIGATION_FULL] = "Mitigation: Microcode", 761 [GDS_MITIGATION_FULL_LOCKED] = "Mitigation: Microcode (locked)", 762 [GDS_MITIGATION_HYPERVISOR] = "Unknown: Dependent on hypervisor status", 763 }; 764 765 bool gds_ucode_mitigated(void) 766 { 767 return (gds_mitigation == GDS_MITIGATION_FULL || 768 gds_mitigation == GDS_MITIGATION_FULL_LOCKED); 769 } 770 EXPORT_SYMBOL_GPL(gds_ucode_mitigated); 771 772 void update_gds_msr(void) 773 { 774 u64 mcu_ctrl_after; 775 u64 mcu_ctrl; 776 777 switch (gds_mitigation) { 778 case GDS_MITIGATION_OFF: 779 rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); 780 mcu_ctrl |= GDS_MITG_DIS; 781 break; 782 case GDS_MITIGATION_FULL_LOCKED: 783 /* 784 * The LOCKED state comes from the boot CPU. APs might not have 785 * the same state. Make sure the mitigation is enabled on all 786 * CPUs. 787 */ 788 case GDS_MITIGATION_FULL: 789 rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); 790 mcu_ctrl &= ~GDS_MITG_DIS; 791 break; 792 case GDS_MITIGATION_FORCE: 793 case GDS_MITIGATION_UCODE_NEEDED: 794 case GDS_MITIGATION_HYPERVISOR: 795 return; 796 } 797 798 wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); 799 800 /* 801 * Check to make sure that the WRMSR value was not ignored. Writes to 802 * GDS_MITG_DIS will be ignored if this processor is locked but the boot 803 * processor was not. 804 */ 805 rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl_after); 806 WARN_ON_ONCE(mcu_ctrl != mcu_ctrl_after); 807 } 808 809 static void __init gds_select_mitigation(void) 810 { 811 u64 mcu_ctrl; 812 813 if (!boot_cpu_has_bug(X86_BUG_GDS)) 814 return; 815 816 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { 817 gds_mitigation = GDS_MITIGATION_HYPERVISOR; 818 goto out; 819 } 820 821 if (cpu_mitigations_off()) 822 gds_mitigation = GDS_MITIGATION_OFF; 823 /* Will verify below that mitigation _can_ be disabled */ 824 825 /* No microcode */ 826 if (!(x86_arch_cap_msr & ARCH_CAP_GDS_CTRL)) { 827 if (gds_mitigation == GDS_MITIGATION_FORCE) { 828 /* 829 * This only needs to be done on the boot CPU so do it 830 * here rather than in update_gds_msr() 831 */ 832 setup_clear_cpu_cap(X86_FEATURE_AVX); 833 pr_warn("Microcode update needed! Disabling AVX as mitigation.\n"); 834 } else { 835 gds_mitigation = GDS_MITIGATION_UCODE_NEEDED; 836 } 837 goto out; 838 } 839 840 /* Microcode has mitigation, use it */ 841 if (gds_mitigation == GDS_MITIGATION_FORCE) 842 gds_mitigation = GDS_MITIGATION_FULL; 843 844 rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); 845 if (mcu_ctrl & GDS_MITG_LOCKED) { 846 if (gds_mitigation == GDS_MITIGATION_OFF) 847 pr_warn("Mitigation locked. Disable failed.\n"); 848 849 /* 850 * The mitigation is selected from the boot CPU. All other CPUs 851 * _should_ have the same state. If the boot CPU isn't locked 852 * but others are then update_gds_msr() will WARN() of the state 853 * mismatch. If the boot CPU is locked update_gds_msr() will 854 * ensure the other CPUs have the mitigation enabled. 855 */ 856 gds_mitigation = GDS_MITIGATION_FULL_LOCKED; 857 } 858 859 update_gds_msr(); 860 out: 861 pr_info("%s\n", gds_strings[gds_mitigation]); 862 } 863 864 static int __init gds_parse_cmdline(char *str) 865 { 866 if (!str) 867 return -EINVAL; 868 869 if (!boot_cpu_has_bug(X86_BUG_GDS)) 870 return 0; 871 872 if (!strcmp(str, "off")) 873 gds_mitigation = GDS_MITIGATION_OFF; 874 else if (!strcmp(str, "force")) 875 gds_mitigation = GDS_MITIGATION_FORCE; 876 877 return 0; 878 } 879 early_param("gather_data_sampling", gds_parse_cmdline); 880 881 #undef pr_fmt 882 #define pr_fmt(fmt) "Spectre V1 : " fmt 883 884 enum spectre_v1_mitigation { 885 SPECTRE_V1_MITIGATION_NONE, 886 SPECTRE_V1_MITIGATION_AUTO, 887 }; 888 889 static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init = 890 IS_ENABLED(CONFIG_MITIGATION_SPECTRE_V1) ? 891 SPECTRE_V1_MITIGATION_AUTO : SPECTRE_V1_MITIGATION_NONE; 892 893 static const char * const spectre_v1_strings[] = { 894 [SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers", 895 [SPECTRE_V1_MITIGATION_AUTO] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization", 896 }; 897 898 /* 899 * Does SMAP provide full mitigation against speculative kernel access to 900 * userspace? 901 */ 902 static bool smap_works_speculatively(void) 903 { 904 if (!boot_cpu_has(X86_FEATURE_SMAP)) 905 return false; 906 907 /* 908 * On CPUs which are vulnerable to Meltdown, SMAP does not 909 * prevent speculative access to user data in the L1 cache. 910 * Consider SMAP to be non-functional as a mitigation on these 911 * CPUs. 912 */ 913 if (boot_cpu_has(X86_BUG_CPU_MELTDOWN)) 914 return false; 915 916 return true; 917 } 918 919 static void __init spectre_v1_select_mitigation(void) 920 { 921 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) { 922 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE; 923 return; 924 } 925 926 if (spectre_v1_mitigation == SPECTRE_V1_MITIGATION_AUTO) { 927 /* 928 * With Spectre v1, a user can speculatively control either 929 * path of a conditional swapgs with a user-controlled GS 930 * value. The mitigation is to add lfences to both code paths. 931 * 932 * If FSGSBASE is enabled, the user can put a kernel address in 933 * GS, in which case SMAP provides no protection. 934 * 935 * If FSGSBASE is disabled, the user can only put a user space 936 * address in GS. That makes an attack harder, but still 937 * possible if there's no SMAP protection. 938 */ 939 if (boot_cpu_has(X86_FEATURE_FSGSBASE) || 940 !smap_works_speculatively()) { 941 /* 942 * Mitigation can be provided from SWAPGS itself or 943 * PTI as the CR3 write in the Meltdown mitigation 944 * is serializing. 945 * 946 * If neither is there, mitigate with an LFENCE to 947 * stop speculation through swapgs. 948 */ 949 if (boot_cpu_has_bug(X86_BUG_SWAPGS) && 950 !boot_cpu_has(X86_FEATURE_PTI)) 951 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER); 952 953 /* 954 * Enable lfences in the kernel entry (non-swapgs) 955 * paths, to prevent user entry from speculatively 956 * skipping swapgs. 957 */ 958 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL); 959 } 960 } 961 962 pr_info("%s\n", spectre_v1_strings[spectre_v1_mitigation]); 963 } 964 965 static int __init nospectre_v1_cmdline(char *str) 966 { 967 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE; 968 return 0; 969 } 970 early_param("nospectre_v1", nospectre_v1_cmdline); 971 972 enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = SPECTRE_V2_NONE; 973 974 #undef pr_fmt 975 #define pr_fmt(fmt) "RETBleed: " fmt 976 977 enum retbleed_mitigation { 978 RETBLEED_MITIGATION_NONE, 979 RETBLEED_MITIGATION_UNRET, 980 RETBLEED_MITIGATION_IBPB, 981 RETBLEED_MITIGATION_IBRS, 982 RETBLEED_MITIGATION_EIBRS, 983 RETBLEED_MITIGATION_STUFF, 984 }; 985 986 enum retbleed_mitigation_cmd { 987 RETBLEED_CMD_OFF, 988 RETBLEED_CMD_AUTO, 989 RETBLEED_CMD_UNRET, 990 RETBLEED_CMD_IBPB, 991 RETBLEED_CMD_STUFF, 992 }; 993 994 static const char * const retbleed_strings[] = { 995 [RETBLEED_MITIGATION_NONE] = "Vulnerable", 996 [RETBLEED_MITIGATION_UNRET] = "Mitigation: untrained return thunk", 997 [RETBLEED_MITIGATION_IBPB] = "Mitigation: IBPB", 998 [RETBLEED_MITIGATION_IBRS] = "Mitigation: IBRS", 999 [RETBLEED_MITIGATION_EIBRS] = "Mitigation: Enhanced IBRS", 1000 [RETBLEED_MITIGATION_STUFF] = "Mitigation: Stuffing", 1001 }; 1002 1003 static enum retbleed_mitigation retbleed_mitigation __ro_after_init = 1004 RETBLEED_MITIGATION_NONE; 1005 static enum retbleed_mitigation_cmd retbleed_cmd __ro_after_init = 1006 IS_ENABLED(CONFIG_MITIGATION_RETBLEED) ? RETBLEED_CMD_AUTO : RETBLEED_CMD_OFF; 1007 1008 static int __ro_after_init retbleed_nosmt = false; 1009 1010 static int __init retbleed_parse_cmdline(char *str) 1011 { 1012 if (!str) 1013 return -EINVAL; 1014 1015 while (str) { 1016 char *next = strchr(str, ','); 1017 if (next) { 1018 *next = 0; 1019 next++; 1020 } 1021 1022 if (!strcmp(str, "off")) { 1023 retbleed_cmd = RETBLEED_CMD_OFF; 1024 } else if (!strcmp(str, "auto")) { 1025 retbleed_cmd = RETBLEED_CMD_AUTO; 1026 } else if (!strcmp(str, "unret")) { 1027 retbleed_cmd = RETBLEED_CMD_UNRET; 1028 } else if (!strcmp(str, "ibpb")) { 1029 retbleed_cmd = RETBLEED_CMD_IBPB; 1030 } else if (!strcmp(str, "stuff")) { 1031 retbleed_cmd = RETBLEED_CMD_STUFF; 1032 } else if (!strcmp(str, "nosmt")) { 1033 retbleed_nosmt = true; 1034 } else if (!strcmp(str, "force")) { 1035 setup_force_cpu_bug(X86_BUG_RETBLEED); 1036 } else { 1037 pr_err("Ignoring unknown retbleed option (%s).", str); 1038 } 1039 1040 str = next; 1041 } 1042 1043 return 0; 1044 } 1045 early_param("retbleed", retbleed_parse_cmdline); 1046 1047 #define RETBLEED_UNTRAIN_MSG "WARNING: BTB untrained return thunk mitigation is only effective on AMD/Hygon!\n" 1048 #define RETBLEED_INTEL_MSG "WARNING: Spectre v2 mitigation leaves CPU vulnerable to RETBleed attacks, data leaks possible!\n" 1049 1050 static void __init retbleed_select_mitigation(void) 1051 { 1052 bool mitigate_smt = false; 1053 1054 if (!boot_cpu_has_bug(X86_BUG_RETBLEED) || cpu_mitigations_off()) 1055 return; 1056 1057 switch (retbleed_cmd) { 1058 case RETBLEED_CMD_OFF: 1059 return; 1060 1061 case RETBLEED_CMD_UNRET: 1062 if (IS_ENABLED(CONFIG_MITIGATION_UNRET_ENTRY)) { 1063 retbleed_mitigation = RETBLEED_MITIGATION_UNRET; 1064 } else { 1065 pr_err("WARNING: kernel not compiled with MITIGATION_UNRET_ENTRY.\n"); 1066 goto do_cmd_auto; 1067 } 1068 break; 1069 1070 case RETBLEED_CMD_IBPB: 1071 if (!boot_cpu_has(X86_FEATURE_IBPB)) { 1072 pr_err("WARNING: CPU does not support IBPB.\n"); 1073 goto do_cmd_auto; 1074 } else if (IS_ENABLED(CONFIG_MITIGATION_IBPB_ENTRY)) { 1075 retbleed_mitigation = RETBLEED_MITIGATION_IBPB; 1076 } else { 1077 pr_err("WARNING: kernel not compiled with MITIGATION_IBPB_ENTRY.\n"); 1078 goto do_cmd_auto; 1079 } 1080 break; 1081 1082 case RETBLEED_CMD_STUFF: 1083 if (IS_ENABLED(CONFIG_MITIGATION_CALL_DEPTH_TRACKING) && 1084 spectre_v2_enabled == SPECTRE_V2_RETPOLINE) { 1085 retbleed_mitigation = RETBLEED_MITIGATION_STUFF; 1086 1087 } else { 1088 if (IS_ENABLED(CONFIG_MITIGATION_CALL_DEPTH_TRACKING)) 1089 pr_err("WARNING: retbleed=stuff depends on spectre_v2=retpoline\n"); 1090 else 1091 pr_err("WARNING: kernel not compiled with MITIGATION_CALL_DEPTH_TRACKING.\n"); 1092 1093 goto do_cmd_auto; 1094 } 1095 break; 1096 1097 do_cmd_auto: 1098 case RETBLEED_CMD_AUTO: 1099 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 1100 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) { 1101 if (IS_ENABLED(CONFIG_MITIGATION_UNRET_ENTRY)) 1102 retbleed_mitigation = RETBLEED_MITIGATION_UNRET; 1103 else if (IS_ENABLED(CONFIG_MITIGATION_IBPB_ENTRY) && 1104 boot_cpu_has(X86_FEATURE_IBPB)) 1105 retbleed_mitigation = RETBLEED_MITIGATION_IBPB; 1106 } 1107 1108 /* 1109 * The Intel mitigation (IBRS or eIBRS) was already selected in 1110 * spectre_v2_select_mitigation(). 'retbleed_mitigation' will 1111 * be set accordingly below. 1112 */ 1113 1114 break; 1115 } 1116 1117 switch (retbleed_mitigation) { 1118 case RETBLEED_MITIGATION_UNRET: 1119 setup_force_cpu_cap(X86_FEATURE_RETHUNK); 1120 setup_force_cpu_cap(X86_FEATURE_UNRET); 1121 1122 x86_return_thunk = retbleed_return_thunk; 1123 1124 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD && 1125 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON) 1126 pr_err(RETBLEED_UNTRAIN_MSG); 1127 1128 mitigate_smt = true; 1129 break; 1130 1131 case RETBLEED_MITIGATION_IBPB: 1132 setup_force_cpu_cap(X86_FEATURE_ENTRY_IBPB); 1133 setup_force_cpu_cap(X86_FEATURE_IBPB_ON_VMEXIT); 1134 mitigate_smt = true; 1135 1136 /* 1137 * IBPB on entry already obviates the need for 1138 * software-based untraining so clear those in case some 1139 * other mitigation like SRSO has selected them. 1140 */ 1141 setup_clear_cpu_cap(X86_FEATURE_UNRET); 1142 setup_clear_cpu_cap(X86_FEATURE_RETHUNK); 1143 1144 /* 1145 * There is no need for RSB filling: entry_ibpb() ensures 1146 * all predictions, including the RSB, are invalidated, 1147 * regardless of IBPB implementation. 1148 */ 1149 setup_clear_cpu_cap(X86_FEATURE_RSB_VMEXIT); 1150 1151 break; 1152 1153 case RETBLEED_MITIGATION_STUFF: 1154 setup_force_cpu_cap(X86_FEATURE_RETHUNK); 1155 setup_force_cpu_cap(X86_FEATURE_CALL_DEPTH); 1156 1157 x86_return_thunk = call_depth_return_thunk; 1158 break; 1159 1160 default: 1161 break; 1162 } 1163 1164 if (mitigate_smt && !boot_cpu_has(X86_FEATURE_STIBP) && 1165 (retbleed_nosmt || cpu_mitigations_auto_nosmt())) 1166 cpu_smt_disable(false); 1167 1168 /* 1169 * Let IBRS trump all on Intel without affecting the effects of the 1170 * retbleed= cmdline option except for call depth based stuffing 1171 */ 1172 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) { 1173 switch (spectre_v2_enabled) { 1174 case SPECTRE_V2_IBRS: 1175 retbleed_mitigation = RETBLEED_MITIGATION_IBRS; 1176 break; 1177 case SPECTRE_V2_EIBRS: 1178 case SPECTRE_V2_EIBRS_RETPOLINE: 1179 case SPECTRE_V2_EIBRS_LFENCE: 1180 retbleed_mitigation = RETBLEED_MITIGATION_EIBRS; 1181 break; 1182 default: 1183 if (retbleed_mitigation != RETBLEED_MITIGATION_STUFF) 1184 pr_err(RETBLEED_INTEL_MSG); 1185 } 1186 } 1187 1188 pr_info("%s\n", retbleed_strings[retbleed_mitigation]); 1189 } 1190 1191 #undef pr_fmt 1192 #define pr_fmt(fmt) "Spectre V2 : " fmt 1193 1194 static enum spectre_v2_user_mitigation spectre_v2_user_stibp __ro_after_init = 1195 SPECTRE_V2_USER_NONE; 1196 static enum spectre_v2_user_mitigation spectre_v2_user_ibpb __ro_after_init = 1197 SPECTRE_V2_USER_NONE; 1198 1199 #ifdef CONFIG_MITIGATION_RETPOLINE 1200 static bool spectre_v2_bad_module; 1201 1202 bool retpoline_module_ok(bool has_retpoline) 1203 { 1204 if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) 1205 return true; 1206 1207 pr_err("System may be vulnerable to spectre v2\n"); 1208 spectre_v2_bad_module = true; 1209 return false; 1210 } 1211 1212 static inline const char *spectre_v2_module_string(void) 1213 { 1214 return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; 1215 } 1216 #else 1217 static inline const char *spectre_v2_module_string(void) { return ""; } 1218 #endif 1219 1220 #define SPECTRE_V2_LFENCE_MSG "WARNING: LFENCE mitigation is not recommended for this CPU, data leaks possible!\n" 1221 #define SPECTRE_V2_EIBRS_EBPF_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS on, data leaks possible via Spectre v2 BHB attacks!\n" 1222 #define SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS+LFENCE mitigation and SMT, data leaks possible via Spectre v2 BHB attacks!\n" 1223 #define SPECTRE_V2_IBRS_PERF_MSG "WARNING: IBRS mitigation selected on Enhanced IBRS CPU, this may cause unnecessary performance loss\n" 1224 1225 #ifdef CONFIG_BPF_SYSCALL 1226 void unpriv_ebpf_notify(int new_state) 1227 { 1228 if (new_state) 1229 return; 1230 1231 /* Unprivileged eBPF is enabled */ 1232 1233 switch (spectre_v2_enabled) { 1234 case SPECTRE_V2_EIBRS: 1235 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG); 1236 break; 1237 case SPECTRE_V2_EIBRS_LFENCE: 1238 if (sched_smt_active()) 1239 pr_err(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG); 1240 break; 1241 default: 1242 break; 1243 } 1244 } 1245 #endif 1246 1247 static inline bool match_option(const char *arg, int arglen, const char *opt) 1248 { 1249 int len = strlen(opt); 1250 1251 return len == arglen && !strncmp(arg, opt, len); 1252 } 1253 1254 /* The kernel command line selection for spectre v2 */ 1255 enum spectre_v2_mitigation_cmd { 1256 SPECTRE_V2_CMD_NONE, 1257 SPECTRE_V2_CMD_AUTO, 1258 SPECTRE_V2_CMD_FORCE, 1259 SPECTRE_V2_CMD_RETPOLINE, 1260 SPECTRE_V2_CMD_RETPOLINE_GENERIC, 1261 SPECTRE_V2_CMD_RETPOLINE_LFENCE, 1262 SPECTRE_V2_CMD_EIBRS, 1263 SPECTRE_V2_CMD_EIBRS_RETPOLINE, 1264 SPECTRE_V2_CMD_EIBRS_LFENCE, 1265 SPECTRE_V2_CMD_IBRS, 1266 }; 1267 1268 enum spectre_v2_user_cmd { 1269 SPECTRE_V2_USER_CMD_NONE, 1270 SPECTRE_V2_USER_CMD_AUTO, 1271 SPECTRE_V2_USER_CMD_FORCE, 1272 SPECTRE_V2_USER_CMD_PRCTL, 1273 SPECTRE_V2_USER_CMD_PRCTL_IBPB, 1274 SPECTRE_V2_USER_CMD_SECCOMP, 1275 SPECTRE_V2_USER_CMD_SECCOMP_IBPB, 1276 }; 1277 1278 static const char * const spectre_v2_user_strings[] = { 1279 [SPECTRE_V2_USER_NONE] = "User space: Vulnerable", 1280 [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection", 1281 [SPECTRE_V2_USER_STRICT_PREFERRED] = "User space: Mitigation: STIBP always-on protection", 1282 [SPECTRE_V2_USER_PRCTL] = "User space: Mitigation: STIBP via prctl", 1283 [SPECTRE_V2_USER_SECCOMP] = "User space: Mitigation: STIBP via seccomp and prctl", 1284 }; 1285 1286 static const struct { 1287 const char *option; 1288 enum spectre_v2_user_cmd cmd; 1289 bool secure; 1290 } v2_user_options[] __initconst = { 1291 { "auto", SPECTRE_V2_USER_CMD_AUTO, false }, 1292 { "off", SPECTRE_V2_USER_CMD_NONE, false }, 1293 { "on", SPECTRE_V2_USER_CMD_FORCE, true }, 1294 { "prctl", SPECTRE_V2_USER_CMD_PRCTL, false }, 1295 { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB, false }, 1296 { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP, false }, 1297 { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB, false }, 1298 }; 1299 1300 static void __init spec_v2_user_print_cond(const char *reason, bool secure) 1301 { 1302 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) 1303 pr_info("spectre_v2_user=%s forced on command line.\n", reason); 1304 } 1305 1306 static __ro_after_init enum spectre_v2_mitigation_cmd spectre_v2_cmd; 1307 1308 static enum spectre_v2_user_cmd __init 1309 spectre_v2_parse_user_cmdline(void) 1310 { 1311 enum spectre_v2_user_cmd mode; 1312 char arg[20]; 1313 int ret, i; 1314 1315 mode = IS_ENABLED(CONFIG_MITIGATION_SPECTRE_V2) ? 1316 SPECTRE_V2_USER_CMD_AUTO : SPECTRE_V2_USER_CMD_NONE; 1317 1318 switch (spectre_v2_cmd) { 1319 case SPECTRE_V2_CMD_NONE: 1320 return SPECTRE_V2_USER_CMD_NONE; 1321 case SPECTRE_V2_CMD_FORCE: 1322 return SPECTRE_V2_USER_CMD_FORCE; 1323 default: 1324 break; 1325 } 1326 1327 ret = cmdline_find_option(boot_command_line, "spectre_v2_user", 1328 arg, sizeof(arg)); 1329 if (ret < 0) 1330 return mode; 1331 1332 for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) { 1333 if (match_option(arg, ret, v2_user_options[i].option)) { 1334 spec_v2_user_print_cond(v2_user_options[i].option, 1335 v2_user_options[i].secure); 1336 return v2_user_options[i].cmd; 1337 } 1338 } 1339 1340 pr_err("Unknown user space protection option (%s). Switching to default\n", arg); 1341 return mode; 1342 } 1343 1344 static inline bool spectre_v2_in_ibrs_mode(enum spectre_v2_mitigation mode) 1345 { 1346 return spectre_v2_in_eibrs_mode(mode) || mode == SPECTRE_V2_IBRS; 1347 } 1348 1349 static void __init 1350 spectre_v2_user_select_mitigation(void) 1351 { 1352 enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE; 1353 enum spectre_v2_user_cmd cmd; 1354 1355 if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP)) 1356 return; 1357 1358 cmd = spectre_v2_parse_user_cmdline(); 1359 switch (cmd) { 1360 case SPECTRE_V2_USER_CMD_NONE: 1361 goto set_mode; 1362 case SPECTRE_V2_USER_CMD_FORCE: 1363 mode = SPECTRE_V2_USER_STRICT; 1364 break; 1365 case SPECTRE_V2_USER_CMD_AUTO: 1366 case SPECTRE_V2_USER_CMD_PRCTL: 1367 case SPECTRE_V2_USER_CMD_PRCTL_IBPB: 1368 mode = SPECTRE_V2_USER_PRCTL; 1369 break; 1370 case SPECTRE_V2_USER_CMD_SECCOMP: 1371 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: 1372 if (IS_ENABLED(CONFIG_SECCOMP)) 1373 mode = SPECTRE_V2_USER_SECCOMP; 1374 else 1375 mode = SPECTRE_V2_USER_PRCTL; 1376 break; 1377 } 1378 1379 /* Initialize Indirect Branch Prediction Barrier */ 1380 if (boot_cpu_has(X86_FEATURE_IBPB)) { 1381 static_branch_enable(&switch_vcpu_ibpb); 1382 1383 spectre_v2_user_ibpb = mode; 1384 switch (cmd) { 1385 case SPECTRE_V2_USER_CMD_NONE: 1386 break; 1387 case SPECTRE_V2_USER_CMD_FORCE: 1388 case SPECTRE_V2_USER_CMD_PRCTL_IBPB: 1389 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: 1390 static_branch_enable(&switch_mm_always_ibpb); 1391 spectre_v2_user_ibpb = SPECTRE_V2_USER_STRICT; 1392 break; 1393 case SPECTRE_V2_USER_CMD_PRCTL: 1394 case SPECTRE_V2_USER_CMD_AUTO: 1395 case SPECTRE_V2_USER_CMD_SECCOMP: 1396 static_branch_enable(&switch_mm_cond_ibpb); 1397 break; 1398 } 1399 1400 pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n", 1401 static_key_enabled(&switch_mm_always_ibpb) ? 1402 "always-on" : "conditional"); 1403 } 1404 1405 /* 1406 * If no STIBP, Intel enhanced IBRS is enabled, or SMT impossible, STIBP 1407 * is not required. 1408 * 1409 * Intel's Enhanced IBRS also protects against cross-thread branch target 1410 * injection in user-mode as the IBRS bit remains always set which 1411 * implicitly enables cross-thread protections. However, in legacy IBRS 1412 * mode, the IBRS bit is set only on kernel entry and cleared on return 1413 * to userspace. AMD Automatic IBRS also does not protect userspace. 1414 * These modes therefore disable the implicit cross-thread protection, 1415 * so allow for STIBP to be selected in those cases. 1416 */ 1417 if (!boot_cpu_has(X86_FEATURE_STIBP) || 1418 !cpu_smt_possible() || 1419 (spectre_v2_in_eibrs_mode(spectre_v2_enabled) && 1420 !boot_cpu_has(X86_FEATURE_AUTOIBRS))) 1421 return; 1422 1423 /* 1424 * At this point, an STIBP mode other than "off" has been set. 1425 * If STIBP support is not being forced, check if STIBP always-on 1426 * is preferred. 1427 */ 1428 if (mode != SPECTRE_V2_USER_STRICT && 1429 boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON)) 1430 mode = SPECTRE_V2_USER_STRICT_PREFERRED; 1431 1432 if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET || 1433 retbleed_mitigation == RETBLEED_MITIGATION_IBPB) { 1434 if (mode != SPECTRE_V2_USER_STRICT && 1435 mode != SPECTRE_V2_USER_STRICT_PREFERRED) 1436 pr_info("Selecting STIBP always-on mode to complement retbleed mitigation\n"); 1437 mode = SPECTRE_V2_USER_STRICT_PREFERRED; 1438 } 1439 1440 spectre_v2_user_stibp = mode; 1441 1442 set_mode: 1443 pr_info("%s\n", spectre_v2_user_strings[mode]); 1444 } 1445 1446 static const char * const spectre_v2_strings[] = { 1447 [SPECTRE_V2_NONE] = "Vulnerable", 1448 [SPECTRE_V2_RETPOLINE] = "Mitigation: Retpolines", 1449 [SPECTRE_V2_LFENCE] = "Mitigation: LFENCE", 1450 [SPECTRE_V2_EIBRS] = "Mitigation: Enhanced / Automatic IBRS", 1451 [SPECTRE_V2_EIBRS_LFENCE] = "Mitigation: Enhanced / Automatic IBRS + LFENCE", 1452 [SPECTRE_V2_EIBRS_RETPOLINE] = "Mitigation: Enhanced / Automatic IBRS + Retpolines", 1453 [SPECTRE_V2_IBRS] = "Mitigation: IBRS", 1454 }; 1455 1456 static const struct { 1457 const char *option; 1458 enum spectre_v2_mitigation_cmd cmd; 1459 bool secure; 1460 } mitigation_options[] __initconst = { 1461 { "off", SPECTRE_V2_CMD_NONE, false }, 1462 { "on", SPECTRE_V2_CMD_FORCE, true }, 1463 { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, 1464 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_LFENCE, false }, 1465 { "retpoline,lfence", SPECTRE_V2_CMD_RETPOLINE_LFENCE, false }, 1466 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, 1467 { "eibrs", SPECTRE_V2_CMD_EIBRS, false }, 1468 { "eibrs,lfence", SPECTRE_V2_CMD_EIBRS_LFENCE, false }, 1469 { "eibrs,retpoline", SPECTRE_V2_CMD_EIBRS_RETPOLINE, false }, 1470 { "auto", SPECTRE_V2_CMD_AUTO, false }, 1471 { "ibrs", SPECTRE_V2_CMD_IBRS, false }, 1472 }; 1473 1474 static void __init spec_v2_print_cond(const char *reason, bool secure) 1475 { 1476 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) 1477 pr_info("%s selected on command line.\n", reason); 1478 } 1479 1480 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) 1481 { 1482 enum spectre_v2_mitigation_cmd cmd; 1483 char arg[20]; 1484 int ret, i; 1485 1486 cmd = IS_ENABLED(CONFIG_MITIGATION_SPECTRE_V2) ? SPECTRE_V2_CMD_AUTO : SPECTRE_V2_CMD_NONE; 1487 if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") || 1488 cpu_mitigations_off()) 1489 return SPECTRE_V2_CMD_NONE; 1490 1491 ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); 1492 if (ret < 0) 1493 return cmd; 1494 1495 for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { 1496 if (!match_option(arg, ret, mitigation_options[i].option)) 1497 continue; 1498 cmd = mitigation_options[i].cmd; 1499 break; 1500 } 1501 1502 if (i >= ARRAY_SIZE(mitigation_options)) { 1503 pr_err("unknown option (%s). Switching to default mode\n", arg); 1504 return cmd; 1505 } 1506 1507 if ((cmd == SPECTRE_V2_CMD_RETPOLINE || 1508 cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE || 1509 cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC || 1510 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE || 1511 cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) && 1512 !IS_ENABLED(CONFIG_MITIGATION_RETPOLINE)) { 1513 pr_err("%s selected but not compiled in. Switching to AUTO select\n", 1514 mitigation_options[i].option); 1515 return SPECTRE_V2_CMD_AUTO; 1516 } 1517 1518 if ((cmd == SPECTRE_V2_CMD_EIBRS || 1519 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE || 1520 cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) && 1521 !boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { 1522 pr_err("%s selected but CPU doesn't have Enhanced or Automatic IBRS. Switching to AUTO select\n", 1523 mitigation_options[i].option); 1524 return SPECTRE_V2_CMD_AUTO; 1525 } 1526 1527 if ((cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE || 1528 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE) && 1529 !boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { 1530 pr_err("%s selected, but CPU doesn't have a serializing LFENCE. Switching to AUTO select\n", 1531 mitigation_options[i].option); 1532 return SPECTRE_V2_CMD_AUTO; 1533 } 1534 1535 if (cmd == SPECTRE_V2_CMD_IBRS && !IS_ENABLED(CONFIG_MITIGATION_IBRS_ENTRY)) { 1536 pr_err("%s selected but not compiled in. Switching to AUTO select\n", 1537 mitigation_options[i].option); 1538 return SPECTRE_V2_CMD_AUTO; 1539 } 1540 1541 if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) { 1542 pr_err("%s selected but not Intel CPU. Switching to AUTO select\n", 1543 mitigation_options[i].option); 1544 return SPECTRE_V2_CMD_AUTO; 1545 } 1546 1547 if (cmd == SPECTRE_V2_CMD_IBRS && !boot_cpu_has(X86_FEATURE_IBRS)) { 1548 pr_err("%s selected but CPU doesn't have IBRS. Switching to AUTO select\n", 1549 mitigation_options[i].option); 1550 return SPECTRE_V2_CMD_AUTO; 1551 } 1552 1553 if (cmd == SPECTRE_V2_CMD_IBRS && cpu_feature_enabled(X86_FEATURE_XENPV)) { 1554 pr_err("%s selected but running as XenPV guest. Switching to AUTO select\n", 1555 mitigation_options[i].option); 1556 return SPECTRE_V2_CMD_AUTO; 1557 } 1558 1559 spec_v2_print_cond(mitigation_options[i].option, 1560 mitigation_options[i].secure); 1561 return cmd; 1562 } 1563 1564 static enum spectre_v2_mitigation __init spectre_v2_select_retpoline(void) 1565 { 1566 if (!IS_ENABLED(CONFIG_MITIGATION_RETPOLINE)) { 1567 pr_err("Kernel not compiled with retpoline; no mitigation available!"); 1568 return SPECTRE_V2_NONE; 1569 } 1570 1571 return SPECTRE_V2_RETPOLINE; 1572 } 1573 1574 static bool __ro_after_init rrsba_disabled; 1575 1576 /* Disable in-kernel use of non-RSB RET predictors */ 1577 static void __init spec_ctrl_disable_kernel_rrsba(void) 1578 { 1579 if (rrsba_disabled) 1580 return; 1581 1582 if (!(x86_arch_cap_msr & ARCH_CAP_RRSBA)) { 1583 rrsba_disabled = true; 1584 return; 1585 } 1586 1587 if (!boot_cpu_has(X86_FEATURE_RRSBA_CTRL)) 1588 return; 1589 1590 x86_spec_ctrl_base |= SPEC_CTRL_RRSBA_DIS_S; 1591 update_spec_ctrl(x86_spec_ctrl_base); 1592 rrsba_disabled = true; 1593 } 1594 1595 static void __init spectre_v2_determine_rsb_fill_type_at_vmexit(enum spectre_v2_mitigation mode) 1596 { 1597 /* 1598 * Similar to context switches, there are two types of RSB attacks 1599 * after VM exit: 1600 * 1601 * 1) RSB underflow 1602 * 1603 * 2) Poisoned RSB entry 1604 * 1605 * When retpoline is enabled, both are mitigated by filling/clearing 1606 * the RSB. 1607 * 1608 * When IBRS is enabled, while #1 would be mitigated by the IBRS branch 1609 * prediction isolation protections, RSB still needs to be cleared 1610 * because of #2. Note that SMEP provides no protection here, unlike 1611 * user-space-poisoned RSB entries. 1612 * 1613 * eIBRS should protect against RSB poisoning, but if the EIBRS_PBRSB 1614 * bug is present then a LITE version of RSB protection is required, 1615 * just a single call needs to retire before a RET is executed. 1616 */ 1617 switch (mode) { 1618 case SPECTRE_V2_NONE: 1619 return; 1620 1621 case SPECTRE_V2_EIBRS_LFENCE: 1622 case SPECTRE_V2_EIBRS: 1623 if (boot_cpu_has_bug(X86_BUG_EIBRS_PBRSB)) { 1624 setup_force_cpu_cap(X86_FEATURE_RSB_VMEXIT_LITE); 1625 pr_info("Spectre v2 / PBRSB-eIBRS: Retire a single CALL on VMEXIT\n"); 1626 } 1627 return; 1628 1629 case SPECTRE_V2_EIBRS_RETPOLINE: 1630 case SPECTRE_V2_RETPOLINE: 1631 case SPECTRE_V2_LFENCE: 1632 case SPECTRE_V2_IBRS: 1633 setup_force_cpu_cap(X86_FEATURE_RSB_VMEXIT); 1634 pr_info("Spectre v2 / SpectreRSB : Filling RSB on VMEXIT\n"); 1635 return; 1636 } 1637 1638 pr_warn_once("Unknown Spectre v2 mode, disabling RSB mitigation at VM exit"); 1639 dump_stack(); 1640 } 1641 1642 /* 1643 * Set BHI_DIS_S to prevent indirect branches in kernel to be influenced by 1644 * branch history in userspace. Not needed if BHI_NO is set. 1645 */ 1646 static bool __init spec_ctrl_bhi_dis(void) 1647 { 1648 if (!boot_cpu_has(X86_FEATURE_BHI_CTRL)) 1649 return false; 1650 1651 x86_spec_ctrl_base |= SPEC_CTRL_BHI_DIS_S; 1652 update_spec_ctrl(x86_spec_ctrl_base); 1653 setup_force_cpu_cap(X86_FEATURE_CLEAR_BHB_HW); 1654 1655 return true; 1656 } 1657 1658 enum bhi_mitigations { 1659 BHI_MITIGATION_OFF, 1660 BHI_MITIGATION_ON, 1661 BHI_MITIGATION_VMEXIT_ONLY, 1662 }; 1663 1664 static enum bhi_mitigations bhi_mitigation __ro_after_init = 1665 IS_ENABLED(CONFIG_MITIGATION_SPECTRE_BHI) ? BHI_MITIGATION_ON : BHI_MITIGATION_OFF; 1666 1667 static int __init spectre_bhi_parse_cmdline(char *str) 1668 { 1669 if (!str) 1670 return -EINVAL; 1671 1672 if (!strcmp(str, "off")) 1673 bhi_mitigation = BHI_MITIGATION_OFF; 1674 else if (!strcmp(str, "on")) 1675 bhi_mitigation = BHI_MITIGATION_ON; 1676 else if (!strcmp(str, "vmexit")) 1677 bhi_mitigation = BHI_MITIGATION_VMEXIT_ONLY; 1678 else 1679 pr_err("Ignoring unknown spectre_bhi option (%s)", str); 1680 1681 return 0; 1682 } 1683 early_param("spectre_bhi", spectre_bhi_parse_cmdline); 1684 1685 static void __init bhi_select_mitigation(void) 1686 { 1687 if (bhi_mitigation == BHI_MITIGATION_OFF) 1688 return; 1689 1690 /* Retpoline mitigates against BHI unless the CPU has RRSBA behavior */ 1691 if (boot_cpu_has(X86_FEATURE_RETPOLINE) && 1692 !boot_cpu_has(X86_FEATURE_RETPOLINE_LFENCE)) { 1693 spec_ctrl_disable_kernel_rrsba(); 1694 if (rrsba_disabled) 1695 return; 1696 } 1697 1698 /* Mitigate in hardware if supported */ 1699 if (spec_ctrl_bhi_dis()) 1700 return; 1701 1702 if (!IS_ENABLED(CONFIG_X86_64)) 1703 return; 1704 1705 if (bhi_mitigation == BHI_MITIGATION_VMEXIT_ONLY) { 1706 pr_info("Spectre BHI mitigation: SW BHB clearing on VM exit only\n"); 1707 setup_force_cpu_cap(X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT); 1708 return; 1709 } 1710 1711 pr_info("Spectre BHI mitigation: SW BHB clearing on syscall and VM exit\n"); 1712 setup_force_cpu_cap(X86_FEATURE_CLEAR_BHB_LOOP); 1713 setup_force_cpu_cap(X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT); 1714 } 1715 1716 static void __init spectre_v2_select_mitigation(void) 1717 { 1718 enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); 1719 enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; 1720 1721 /* 1722 * If the CPU is not affected and the command line mode is NONE or AUTO 1723 * then nothing to do. 1724 */ 1725 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && 1726 (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) 1727 return; 1728 1729 switch (cmd) { 1730 case SPECTRE_V2_CMD_NONE: 1731 return; 1732 1733 case SPECTRE_V2_CMD_FORCE: 1734 case SPECTRE_V2_CMD_AUTO: 1735 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { 1736 mode = SPECTRE_V2_EIBRS; 1737 break; 1738 } 1739 1740 if (IS_ENABLED(CONFIG_MITIGATION_IBRS_ENTRY) && 1741 boot_cpu_has_bug(X86_BUG_RETBLEED) && 1742 retbleed_cmd != RETBLEED_CMD_OFF && 1743 retbleed_cmd != RETBLEED_CMD_STUFF && 1744 boot_cpu_has(X86_FEATURE_IBRS) && 1745 boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) { 1746 mode = SPECTRE_V2_IBRS; 1747 break; 1748 } 1749 1750 mode = spectre_v2_select_retpoline(); 1751 break; 1752 1753 case SPECTRE_V2_CMD_RETPOLINE_LFENCE: 1754 pr_err(SPECTRE_V2_LFENCE_MSG); 1755 mode = SPECTRE_V2_LFENCE; 1756 break; 1757 1758 case SPECTRE_V2_CMD_RETPOLINE_GENERIC: 1759 mode = SPECTRE_V2_RETPOLINE; 1760 break; 1761 1762 case SPECTRE_V2_CMD_RETPOLINE: 1763 mode = spectre_v2_select_retpoline(); 1764 break; 1765 1766 case SPECTRE_V2_CMD_IBRS: 1767 mode = SPECTRE_V2_IBRS; 1768 break; 1769 1770 case SPECTRE_V2_CMD_EIBRS: 1771 mode = SPECTRE_V2_EIBRS; 1772 break; 1773 1774 case SPECTRE_V2_CMD_EIBRS_LFENCE: 1775 mode = SPECTRE_V2_EIBRS_LFENCE; 1776 break; 1777 1778 case SPECTRE_V2_CMD_EIBRS_RETPOLINE: 1779 mode = SPECTRE_V2_EIBRS_RETPOLINE; 1780 break; 1781 } 1782 1783 if (mode == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled()) 1784 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG); 1785 1786 if (spectre_v2_in_ibrs_mode(mode)) { 1787 if (boot_cpu_has(X86_FEATURE_AUTOIBRS)) { 1788 msr_set_bit(MSR_EFER, _EFER_AUTOIBRS); 1789 } else { 1790 x86_spec_ctrl_base |= SPEC_CTRL_IBRS; 1791 update_spec_ctrl(x86_spec_ctrl_base); 1792 } 1793 } 1794 1795 switch (mode) { 1796 case SPECTRE_V2_NONE: 1797 case SPECTRE_V2_EIBRS: 1798 break; 1799 1800 case SPECTRE_V2_IBRS: 1801 setup_force_cpu_cap(X86_FEATURE_KERNEL_IBRS); 1802 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) 1803 pr_warn(SPECTRE_V2_IBRS_PERF_MSG); 1804 break; 1805 1806 case SPECTRE_V2_LFENCE: 1807 case SPECTRE_V2_EIBRS_LFENCE: 1808 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_LFENCE); 1809 fallthrough; 1810 1811 case SPECTRE_V2_RETPOLINE: 1812 case SPECTRE_V2_EIBRS_RETPOLINE: 1813 setup_force_cpu_cap(X86_FEATURE_RETPOLINE); 1814 break; 1815 } 1816 1817 /* 1818 * Disable alternate RSB predictions in kernel when indirect CALLs and 1819 * JMPs gets protection against BHI and Intramode-BTI, but RET 1820 * prediction from a non-RSB predictor is still a risk. 1821 */ 1822 if (mode == SPECTRE_V2_EIBRS_LFENCE || 1823 mode == SPECTRE_V2_EIBRS_RETPOLINE || 1824 mode == SPECTRE_V2_RETPOLINE) 1825 spec_ctrl_disable_kernel_rrsba(); 1826 1827 if (boot_cpu_has(X86_BUG_BHI)) 1828 bhi_select_mitigation(); 1829 1830 spectre_v2_enabled = mode; 1831 pr_info("%s\n", spectre_v2_strings[mode]); 1832 1833 /* 1834 * If Spectre v2 protection has been enabled, fill the RSB during a 1835 * context switch. In general there are two types of RSB attacks 1836 * across context switches, for which the CALLs/RETs may be unbalanced. 1837 * 1838 * 1) RSB underflow 1839 * 1840 * Some Intel parts have "bottomless RSB". When the RSB is empty, 1841 * speculated return targets may come from the branch predictor, 1842 * which could have a user-poisoned BTB or BHB entry. 1843 * 1844 * AMD has it even worse: *all* returns are speculated from the BTB, 1845 * regardless of the state of the RSB. 1846 * 1847 * When IBRS or eIBRS is enabled, the "user -> kernel" attack 1848 * scenario is mitigated by the IBRS branch prediction isolation 1849 * properties, so the RSB buffer filling wouldn't be necessary to 1850 * protect against this type of attack. 1851 * 1852 * The "user -> user" attack scenario is mitigated by RSB filling. 1853 * 1854 * 2) Poisoned RSB entry 1855 * 1856 * If the 'next' in-kernel return stack is shorter than 'prev', 1857 * 'next' could be tricked into speculating with a user-poisoned RSB 1858 * entry. 1859 * 1860 * The "user -> kernel" attack scenario is mitigated by SMEP and 1861 * eIBRS. 1862 * 1863 * The "user -> user" scenario, also known as SpectreBHB, requires 1864 * RSB clearing. 1865 * 1866 * So to mitigate all cases, unconditionally fill RSB on context 1867 * switches. 1868 * 1869 * FIXME: Is this pointless for retbleed-affected AMD? 1870 */ 1871 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); 1872 pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n"); 1873 1874 spectre_v2_determine_rsb_fill_type_at_vmexit(mode); 1875 1876 /* 1877 * Retpoline protects the kernel, but doesn't protect firmware. IBRS 1878 * and Enhanced IBRS protect firmware too, so enable IBRS around 1879 * firmware calls only when IBRS / Enhanced / Automatic IBRS aren't 1880 * otherwise enabled. 1881 * 1882 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because 1883 * the user might select retpoline on the kernel command line and if 1884 * the CPU supports Enhanced IBRS, kernel might un-intentionally not 1885 * enable IBRS around firmware calls. 1886 */ 1887 if (boot_cpu_has_bug(X86_BUG_RETBLEED) && 1888 boot_cpu_has(X86_FEATURE_IBPB) && 1889 (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 1890 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)) { 1891 1892 if (retbleed_cmd != RETBLEED_CMD_IBPB) { 1893 setup_force_cpu_cap(X86_FEATURE_USE_IBPB_FW); 1894 pr_info("Enabling Speculation Barrier for firmware calls\n"); 1895 } 1896 1897 } else if (boot_cpu_has(X86_FEATURE_IBRS) && !spectre_v2_in_ibrs_mode(mode)) { 1898 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); 1899 pr_info("Enabling Restricted Speculation for firmware calls\n"); 1900 } 1901 1902 /* Set up IBPB and STIBP depending on the general spectre V2 command */ 1903 spectre_v2_cmd = cmd; 1904 } 1905 1906 static void update_stibp_msr(void * __unused) 1907 { 1908 u64 val = spec_ctrl_current() | (x86_spec_ctrl_base & SPEC_CTRL_STIBP); 1909 update_spec_ctrl(val); 1910 } 1911 1912 /* Update x86_spec_ctrl_base in case SMT state changed. */ 1913 static void update_stibp_strict(void) 1914 { 1915 u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP; 1916 1917 if (sched_smt_active()) 1918 mask |= SPEC_CTRL_STIBP; 1919 1920 if (mask == x86_spec_ctrl_base) 1921 return; 1922 1923 pr_info("Update user space SMT mitigation: STIBP %s\n", 1924 mask & SPEC_CTRL_STIBP ? "always-on" : "off"); 1925 x86_spec_ctrl_base = mask; 1926 on_each_cpu(update_stibp_msr, NULL, 1); 1927 } 1928 1929 /* Update the static key controlling the evaluation of TIF_SPEC_IB */ 1930 static void update_indir_branch_cond(void) 1931 { 1932 if (sched_smt_active()) 1933 static_branch_enable(&switch_to_cond_stibp); 1934 else 1935 static_branch_disable(&switch_to_cond_stibp); 1936 } 1937 1938 #undef pr_fmt 1939 #define pr_fmt(fmt) fmt 1940 1941 /* Update the static key controlling the MDS CPU buffer clear in idle */ 1942 static void update_mds_branch_idle(void) 1943 { 1944 /* 1945 * Enable the idle clearing if SMT is active on CPUs which are 1946 * affected only by MSBDS and not any other MDS variant. 1947 * 1948 * The other variants cannot be mitigated when SMT is enabled, so 1949 * clearing the buffers on idle just to prevent the Store Buffer 1950 * repartitioning leak would be a window dressing exercise. 1951 */ 1952 if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY)) 1953 return; 1954 1955 if (sched_smt_active()) { 1956 static_branch_enable(&mds_idle_clear); 1957 } else if (mmio_mitigation == MMIO_MITIGATION_OFF || 1958 (x86_arch_cap_msr & ARCH_CAP_FBSDP_NO)) { 1959 static_branch_disable(&mds_idle_clear); 1960 } 1961 } 1962 1963 #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n" 1964 #define TAA_MSG_SMT "TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.\n" 1965 #define MMIO_MSG_SMT "MMIO Stale Data CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/processor_mmio_stale_data.html for more details.\n" 1966 1967 void cpu_bugs_smt_update(void) 1968 { 1969 mutex_lock(&spec_ctrl_mutex); 1970 1971 if (sched_smt_active() && unprivileged_ebpf_enabled() && 1972 spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE) 1973 pr_warn_once(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG); 1974 1975 switch (spectre_v2_user_stibp) { 1976 case SPECTRE_V2_USER_NONE: 1977 break; 1978 case SPECTRE_V2_USER_STRICT: 1979 case SPECTRE_V2_USER_STRICT_PREFERRED: 1980 update_stibp_strict(); 1981 break; 1982 case SPECTRE_V2_USER_PRCTL: 1983 case SPECTRE_V2_USER_SECCOMP: 1984 update_indir_branch_cond(); 1985 break; 1986 } 1987 1988 switch (mds_mitigation) { 1989 case MDS_MITIGATION_FULL: 1990 case MDS_MITIGATION_AUTO: 1991 case MDS_MITIGATION_VMWERV: 1992 if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY)) 1993 pr_warn_once(MDS_MSG_SMT); 1994 update_mds_branch_idle(); 1995 break; 1996 case MDS_MITIGATION_OFF: 1997 break; 1998 } 1999 2000 switch (taa_mitigation) { 2001 case TAA_MITIGATION_VERW: 2002 case TAA_MITIGATION_AUTO: 2003 case TAA_MITIGATION_UCODE_NEEDED: 2004 if (sched_smt_active()) 2005 pr_warn_once(TAA_MSG_SMT); 2006 break; 2007 case TAA_MITIGATION_TSX_DISABLED: 2008 case TAA_MITIGATION_OFF: 2009 break; 2010 } 2011 2012 switch (mmio_mitigation) { 2013 case MMIO_MITIGATION_VERW: 2014 case MMIO_MITIGATION_AUTO: 2015 case MMIO_MITIGATION_UCODE_NEEDED: 2016 if (sched_smt_active()) 2017 pr_warn_once(MMIO_MSG_SMT); 2018 break; 2019 case MMIO_MITIGATION_OFF: 2020 break; 2021 } 2022 2023 mutex_unlock(&spec_ctrl_mutex); 2024 } 2025 2026 #undef pr_fmt 2027 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt 2028 2029 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; 2030 2031 /* The kernel command line selection */ 2032 enum ssb_mitigation_cmd { 2033 SPEC_STORE_BYPASS_CMD_NONE, 2034 SPEC_STORE_BYPASS_CMD_AUTO, 2035 SPEC_STORE_BYPASS_CMD_ON, 2036 SPEC_STORE_BYPASS_CMD_PRCTL, 2037 SPEC_STORE_BYPASS_CMD_SECCOMP, 2038 }; 2039 2040 static const char * const ssb_strings[] = { 2041 [SPEC_STORE_BYPASS_NONE] = "Vulnerable", 2042 [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", 2043 [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", 2044 [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", 2045 }; 2046 2047 static const struct { 2048 const char *option; 2049 enum ssb_mitigation_cmd cmd; 2050 } ssb_mitigation_options[] __initconst = { 2051 { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ 2052 { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ 2053 { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ 2054 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ 2055 { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ 2056 }; 2057 2058 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) 2059 { 2060 enum ssb_mitigation_cmd cmd; 2061 char arg[20]; 2062 int ret, i; 2063 2064 cmd = IS_ENABLED(CONFIG_MITIGATION_SSB) ? 2065 SPEC_STORE_BYPASS_CMD_AUTO : SPEC_STORE_BYPASS_CMD_NONE; 2066 if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable") || 2067 cpu_mitigations_off()) { 2068 return SPEC_STORE_BYPASS_CMD_NONE; 2069 } else { 2070 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", 2071 arg, sizeof(arg)); 2072 if (ret < 0) 2073 return cmd; 2074 2075 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { 2076 if (!match_option(arg, ret, ssb_mitigation_options[i].option)) 2077 continue; 2078 2079 cmd = ssb_mitigation_options[i].cmd; 2080 break; 2081 } 2082 2083 if (i >= ARRAY_SIZE(ssb_mitigation_options)) { 2084 pr_err("unknown option (%s). Switching to default mode\n", arg); 2085 return cmd; 2086 } 2087 } 2088 2089 return cmd; 2090 } 2091 2092 static enum ssb_mitigation __init __ssb_select_mitigation(void) 2093 { 2094 enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; 2095 enum ssb_mitigation_cmd cmd; 2096 2097 if (!boot_cpu_has(X86_FEATURE_SSBD)) 2098 return mode; 2099 2100 cmd = ssb_parse_cmdline(); 2101 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && 2102 (cmd == SPEC_STORE_BYPASS_CMD_NONE || 2103 cmd == SPEC_STORE_BYPASS_CMD_AUTO)) 2104 return mode; 2105 2106 switch (cmd) { 2107 case SPEC_STORE_BYPASS_CMD_SECCOMP: 2108 /* 2109 * Choose prctl+seccomp as the default mode if seccomp is 2110 * enabled. 2111 */ 2112 if (IS_ENABLED(CONFIG_SECCOMP)) 2113 mode = SPEC_STORE_BYPASS_SECCOMP; 2114 else 2115 mode = SPEC_STORE_BYPASS_PRCTL; 2116 break; 2117 case SPEC_STORE_BYPASS_CMD_ON: 2118 mode = SPEC_STORE_BYPASS_DISABLE; 2119 break; 2120 case SPEC_STORE_BYPASS_CMD_AUTO: 2121 case SPEC_STORE_BYPASS_CMD_PRCTL: 2122 mode = SPEC_STORE_BYPASS_PRCTL; 2123 break; 2124 case SPEC_STORE_BYPASS_CMD_NONE: 2125 break; 2126 } 2127 2128 /* 2129 * We have three CPU feature flags that are in play here: 2130 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. 2131 * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass 2132 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation 2133 */ 2134 if (mode == SPEC_STORE_BYPASS_DISABLE) { 2135 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); 2136 /* 2137 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may 2138 * use a completely different MSR and bit dependent on family. 2139 */ 2140 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) && 2141 !static_cpu_has(X86_FEATURE_AMD_SSBD)) { 2142 x86_amd_ssb_disable(); 2143 } else { 2144 x86_spec_ctrl_base |= SPEC_CTRL_SSBD; 2145 update_spec_ctrl(x86_spec_ctrl_base); 2146 } 2147 } 2148 2149 return mode; 2150 } 2151 2152 static void ssb_select_mitigation(void) 2153 { 2154 ssb_mode = __ssb_select_mitigation(); 2155 2156 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 2157 pr_info("%s\n", ssb_strings[ssb_mode]); 2158 } 2159 2160 #undef pr_fmt 2161 #define pr_fmt(fmt) "Speculation prctl: " fmt 2162 2163 static void task_update_spec_tif(struct task_struct *tsk) 2164 { 2165 /* Force the update of the real TIF bits */ 2166 set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE); 2167 2168 /* 2169 * Immediately update the speculation control MSRs for the current 2170 * task, but for a non-current task delay setting the CPU 2171 * mitigation until it is scheduled next. 2172 * 2173 * This can only happen for SECCOMP mitigation. For PRCTL it's 2174 * always the current task. 2175 */ 2176 if (tsk == current) 2177 speculation_ctrl_update_current(); 2178 } 2179 2180 static int l1d_flush_prctl_set(struct task_struct *task, unsigned long ctrl) 2181 { 2182 2183 if (!static_branch_unlikely(&switch_mm_cond_l1d_flush)) 2184 return -EPERM; 2185 2186 switch (ctrl) { 2187 case PR_SPEC_ENABLE: 2188 set_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH); 2189 return 0; 2190 case PR_SPEC_DISABLE: 2191 clear_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH); 2192 return 0; 2193 default: 2194 return -ERANGE; 2195 } 2196 } 2197 2198 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) 2199 { 2200 if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && 2201 ssb_mode != SPEC_STORE_BYPASS_SECCOMP) 2202 return -ENXIO; 2203 2204 switch (ctrl) { 2205 case PR_SPEC_ENABLE: 2206 /* If speculation is force disabled, enable is not allowed */ 2207 if (task_spec_ssb_force_disable(task)) 2208 return -EPERM; 2209 task_clear_spec_ssb_disable(task); 2210 task_clear_spec_ssb_noexec(task); 2211 task_update_spec_tif(task); 2212 break; 2213 case PR_SPEC_DISABLE: 2214 task_set_spec_ssb_disable(task); 2215 task_clear_spec_ssb_noexec(task); 2216 task_update_spec_tif(task); 2217 break; 2218 case PR_SPEC_FORCE_DISABLE: 2219 task_set_spec_ssb_disable(task); 2220 task_set_spec_ssb_force_disable(task); 2221 task_clear_spec_ssb_noexec(task); 2222 task_update_spec_tif(task); 2223 break; 2224 case PR_SPEC_DISABLE_NOEXEC: 2225 if (task_spec_ssb_force_disable(task)) 2226 return -EPERM; 2227 task_set_spec_ssb_disable(task); 2228 task_set_spec_ssb_noexec(task); 2229 task_update_spec_tif(task); 2230 break; 2231 default: 2232 return -ERANGE; 2233 } 2234 return 0; 2235 } 2236 2237 static bool is_spec_ib_user_controlled(void) 2238 { 2239 return spectre_v2_user_ibpb == SPECTRE_V2_USER_PRCTL || 2240 spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP || 2241 spectre_v2_user_stibp == SPECTRE_V2_USER_PRCTL || 2242 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP; 2243 } 2244 2245 static int ib_prctl_set(struct task_struct *task, unsigned long ctrl) 2246 { 2247 switch (ctrl) { 2248 case PR_SPEC_ENABLE: 2249 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE && 2250 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE) 2251 return 0; 2252 2253 /* 2254 * With strict mode for both IBPB and STIBP, the instruction 2255 * code paths avoid checking this task flag and instead, 2256 * unconditionally run the instruction. However, STIBP and IBPB 2257 * are independent and either can be set to conditionally 2258 * enabled regardless of the mode of the other. 2259 * 2260 * If either is set to conditional, allow the task flag to be 2261 * updated, unless it was force-disabled by a previous prctl 2262 * call. Currently, this is possible on an AMD CPU which has the 2263 * feature X86_FEATURE_AMD_STIBP_ALWAYS_ON. In this case, if the 2264 * kernel is booted with 'spectre_v2_user=seccomp', then 2265 * spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP and 2266 * spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED. 2267 */ 2268 if (!is_spec_ib_user_controlled() || 2269 task_spec_ib_force_disable(task)) 2270 return -EPERM; 2271 2272 task_clear_spec_ib_disable(task); 2273 task_update_spec_tif(task); 2274 break; 2275 case PR_SPEC_DISABLE: 2276 case PR_SPEC_FORCE_DISABLE: 2277 /* 2278 * Indirect branch speculation is always allowed when 2279 * mitigation is force disabled. 2280 */ 2281 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE && 2282 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE) 2283 return -EPERM; 2284 2285 if (!is_spec_ib_user_controlled()) 2286 return 0; 2287 2288 task_set_spec_ib_disable(task); 2289 if (ctrl == PR_SPEC_FORCE_DISABLE) 2290 task_set_spec_ib_force_disable(task); 2291 task_update_spec_tif(task); 2292 if (task == current) 2293 indirect_branch_prediction_barrier(); 2294 break; 2295 default: 2296 return -ERANGE; 2297 } 2298 return 0; 2299 } 2300 2301 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, 2302 unsigned long ctrl) 2303 { 2304 switch (which) { 2305 case PR_SPEC_STORE_BYPASS: 2306 return ssb_prctl_set(task, ctrl); 2307 case PR_SPEC_INDIRECT_BRANCH: 2308 return ib_prctl_set(task, ctrl); 2309 case PR_SPEC_L1D_FLUSH: 2310 return l1d_flush_prctl_set(task, ctrl); 2311 default: 2312 return -ENODEV; 2313 } 2314 } 2315 2316 #ifdef CONFIG_SECCOMP 2317 void arch_seccomp_spec_mitigate(struct task_struct *task) 2318 { 2319 if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) 2320 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); 2321 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP || 2322 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP) 2323 ib_prctl_set(task, PR_SPEC_FORCE_DISABLE); 2324 } 2325 #endif 2326 2327 static int l1d_flush_prctl_get(struct task_struct *task) 2328 { 2329 if (!static_branch_unlikely(&switch_mm_cond_l1d_flush)) 2330 return PR_SPEC_FORCE_DISABLE; 2331 2332 if (test_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH)) 2333 return PR_SPEC_PRCTL | PR_SPEC_ENABLE; 2334 else 2335 return PR_SPEC_PRCTL | PR_SPEC_DISABLE; 2336 } 2337 2338 static int ssb_prctl_get(struct task_struct *task) 2339 { 2340 switch (ssb_mode) { 2341 case SPEC_STORE_BYPASS_NONE: 2342 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 2343 return PR_SPEC_ENABLE; 2344 return PR_SPEC_NOT_AFFECTED; 2345 case SPEC_STORE_BYPASS_DISABLE: 2346 return PR_SPEC_DISABLE; 2347 case SPEC_STORE_BYPASS_SECCOMP: 2348 case SPEC_STORE_BYPASS_PRCTL: 2349 if (task_spec_ssb_force_disable(task)) 2350 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; 2351 if (task_spec_ssb_noexec(task)) 2352 return PR_SPEC_PRCTL | PR_SPEC_DISABLE_NOEXEC; 2353 if (task_spec_ssb_disable(task)) 2354 return PR_SPEC_PRCTL | PR_SPEC_DISABLE; 2355 return PR_SPEC_PRCTL | PR_SPEC_ENABLE; 2356 } 2357 BUG(); 2358 } 2359 2360 static int ib_prctl_get(struct task_struct *task) 2361 { 2362 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) 2363 return PR_SPEC_NOT_AFFECTED; 2364 2365 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE && 2366 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE) 2367 return PR_SPEC_ENABLE; 2368 else if (is_spec_ib_user_controlled()) { 2369 if (task_spec_ib_force_disable(task)) 2370 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; 2371 if (task_spec_ib_disable(task)) 2372 return PR_SPEC_PRCTL | PR_SPEC_DISABLE; 2373 return PR_SPEC_PRCTL | PR_SPEC_ENABLE; 2374 } else if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT || 2375 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT || 2376 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED) 2377 return PR_SPEC_DISABLE; 2378 else 2379 return PR_SPEC_NOT_AFFECTED; 2380 } 2381 2382 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) 2383 { 2384 switch (which) { 2385 case PR_SPEC_STORE_BYPASS: 2386 return ssb_prctl_get(task); 2387 case PR_SPEC_INDIRECT_BRANCH: 2388 return ib_prctl_get(task); 2389 case PR_SPEC_L1D_FLUSH: 2390 return l1d_flush_prctl_get(task); 2391 default: 2392 return -ENODEV; 2393 } 2394 } 2395 2396 void x86_spec_ctrl_setup_ap(void) 2397 { 2398 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) 2399 update_spec_ctrl(x86_spec_ctrl_base); 2400 2401 if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) 2402 x86_amd_ssb_disable(); 2403 } 2404 2405 bool itlb_multihit_kvm_mitigation; 2406 EXPORT_SYMBOL_GPL(itlb_multihit_kvm_mitigation); 2407 2408 #undef pr_fmt 2409 #define pr_fmt(fmt) "L1TF: " fmt 2410 2411 /* Default mitigation for L1TF-affected CPUs */ 2412 enum l1tf_mitigations l1tf_mitigation __ro_after_init = 2413 IS_ENABLED(CONFIG_MITIGATION_L1TF) ? L1TF_MITIGATION_FLUSH : L1TF_MITIGATION_OFF; 2414 #if IS_ENABLED(CONFIG_KVM_INTEL) 2415 EXPORT_SYMBOL_GPL(l1tf_mitigation); 2416 #endif 2417 enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; 2418 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation); 2419 2420 /* 2421 * These CPUs all support 44bits physical address space internally in the 2422 * cache but CPUID can report a smaller number of physical address bits. 2423 * 2424 * The L1TF mitigation uses the top most address bit for the inversion of 2425 * non present PTEs. When the installed memory reaches into the top most 2426 * address bit due to memory holes, which has been observed on machines 2427 * which report 36bits physical address bits and have 32G RAM installed, 2428 * then the mitigation range check in l1tf_select_mitigation() triggers. 2429 * This is a false positive because the mitigation is still possible due to 2430 * the fact that the cache uses 44bit internally. Use the cache bits 2431 * instead of the reported physical bits and adjust them on the affected 2432 * machines to 44bit if the reported bits are less than 44. 2433 */ 2434 static void override_cache_bits(struct cpuinfo_x86 *c) 2435 { 2436 if (c->x86 != 6) 2437 return; 2438 2439 switch (c->x86_vfm) { 2440 case INTEL_NEHALEM: 2441 case INTEL_WESTMERE: 2442 case INTEL_SANDYBRIDGE: 2443 case INTEL_IVYBRIDGE: 2444 case INTEL_HASWELL: 2445 case INTEL_HASWELL_L: 2446 case INTEL_HASWELL_G: 2447 case INTEL_BROADWELL: 2448 case INTEL_BROADWELL_G: 2449 case INTEL_SKYLAKE_L: 2450 case INTEL_SKYLAKE: 2451 case INTEL_KABYLAKE_L: 2452 case INTEL_KABYLAKE: 2453 if (c->x86_cache_bits < 44) 2454 c->x86_cache_bits = 44; 2455 break; 2456 } 2457 } 2458 2459 static void __init l1tf_select_mitigation(void) 2460 { 2461 u64 half_pa; 2462 2463 if (!boot_cpu_has_bug(X86_BUG_L1TF)) 2464 return; 2465 2466 if (cpu_mitigations_off()) 2467 l1tf_mitigation = L1TF_MITIGATION_OFF; 2468 else if (cpu_mitigations_auto_nosmt()) 2469 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; 2470 2471 override_cache_bits(&boot_cpu_data); 2472 2473 switch (l1tf_mitigation) { 2474 case L1TF_MITIGATION_OFF: 2475 case L1TF_MITIGATION_FLUSH_NOWARN: 2476 case L1TF_MITIGATION_FLUSH: 2477 break; 2478 case L1TF_MITIGATION_FLUSH_NOSMT: 2479 case L1TF_MITIGATION_FULL: 2480 cpu_smt_disable(false); 2481 break; 2482 case L1TF_MITIGATION_FULL_FORCE: 2483 cpu_smt_disable(true); 2484 break; 2485 } 2486 2487 #if CONFIG_PGTABLE_LEVELS == 2 2488 pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n"); 2489 return; 2490 #endif 2491 2492 half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT; 2493 if (l1tf_mitigation != L1TF_MITIGATION_OFF && 2494 e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) { 2495 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n"); 2496 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n", 2497 half_pa); 2498 pr_info("However, doing so will make a part of your RAM unusable.\n"); 2499 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n"); 2500 return; 2501 } 2502 2503 setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV); 2504 } 2505 2506 static int __init l1tf_cmdline(char *str) 2507 { 2508 if (!boot_cpu_has_bug(X86_BUG_L1TF)) 2509 return 0; 2510 2511 if (!str) 2512 return -EINVAL; 2513 2514 if (!strcmp(str, "off")) 2515 l1tf_mitigation = L1TF_MITIGATION_OFF; 2516 else if (!strcmp(str, "flush,nowarn")) 2517 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN; 2518 else if (!strcmp(str, "flush")) 2519 l1tf_mitigation = L1TF_MITIGATION_FLUSH; 2520 else if (!strcmp(str, "flush,nosmt")) 2521 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; 2522 else if (!strcmp(str, "full")) 2523 l1tf_mitigation = L1TF_MITIGATION_FULL; 2524 else if (!strcmp(str, "full,force")) 2525 l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE; 2526 2527 return 0; 2528 } 2529 early_param("l1tf", l1tf_cmdline); 2530 2531 #undef pr_fmt 2532 #define pr_fmt(fmt) "Speculative Return Stack Overflow: " fmt 2533 2534 enum srso_mitigation { 2535 SRSO_MITIGATION_NONE, 2536 SRSO_MITIGATION_UCODE_NEEDED, 2537 SRSO_MITIGATION_SAFE_RET_UCODE_NEEDED, 2538 SRSO_MITIGATION_MICROCODE, 2539 SRSO_MITIGATION_SAFE_RET, 2540 SRSO_MITIGATION_IBPB, 2541 SRSO_MITIGATION_IBPB_ON_VMEXIT, 2542 SRSO_MITIGATION_BP_SPEC_REDUCE, 2543 }; 2544 2545 enum srso_mitigation_cmd { 2546 SRSO_CMD_OFF, 2547 SRSO_CMD_MICROCODE, 2548 SRSO_CMD_SAFE_RET, 2549 SRSO_CMD_IBPB, 2550 SRSO_CMD_IBPB_ON_VMEXIT, 2551 }; 2552 2553 static const char * const srso_strings[] = { 2554 [SRSO_MITIGATION_NONE] = "Vulnerable", 2555 [SRSO_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode", 2556 [SRSO_MITIGATION_SAFE_RET_UCODE_NEEDED] = "Vulnerable: Safe RET, no microcode", 2557 [SRSO_MITIGATION_MICROCODE] = "Vulnerable: Microcode, no safe RET", 2558 [SRSO_MITIGATION_SAFE_RET] = "Mitigation: Safe RET", 2559 [SRSO_MITIGATION_IBPB] = "Mitigation: IBPB", 2560 [SRSO_MITIGATION_IBPB_ON_VMEXIT] = "Mitigation: IBPB on VMEXIT only", 2561 [SRSO_MITIGATION_BP_SPEC_REDUCE] = "Mitigation: Reduced Speculation" 2562 }; 2563 2564 static enum srso_mitigation srso_mitigation __ro_after_init = SRSO_MITIGATION_NONE; 2565 static enum srso_mitigation_cmd srso_cmd __ro_after_init = SRSO_CMD_SAFE_RET; 2566 2567 static int __init srso_parse_cmdline(char *str) 2568 { 2569 if (!str) 2570 return -EINVAL; 2571 2572 if (!strcmp(str, "off")) 2573 srso_cmd = SRSO_CMD_OFF; 2574 else if (!strcmp(str, "microcode")) 2575 srso_cmd = SRSO_CMD_MICROCODE; 2576 else if (!strcmp(str, "safe-ret")) 2577 srso_cmd = SRSO_CMD_SAFE_RET; 2578 else if (!strcmp(str, "ibpb")) 2579 srso_cmd = SRSO_CMD_IBPB; 2580 else if (!strcmp(str, "ibpb-vmexit")) 2581 srso_cmd = SRSO_CMD_IBPB_ON_VMEXIT; 2582 else 2583 pr_err("Ignoring unknown SRSO option (%s).", str); 2584 2585 return 0; 2586 } 2587 early_param("spec_rstack_overflow", srso_parse_cmdline); 2588 2589 #define SRSO_NOTICE "WARNING: See https://kernel.org/doc/html/latest/admin-guide/hw-vuln/srso.html for mitigation options." 2590 2591 static void __init srso_select_mitigation(void) 2592 { 2593 bool has_microcode = boot_cpu_has(X86_FEATURE_IBPB_BRTYPE); 2594 2595 if (!boot_cpu_has_bug(X86_BUG_SRSO) || 2596 cpu_mitigations_off() || 2597 srso_cmd == SRSO_CMD_OFF) { 2598 if (boot_cpu_has(X86_FEATURE_SBPB)) 2599 x86_pred_cmd = PRED_CMD_SBPB; 2600 goto out; 2601 } 2602 2603 if (has_microcode) { 2604 /* 2605 * Zen1/2 with SMT off aren't vulnerable after the right 2606 * IBPB microcode has been applied. 2607 * 2608 * Zen1/2 don't have SBPB, no need to try to enable it here. 2609 */ 2610 if (boot_cpu_data.x86 < 0x19 && !cpu_smt_possible()) { 2611 setup_force_cpu_cap(X86_FEATURE_SRSO_NO); 2612 goto out; 2613 } 2614 2615 if (retbleed_mitigation == RETBLEED_MITIGATION_IBPB) { 2616 srso_mitigation = SRSO_MITIGATION_IBPB; 2617 goto out; 2618 } 2619 } else { 2620 pr_warn("IBPB-extending microcode not applied!\n"); 2621 pr_warn(SRSO_NOTICE); 2622 2623 /* may be overwritten by SRSO_CMD_SAFE_RET below */ 2624 srso_mitigation = SRSO_MITIGATION_UCODE_NEEDED; 2625 } 2626 2627 switch (srso_cmd) { 2628 case SRSO_CMD_MICROCODE: 2629 if (has_microcode) { 2630 srso_mitigation = SRSO_MITIGATION_MICROCODE; 2631 pr_warn(SRSO_NOTICE); 2632 } 2633 break; 2634 2635 case SRSO_CMD_SAFE_RET: 2636 if (boot_cpu_has(X86_FEATURE_SRSO_USER_KERNEL_NO)) 2637 goto ibpb_on_vmexit; 2638 2639 if (IS_ENABLED(CONFIG_MITIGATION_SRSO)) { 2640 /* 2641 * Enable the return thunk for generated code 2642 * like ftrace, static_call, etc. 2643 */ 2644 setup_force_cpu_cap(X86_FEATURE_RETHUNK); 2645 setup_force_cpu_cap(X86_FEATURE_UNRET); 2646 2647 if (boot_cpu_data.x86 == 0x19) { 2648 setup_force_cpu_cap(X86_FEATURE_SRSO_ALIAS); 2649 x86_return_thunk = srso_alias_return_thunk; 2650 } else { 2651 setup_force_cpu_cap(X86_FEATURE_SRSO); 2652 x86_return_thunk = srso_return_thunk; 2653 } 2654 if (has_microcode) 2655 srso_mitigation = SRSO_MITIGATION_SAFE_RET; 2656 else 2657 srso_mitigation = SRSO_MITIGATION_SAFE_RET_UCODE_NEEDED; 2658 } else { 2659 pr_err("WARNING: kernel not compiled with MITIGATION_SRSO.\n"); 2660 } 2661 break; 2662 2663 case SRSO_CMD_IBPB: 2664 if (IS_ENABLED(CONFIG_MITIGATION_IBPB_ENTRY)) { 2665 if (has_microcode) { 2666 setup_force_cpu_cap(X86_FEATURE_ENTRY_IBPB); 2667 setup_force_cpu_cap(X86_FEATURE_IBPB_ON_VMEXIT); 2668 srso_mitigation = SRSO_MITIGATION_IBPB; 2669 2670 /* 2671 * IBPB on entry already obviates the need for 2672 * software-based untraining so clear those in case some 2673 * other mitigation like Retbleed has selected them. 2674 */ 2675 setup_clear_cpu_cap(X86_FEATURE_UNRET); 2676 setup_clear_cpu_cap(X86_FEATURE_RETHUNK); 2677 2678 /* 2679 * There is no need for RSB filling: entry_ibpb() ensures 2680 * all predictions, including the RSB, are invalidated, 2681 * regardless of IBPB implementation. 2682 */ 2683 setup_clear_cpu_cap(X86_FEATURE_RSB_VMEXIT); 2684 } 2685 } else { 2686 pr_err("WARNING: kernel not compiled with MITIGATION_IBPB_ENTRY.\n"); 2687 } 2688 break; 2689 2690 ibpb_on_vmexit: 2691 case SRSO_CMD_IBPB_ON_VMEXIT: 2692 if (boot_cpu_has(X86_FEATURE_SRSO_BP_SPEC_REDUCE)) { 2693 pr_notice("Reducing speculation to address VM/HV SRSO attack vector.\n"); 2694 srso_mitigation = SRSO_MITIGATION_BP_SPEC_REDUCE; 2695 break; 2696 } 2697 2698 if (IS_ENABLED(CONFIG_MITIGATION_IBPB_ENTRY)) { 2699 if (has_microcode) { 2700 setup_force_cpu_cap(X86_FEATURE_IBPB_ON_VMEXIT); 2701 srso_mitigation = SRSO_MITIGATION_IBPB_ON_VMEXIT; 2702 2703 /* 2704 * There is no need for RSB filling: entry_ibpb() ensures 2705 * all predictions, including the RSB, are invalidated, 2706 * regardless of IBPB implementation. 2707 */ 2708 setup_clear_cpu_cap(X86_FEATURE_RSB_VMEXIT); 2709 } 2710 } else { 2711 pr_err("WARNING: kernel not compiled with MITIGATION_IBPB_ENTRY.\n"); 2712 } 2713 break; 2714 default: 2715 break; 2716 } 2717 2718 out: 2719 /* 2720 * Clear the feature flag if this mitigation is not selected as that 2721 * feature flag controls the BpSpecReduce MSR bit toggling in KVM. 2722 */ 2723 if (srso_mitigation != SRSO_MITIGATION_BP_SPEC_REDUCE) 2724 setup_clear_cpu_cap(X86_FEATURE_SRSO_BP_SPEC_REDUCE); 2725 2726 if (srso_mitigation != SRSO_MITIGATION_NONE) 2727 pr_info("%s\n", srso_strings[srso_mitigation]); 2728 } 2729 2730 #undef pr_fmt 2731 #define pr_fmt(fmt) fmt 2732 2733 #ifdef CONFIG_SYSFS 2734 2735 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion" 2736 2737 #if IS_ENABLED(CONFIG_KVM_INTEL) 2738 static const char * const l1tf_vmx_states[] = { 2739 [VMENTER_L1D_FLUSH_AUTO] = "auto", 2740 [VMENTER_L1D_FLUSH_NEVER] = "vulnerable", 2741 [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes", 2742 [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes", 2743 [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled", 2744 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary" 2745 }; 2746 2747 static ssize_t l1tf_show_state(char *buf) 2748 { 2749 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) 2750 return sysfs_emit(buf, "%s\n", L1TF_DEFAULT_MSG); 2751 2752 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED || 2753 (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER && 2754 sched_smt_active())) { 2755 return sysfs_emit(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG, 2756 l1tf_vmx_states[l1tf_vmx_mitigation]); 2757 } 2758 2759 return sysfs_emit(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG, 2760 l1tf_vmx_states[l1tf_vmx_mitigation], 2761 sched_smt_active() ? "vulnerable" : "disabled"); 2762 } 2763 2764 static ssize_t itlb_multihit_show_state(char *buf) 2765 { 2766 if (!boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || 2767 !boot_cpu_has(X86_FEATURE_VMX)) 2768 return sysfs_emit(buf, "KVM: Mitigation: VMX unsupported\n"); 2769 else if (!(cr4_read_shadow() & X86_CR4_VMXE)) 2770 return sysfs_emit(buf, "KVM: Mitigation: VMX disabled\n"); 2771 else if (itlb_multihit_kvm_mitigation) 2772 return sysfs_emit(buf, "KVM: Mitigation: Split huge pages\n"); 2773 else 2774 return sysfs_emit(buf, "KVM: Vulnerable\n"); 2775 } 2776 #else 2777 static ssize_t l1tf_show_state(char *buf) 2778 { 2779 return sysfs_emit(buf, "%s\n", L1TF_DEFAULT_MSG); 2780 } 2781 2782 static ssize_t itlb_multihit_show_state(char *buf) 2783 { 2784 return sysfs_emit(buf, "Processor vulnerable\n"); 2785 } 2786 #endif 2787 2788 static ssize_t mds_show_state(char *buf) 2789 { 2790 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { 2791 return sysfs_emit(buf, "%s; SMT Host state unknown\n", 2792 mds_strings[mds_mitigation]); 2793 } 2794 2795 if (boot_cpu_has(X86_BUG_MSBDS_ONLY)) { 2796 return sysfs_emit(buf, "%s; SMT %s\n", mds_strings[mds_mitigation], 2797 (mds_mitigation == MDS_MITIGATION_OFF ? "vulnerable" : 2798 sched_smt_active() ? "mitigated" : "disabled")); 2799 } 2800 2801 return sysfs_emit(buf, "%s; SMT %s\n", mds_strings[mds_mitigation], 2802 sched_smt_active() ? "vulnerable" : "disabled"); 2803 } 2804 2805 static ssize_t tsx_async_abort_show_state(char *buf) 2806 { 2807 if ((taa_mitigation == TAA_MITIGATION_TSX_DISABLED) || 2808 (taa_mitigation == TAA_MITIGATION_OFF)) 2809 return sysfs_emit(buf, "%s\n", taa_strings[taa_mitigation]); 2810 2811 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { 2812 return sysfs_emit(buf, "%s; SMT Host state unknown\n", 2813 taa_strings[taa_mitigation]); 2814 } 2815 2816 return sysfs_emit(buf, "%s; SMT %s\n", taa_strings[taa_mitigation], 2817 sched_smt_active() ? "vulnerable" : "disabled"); 2818 } 2819 2820 static ssize_t mmio_stale_data_show_state(char *buf) 2821 { 2822 if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN)) 2823 return sysfs_emit(buf, "Unknown: No mitigations\n"); 2824 2825 if (mmio_mitigation == MMIO_MITIGATION_OFF) 2826 return sysfs_emit(buf, "%s\n", mmio_strings[mmio_mitigation]); 2827 2828 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { 2829 return sysfs_emit(buf, "%s; SMT Host state unknown\n", 2830 mmio_strings[mmio_mitigation]); 2831 } 2832 2833 return sysfs_emit(buf, "%s; SMT %s\n", mmio_strings[mmio_mitigation], 2834 sched_smt_active() ? "vulnerable" : "disabled"); 2835 } 2836 2837 static ssize_t rfds_show_state(char *buf) 2838 { 2839 return sysfs_emit(buf, "%s\n", rfds_strings[rfds_mitigation]); 2840 } 2841 2842 static char *stibp_state(void) 2843 { 2844 if (spectre_v2_in_eibrs_mode(spectre_v2_enabled) && 2845 !boot_cpu_has(X86_FEATURE_AUTOIBRS)) 2846 return ""; 2847 2848 switch (spectre_v2_user_stibp) { 2849 case SPECTRE_V2_USER_NONE: 2850 return "; STIBP: disabled"; 2851 case SPECTRE_V2_USER_STRICT: 2852 return "; STIBP: forced"; 2853 case SPECTRE_V2_USER_STRICT_PREFERRED: 2854 return "; STIBP: always-on"; 2855 case SPECTRE_V2_USER_PRCTL: 2856 case SPECTRE_V2_USER_SECCOMP: 2857 if (static_key_enabled(&switch_to_cond_stibp)) 2858 return "; STIBP: conditional"; 2859 } 2860 return ""; 2861 } 2862 2863 static char *ibpb_state(void) 2864 { 2865 if (boot_cpu_has(X86_FEATURE_IBPB)) { 2866 if (static_key_enabled(&switch_mm_always_ibpb)) 2867 return "; IBPB: always-on"; 2868 if (static_key_enabled(&switch_mm_cond_ibpb)) 2869 return "; IBPB: conditional"; 2870 return "; IBPB: disabled"; 2871 } 2872 return ""; 2873 } 2874 2875 static char *pbrsb_eibrs_state(void) 2876 { 2877 if (boot_cpu_has_bug(X86_BUG_EIBRS_PBRSB)) { 2878 if (boot_cpu_has(X86_FEATURE_RSB_VMEXIT_LITE) || 2879 boot_cpu_has(X86_FEATURE_RSB_VMEXIT)) 2880 return "; PBRSB-eIBRS: SW sequence"; 2881 else 2882 return "; PBRSB-eIBRS: Vulnerable"; 2883 } else { 2884 return "; PBRSB-eIBRS: Not affected"; 2885 } 2886 } 2887 2888 static const char *spectre_bhi_state(void) 2889 { 2890 if (!boot_cpu_has_bug(X86_BUG_BHI)) 2891 return "; BHI: Not affected"; 2892 else if (boot_cpu_has(X86_FEATURE_CLEAR_BHB_HW)) 2893 return "; BHI: BHI_DIS_S"; 2894 else if (boot_cpu_has(X86_FEATURE_CLEAR_BHB_LOOP)) 2895 return "; BHI: SW loop, KVM: SW loop"; 2896 else if (boot_cpu_has(X86_FEATURE_RETPOLINE) && 2897 !boot_cpu_has(X86_FEATURE_RETPOLINE_LFENCE) && 2898 rrsba_disabled) 2899 return "; BHI: Retpoline"; 2900 else if (boot_cpu_has(X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT)) 2901 return "; BHI: Vulnerable, KVM: SW loop"; 2902 2903 return "; BHI: Vulnerable"; 2904 } 2905 2906 static ssize_t spectre_v2_show_state(char *buf) 2907 { 2908 if (spectre_v2_enabled == SPECTRE_V2_LFENCE) 2909 return sysfs_emit(buf, "Vulnerable: LFENCE\n"); 2910 2911 if (spectre_v2_enabled == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled()) 2912 return sysfs_emit(buf, "Vulnerable: eIBRS with unprivileged eBPF\n"); 2913 2914 if (sched_smt_active() && unprivileged_ebpf_enabled() && 2915 spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE) 2916 return sysfs_emit(buf, "Vulnerable: eIBRS+LFENCE with unprivileged eBPF and SMT\n"); 2917 2918 return sysfs_emit(buf, "%s%s%s%s%s%s%s%s\n", 2919 spectre_v2_strings[spectre_v2_enabled], 2920 ibpb_state(), 2921 boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? "; IBRS_FW" : "", 2922 stibp_state(), 2923 boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? "; RSB filling" : "", 2924 pbrsb_eibrs_state(), 2925 spectre_bhi_state(), 2926 /* this should always be at the end */ 2927 spectre_v2_module_string()); 2928 } 2929 2930 static ssize_t srbds_show_state(char *buf) 2931 { 2932 return sysfs_emit(buf, "%s\n", srbds_strings[srbds_mitigation]); 2933 } 2934 2935 static ssize_t retbleed_show_state(char *buf) 2936 { 2937 if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET || 2938 retbleed_mitigation == RETBLEED_MITIGATION_IBPB) { 2939 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD && 2940 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON) 2941 return sysfs_emit(buf, "Vulnerable: untrained return thunk / IBPB on non-AMD based uarch\n"); 2942 2943 return sysfs_emit(buf, "%s; SMT %s\n", retbleed_strings[retbleed_mitigation], 2944 !sched_smt_active() ? "disabled" : 2945 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT || 2946 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED ? 2947 "enabled with STIBP protection" : "vulnerable"); 2948 } 2949 2950 return sysfs_emit(buf, "%s\n", retbleed_strings[retbleed_mitigation]); 2951 } 2952 2953 static ssize_t srso_show_state(char *buf) 2954 { 2955 if (boot_cpu_has(X86_FEATURE_SRSO_NO)) 2956 return sysfs_emit(buf, "Mitigation: SMT disabled\n"); 2957 2958 return sysfs_emit(buf, "%s\n", srso_strings[srso_mitigation]); 2959 } 2960 2961 static ssize_t gds_show_state(char *buf) 2962 { 2963 return sysfs_emit(buf, "%s\n", gds_strings[gds_mitigation]); 2964 } 2965 2966 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, 2967 char *buf, unsigned int bug) 2968 { 2969 if (!boot_cpu_has_bug(bug)) 2970 return sysfs_emit(buf, "Not affected\n"); 2971 2972 switch (bug) { 2973 case X86_BUG_CPU_MELTDOWN: 2974 if (boot_cpu_has(X86_FEATURE_PTI)) 2975 return sysfs_emit(buf, "Mitigation: PTI\n"); 2976 2977 if (hypervisor_is_type(X86_HYPER_XEN_PV)) 2978 return sysfs_emit(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n"); 2979 2980 break; 2981 2982 case X86_BUG_SPECTRE_V1: 2983 return sysfs_emit(buf, "%s\n", spectre_v1_strings[spectre_v1_mitigation]); 2984 2985 case X86_BUG_SPECTRE_V2: 2986 return spectre_v2_show_state(buf); 2987 2988 case X86_BUG_SPEC_STORE_BYPASS: 2989 return sysfs_emit(buf, "%s\n", ssb_strings[ssb_mode]); 2990 2991 case X86_BUG_L1TF: 2992 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV)) 2993 return l1tf_show_state(buf); 2994 break; 2995 2996 case X86_BUG_MDS: 2997 return mds_show_state(buf); 2998 2999 case X86_BUG_TAA: 3000 return tsx_async_abort_show_state(buf); 3001 3002 case X86_BUG_ITLB_MULTIHIT: 3003 return itlb_multihit_show_state(buf); 3004 3005 case X86_BUG_SRBDS: 3006 return srbds_show_state(buf); 3007 3008 case X86_BUG_MMIO_STALE_DATA: 3009 case X86_BUG_MMIO_UNKNOWN: 3010 return mmio_stale_data_show_state(buf); 3011 3012 case X86_BUG_RETBLEED: 3013 return retbleed_show_state(buf); 3014 3015 case X86_BUG_SRSO: 3016 return srso_show_state(buf); 3017 3018 case X86_BUG_GDS: 3019 return gds_show_state(buf); 3020 3021 case X86_BUG_RFDS: 3022 return rfds_show_state(buf); 3023 3024 default: 3025 break; 3026 } 3027 3028 return sysfs_emit(buf, "Vulnerable\n"); 3029 } 3030 3031 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) 3032 { 3033 return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); 3034 } 3035 3036 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) 3037 { 3038 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); 3039 } 3040 3041 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) 3042 { 3043 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); 3044 } 3045 3046 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) 3047 { 3048 return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); 3049 } 3050 3051 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf) 3052 { 3053 return cpu_show_common(dev, attr, buf, X86_BUG_L1TF); 3054 } 3055 3056 ssize_t cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf) 3057 { 3058 return cpu_show_common(dev, attr, buf, X86_BUG_MDS); 3059 } 3060 3061 ssize_t cpu_show_tsx_async_abort(struct device *dev, struct device_attribute *attr, char *buf) 3062 { 3063 return cpu_show_common(dev, attr, buf, X86_BUG_TAA); 3064 } 3065 3066 ssize_t cpu_show_itlb_multihit(struct device *dev, struct device_attribute *attr, char *buf) 3067 { 3068 return cpu_show_common(dev, attr, buf, X86_BUG_ITLB_MULTIHIT); 3069 } 3070 3071 ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *buf) 3072 { 3073 return cpu_show_common(dev, attr, buf, X86_BUG_SRBDS); 3074 } 3075 3076 ssize_t cpu_show_mmio_stale_data(struct device *dev, struct device_attribute *attr, char *buf) 3077 { 3078 if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN)) 3079 return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_UNKNOWN); 3080 else 3081 return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_STALE_DATA); 3082 } 3083 3084 ssize_t cpu_show_retbleed(struct device *dev, struct device_attribute *attr, char *buf) 3085 { 3086 return cpu_show_common(dev, attr, buf, X86_BUG_RETBLEED); 3087 } 3088 3089 ssize_t cpu_show_spec_rstack_overflow(struct device *dev, struct device_attribute *attr, char *buf) 3090 { 3091 return cpu_show_common(dev, attr, buf, X86_BUG_SRSO); 3092 } 3093 3094 ssize_t cpu_show_gds(struct device *dev, struct device_attribute *attr, char *buf) 3095 { 3096 return cpu_show_common(dev, attr, buf, X86_BUG_GDS); 3097 } 3098 3099 ssize_t cpu_show_reg_file_data_sampling(struct device *dev, struct device_attribute *attr, char *buf) 3100 { 3101 return cpu_show_common(dev, attr, buf, X86_BUG_RFDS); 3102 } 3103 #endif 3104 3105 void __warn_thunk(void) 3106 { 3107 WARN_ONCE(1, "Unpatched return thunk in use. This should not happen!\n"); 3108 } 3109