1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 1994 Linus Torvalds 4 * 5 * Cyrix stuff, June 1998 by: 6 * - Rafael R. Reilova (moved everything from head.S), 7 * <rreilova@ececs.uc.edu> 8 * - Channing Corn (tests & fixes), 9 * - Andrew D. Balsa (code cleanup). 10 */ 11 #include <linux/init.h> 12 #include <linux/cpu.h> 13 #include <linux/module.h> 14 #include <linux/nospec.h> 15 #include <linux/prctl.h> 16 #include <linux/sched/smt.h> 17 #include <linux/pgtable.h> 18 #include <linux/bpf.h> 19 20 #include <asm/spec-ctrl.h> 21 #include <asm/cmdline.h> 22 #include <asm/bugs.h> 23 #include <asm/processor.h> 24 #include <asm/processor-flags.h> 25 #include <asm/fpu/api.h> 26 #include <asm/msr.h> 27 #include <asm/vmx.h> 28 #include <asm/paravirt.h> 29 #include <asm/cpu_device_id.h> 30 #include <asm/e820/api.h> 31 #include <asm/hypervisor.h> 32 #include <asm/tlbflush.h> 33 #include <asm/cpu.h> 34 35 #include "cpu.h" 36 37 static void __init spectre_v1_select_mitigation(void); 38 static void __init spectre_v2_select_mitigation(void); 39 static void __init retbleed_select_mitigation(void); 40 static void __init spectre_v2_user_select_mitigation(void); 41 static void __init ssb_select_mitigation(void); 42 static void __init l1tf_select_mitigation(void); 43 static void __init mds_select_mitigation(void); 44 static void __init md_clear_update_mitigation(void); 45 static void __init md_clear_select_mitigation(void); 46 static void __init taa_select_mitigation(void); 47 static void __init mmio_select_mitigation(void); 48 static void __init srbds_select_mitigation(void); 49 static void __init l1d_flush_select_mitigation(void); 50 static void __init srso_select_mitigation(void); 51 static void __init gds_select_mitigation(void); 52 53 /* The base value of the SPEC_CTRL MSR without task-specific bits set */ 54 u64 x86_spec_ctrl_base; 55 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); 56 57 /* The current value of the SPEC_CTRL MSR with task-specific bits set */ 58 DEFINE_PER_CPU(u64, x86_spec_ctrl_current); 59 EXPORT_PER_CPU_SYMBOL_GPL(x86_spec_ctrl_current); 60 61 u64 x86_pred_cmd __ro_after_init = PRED_CMD_IBPB; 62 EXPORT_SYMBOL_GPL(x86_pred_cmd); 63 64 static u64 __ro_after_init x86_arch_cap_msr; 65 66 static DEFINE_MUTEX(spec_ctrl_mutex); 67 68 void (*x86_return_thunk)(void) __ro_after_init = __x86_return_thunk; 69 70 /* Update SPEC_CTRL MSR and its cached copy unconditionally */ 71 static void update_spec_ctrl(u64 val) 72 { 73 this_cpu_write(x86_spec_ctrl_current, val); 74 wrmsrl(MSR_IA32_SPEC_CTRL, val); 75 } 76 77 /* 78 * Keep track of the SPEC_CTRL MSR value for the current task, which may differ 79 * from x86_spec_ctrl_base due to STIBP/SSB in __speculation_ctrl_update(). 80 */ 81 void update_spec_ctrl_cond(u64 val) 82 { 83 if (this_cpu_read(x86_spec_ctrl_current) == val) 84 return; 85 86 this_cpu_write(x86_spec_ctrl_current, val); 87 88 /* 89 * When KERNEL_IBRS this MSR is written on return-to-user, unless 90 * forced the update can be delayed until that time. 91 */ 92 if (!cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS)) 93 wrmsrl(MSR_IA32_SPEC_CTRL, val); 94 } 95 96 noinstr u64 spec_ctrl_current(void) 97 { 98 return this_cpu_read(x86_spec_ctrl_current); 99 } 100 EXPORT_SYMBOL_GPL(spec_ctrl_current); 101 102 /* 103 * AMD specific MSR info for Speculative Store Bypass control. 104 * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). 105 */ 106 u64 __ro_after_init x86_amd_ls_cfg_base; 107 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; 108 109 /* Control conditional STIBP in switch_to() */ 110 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp); 111 /* Control conditional IBPB in switch_mm() */ 112 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb); 113 /* Control unconditional IBPB in switch_mm() */ 114 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb); 115 116 /* Control MDS CPU buffer clear before idling (halt, mwait) */ 117 DEFINE_STATIC_KEY_FALSE(mds_idle_clear); 118 EXPORT_SYMBOL_GPL(mds_idle_clear); 119 120 /* 121 * Controls whether l1d flush based mitigations are enabled, 122 * based on hw features and admin setting via boot parameter 123 * defaults to false 124 */ 125 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush); 126 127 /* Controls CPU Fill buffer clear before KVM guest MMIO accesses */ 128 DEFINE_STATIC_KEY_FALSE(mmio_stale_data_clear); 129 EXPORT_SYMBOL_GPL(mmio_stale_data_clear); 130 131 void __init cpu_select_mitigations(void) 132 { 133 /* 134 * Read the SPEC_CTRL MSR to account for reserved bits which may 135 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD 136 * init code as it is not enumerated and depends on the family. 137 */ 138 if (cpu_feature_enabled(X86_FEATURE_MSR_SPEC_CTRL)) { 139 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); 140 141 /* 142 * Previously running kernel (kexec), may have some controls 143 * turned ON. Clear them and let the mitigations setup below 144 * rediscover them based on configuration. 145 */ 146 x86_spec_ctrl_base &= ~SPEC_CTRL_MITIGATIONS_MASK; 147 } 148 149 x86_arch_cap_msr = x86_read_arch_cap_msr(); 150 151 /* Select the proper CPU mitigations before patching alternatives: */ 152 spectre_v1_select_mitigation(); 153 spectre_v2_select_mitigation(); 154 /* 155 * retbleed_select_mitigation() relies on the state set by 156 * spectre_v2_select_mitigation(); specifically it wants to know about 157 * spectre_v2=ibrs. 158 */ 159 retbleed_select_mitigation(); 160 /* 161 * spectre_v2_user_select_mitigation() relies on the state set by 162 * retbleed_select_mitigation(); specifically the STIBP selection is 163 * forced for UNRET or IBPB. 164 */ 165 spectre_v2_user_select_mitigation(); 166 ssb_select_mitigation(); 167 l1tf_select_mitigation(); 168 md_clear_select_mitigation(); 169 srbds_select_mitigation(); 170 l1d_flush_select_mitigation(); 171 172 /* 173 * srso_select_mitigation() depends and must run after 174 * retbleed_select_mitigation(). 175 */ 176 srso_select_mitigation(); 177 gds_select_mitigation(); 178 } 179 180 /* 181 * NOTE: This function is *only* called for SVM, since Intel uses 182 * MSR_IA32_SPEC_CTRL for SSBD. 183 */ 184 void 185 x86_virt_spec_ctrl(u64 guest_virt_spec_ctrl, bool setguest) 186 { 187 u64 guestval, hostval; 188 struct thread_info *ti = current_thread_info(); 189 190 /* 191 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update 192 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported. 193 */ 194 if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) && 195 !static_cpu_has(X86_FEATURE_VIRT_SSBD)) 196 return; 197 198 /* 199 * If the host has SSBD mitigation enabled, force it in the host's 200 * virtual MSR value. If its not permanently enabled, evaluate 201 * current's TIF_SSBD thread flag. 202 */ 203 if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE)) 204 hostval = SPEC_CTRL_SSBD; 205 else 206 hostval = ssbd_tif_to_spec_ctrl(ti->flags); 207 208 /* Sanitize the guest value */ 209 guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD; 210 211 if (hostval != guestval) { 212 unsigned long tif; 213 214 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) : 215 ssbd_spec_ctrl_to_tif(hostval); 216 217 speculation_ctrl_update(tif); 218 } 219 } 220 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); 221 222 static void x86_amd_ssb_disable(void) 223 { 224 u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; 225 226 if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) 227 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); 228 else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) 229 wrmsrl(MSR_AMD64_LS_CFG, msrval); 230 } 231 232 #undef pr_fmt 233 #define pr_fmt(fmt) "MDS: " fmt 234 235 /* Default mitigation for MDS-affected CPUs */ 236 static enum mds_mitigations mds_mitigation __ro_after_init = 237 IS_ENABLED(CONFIG_MITIGATION_MDS) ? MDS_MITIGATION_FULL : MDS_MITIGATION_OFF; 238 static bool mds_nosmt __ro_after_init = false; 239 240 static const char * const mds_strings[] = { 241 [MDS_MITIGATION_OFF] = "Vulnerable", 242 [MDS_MITIGATION_FULL] = "Mitigation: Clear CPU buffers", 243 [MDS_MITIGATION_VMWERV] = "Vulnerable: Clear CPU buffers attempted, no microcode", 244 }; 245 246 static void __init mds_select_mitigation(void) 247 { 248 if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) { 249 mds_mitigation = MDS_MITIGATION_OFF; 250 return; 251 } 252 253 if (mds_mitigation == MDS_MITIGATION_FULL) { 254 if (!boot_cpu_has(X86_FEATURE_MD_CLEAR)) 255 mds_mitigation = MDS_MITIGATION_VMWERV; 256 257 setup_force_cpu_cap(X86_FEATURE_CLEAR_CPU_BUF); 258 259 if (!boot_cpu_has(X86_BUG_MSBDS_ONLY) && 260 (mds_nosmt || cpu_mitigations_auto_nosmt())) 261 cpu_smt_disable(false); 262 } 263 } 264 265 static int __init mds_cmdline(char *str) 266 { 267 if (!boot_cpu_has_bug(X86_BUG_MDS)) 268 return 0; 269 270 if (!str) 271 return -EINVAL; 272 273 if (!strcmp(str, "off")) 274 mds_mitigation = MDS_MITIGATION_OFF; 275 else if (!strcmp(str, "full")) 276 mds_mitigation = MDS_MITIGATION_FULL; 277 else if (!strcmp(str, "full,nosmt")) { 278 mds_mitigation = MDS_MITIGATION_FULL; 279 mds_nosmt = true; 280 } 281 282 return 0; 283 } 284 early_param("mds", mds_cmdline); 285 286 #undef pr_fmt 287 #define pr_fmt(fmt) "TAA: " fmt 288 289 enum taa_mitigations { 290 TAA_MITIGATION_OFF, 291 TAA_MITIGATION_UCODE_NEEDED, 292 TAA_MITIGATION_VERW, 293 TAA_MITIGATION_TSX_DISABLED, 294 }; 295 296 /* Default mitigation for TAA-affected CPUs */ 297 static enum taa_mitigations taa_mitigation __ro_after_init = 298 IS_ENABLED(CONFIG_MITIGATION_TAA) ? TAA_MITIGATION_VERW : TAA_MITIGATION_OFF; 299 static bool taa_nosmt __ro_after_init; 300 301 static const char * const taa_strings[] = { 302 [TAA_MITIGATION_OFF] = "Vulnerable", 303 [TAA_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode", 304 [TAA_MITIGATION_VERW] = "Mitigation: Clear CPU buffers", 305 [TAA_MITIGATION_TSX_DISABLED] = "Mitigation: TSX disabled", 306 }; 307 308 static void __init taa_select_mitigation(void) 309 { 310 if (!boot_cpu_has_bug(X86_BUG_TAA)) { 311 taa_mitigation = TAA_MITIGATION_OFF; 312 return; 313 } 314 315 /* TSX previously disabled by tsx=off */ 316 if (!boot_cpu_has(X86_FEATURE_RTM)) { 317 taa_mitigation = TAA_MITIGATION_TSX_DISABLED; 318 return; 319 } 320 321 if (cpu_mitigations_off()) { 322 taa_mitigation = TAA_MITIGATION_OFF; 323 return; 324 } 325 326 /* 327 * TAA mitigation via VERW is turned off if both 328 * tsx_async_abort=off and mds=off are specified. 329 */ 330 if (taa_mitigation == TAA_MITIGATION_OFF && 331 mds_mitigation == MDS_MITIGATION_OFF) 332 return; 333 334 if (boot_cpu_has(X86_FEATURE_MD_CLEAR)) 335 taa_mitigation = TAA_MITIGATION_VERW; 336 else 337 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED; 338 339 /* 340 * VERW doesn't clear the CPU buffers when MD_CLEAR=1 and MDS_NO=1. 341 * A microcode update fixes this behavior to clear CPU buffers. It also 342 * adds support for MSR_IA32_TSX_CTRL which is enumerated by the 343 * ARCH_CAP_TSX_CTRL_MSR bit. 344 * 345 * On MDS_NO=1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode 346 * update is required. 347 */ 348 if ( (x86_arch_cap_msr & ARCH_CAP_MDS_NO) && 349 !(x86_arch_cap_msr & ARCH_CAP_TSX_CTRL_MSR)) 350 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED; 351 352 /* 353 * TSX is enabled, select alternate mitigation for TAA which is 354 * the same as MDS. Enable MDS static branch to clear CPU buffers. 355 * 356 * For guests that can't determine whether the correct microcode is 357 * present on host, enable the mitigation for UCODE_NEEDED as well. 358 */ 359 setup_force_cpu_cap(X86_FEATURE_CLEAR_CPU_BUF); 360 361 if (taa_nosmt || cpu_mitigations_auto_nosmt()) 362 cpu_smt_disable(false); 363 } 364 365 static int __init tsx_async_abort_parse_cmdline(char *str) 366 { 367 if (!boot_cpu_has_bug(X86_BUG_TAA)) 368 return 0; 369 370 if (!str) 371 return -EINVAL; 372 373 if (!strcmp(str, "off")) { 374 taa_mitigation = TAA_MITIGATION_OFF; 375 } else if (!strcmp(str, "full")) { 376 taa_mitigation = TAA_MITIGATION_VERW; 377 } else if (!strcmp(str, "full,nosmt")) { 378 taa_mitigation = TAA_MITIGATION_VERW; 379 taa_nosmt = true; 380 } 381 382 return 0; 383 } 384 early_param("tsx_async_abort", tsx_async_abort_parse_cmdline); 385 386 #undef pr_fmt 387 #define pr_fmt(fmt) "MMIO Stale Data: " fmt 388 389 enum mmio_mitigations { 390 MMIO_MITIGATION_OFF, 391 MMIO_MITIGATION_UCODE_NEEDED, 392 MMIO_MITIGATION_VERW, 393 }; 394 395 /* Default mitigation for Processor MMIO Stale Data vulnerabilities */ 396 static enum mmio_mitigations mmio_mitigation __ro_after_init = 397 IS_ENABLED(CONFIG_MITIGATION_MMIO_STALE_DATA) ? MMIO_MITIGATION_VERW : MMIO_MITIGATION_OFF; 398 static bool mmio_nosmt __ro_after_init = false; 399 400 static const char * const mmio_strings[] = { 401 [MMIO_MITIGATION_OFF] = "Vulnerable", 402 [MMIO_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode", 403 [MMIO_MITIGATION_VERW] = "Mitigation: Clear CPU buffers", 404 }; 405 406 static void __init mmio_select_mitigation(void) 407 { 408 if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA) || 409 boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN) || 410 cpu_mitigations_off()) { 411 mmio_mitigation = MMIO_MITIGATION_OFF; 412 return; 413 } 414 415 if (mmio_mitigation == MMIO_MITIGATION_OFF) 416 return; 417 418 /* 419 * Enable CPU buffer clear mitigation for host and VMM, if also affected 420 * by MDS or TAA. Otherwise, enable mitigation for VMM only. 421 */ 422 if (boot_cpu_has_bug(X86_BUG_MDS) || (boot_cpu_has_bug(X86_BUG_TAA) && 423 boot_cpu_has(X86_FEATURE_RTM))) 424 setup_force_cpu_cap(X86_FEATURE_CLEAR_CPU_BUF); 425 426 /* 427 * X86_FEATURE_CLEAR_CPU_BUF could be enabled by other VERW based 428 * mitigations, disable KVM-only mitigation in that case. 429 */ 430 if (boot_cpu_has(X86_FEATURE_CLEAR_CPU_BUF)) 431 static_branch_disable(&mmio_stale_data_clear); 432 else 433 static_branch_enable(&mmio_stale_data_clear); 434 435 /* 436 * If Processor-MMIO-Stale-Data bug is present and Fill Buffer data can 437 * be propagated to uncore buffers, clearing the Fill buffers on idle 438 * is required irrespective of SMT state. 439 */ 440 if (!(x86_arch_cap_msr & ARCH_CAP_FBSDP_NO)) 441 static_branch_enable(&mds_idle_clear); 442 443 /* 444 * Check if the system has the right microcode. 445 * 446 * CPU Fill buffer clear mitigation is enumerated by either an explicit 447 * FB_CLEAR or by the presence of both MD_CLEAR and L1D_FLUSH on MDS 448 * affected systems. 449 */ 450 if ((x86_arch_cap_msr & ARCH_CAP_FB_CLEAR) || 451 (boot_cpu_has(X86_FEATURE_MD_CLEAR) && 452 boot_cpu_has(X86_FEATURE_FLUSH_L1D) && 453 !(x86_arch_cap_msr & ARCH_CAP_MDS_NO))) 454 mmio_mitigation = MMIO_MITIGATION_VERW; 455 else 456 mmio_mitigation = MMIO_MITIGATION_UCODE_NEEDED; 457 458 if (mmio_nosmt || cpu_mitigations_auto_nosmt()) 459 cpu_smt_disable(false); 460 } 461 462 static int __init mmio_stale_data_parse_cmdline(char *str) 463 { 464 if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) 465 return 0; 466 467 if (!str) 468 return -EINVAL; 469 470 if (!strcmp(str, "off")) { 471 mmio_mitigation = MMIO_MITIGATION_OFF; 472 } else if (!strcmp(str, "full")) { 473 mmio_mitigation = MMIO_MITIGATION_VERW; 474 } else if (!strcmp(str, "full,nosmt")) { 475 mmio_mitigation = MMIO_MITIGATION_VERW; 476 mmio_nosmt = true; 477 } 478 479 return 0; 480 } 481 early_param("mmio_stale_data", mmio_stale_data_parse_cmdline); 482 483 #undef pr_fmt 484 #define pr_fmt(fmt) "Register File Data Sampling: " fmt 485 486 enum rfds_mitigations { 487 RFDS_MITIGATION_OFF, 488 RFDS_MITIGATION_VERW, 489 RFDS_MITIGATION_UCODE_NEEDED, 490 }; 491 492 /* Default mitigation for Register File Data Sampling */ 493 static enum rfds_mitigations rfds_mitigation __ro_after_init = 494 IS_ENABLED(CONFIG_MITIGATION_RFDS) ? RFDS_MITIGATION_VERW : RFDS_MITIGATION_OFF; 495 496 static const char * const rfds_strings[] = { 497 [RFDS_MITIGATION_OFF] = "Vulnerable", 498 [RFDS_MITIGATION_VERW] = "Mitigation: Clear Register File", 499 [RFDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode", 500 }; 501 502 static void __init rfds_select_mitigation(void) 503 { 504 if (!boot_cpu_has_bug(X86_BUG_RFDS) || cpu_mitigations_off()) { 505 rfds_mitigation = RFDS_MITIGATION_OFF; 506 return; 507 } 508 if (rfds_mitigation == RFDS_MITIGATION_OFF) 509 return; 510 511 if (x86_arch_cap_msr & ARCH_CAP_RFDS_CLEAR) 512 setup_force_cpu_cap(X86_FEATURE_CLEAR_CPU_BUF); 513 else 514 rfds_mitigation = RFDS_MITIGATION_UCODE_NEEDED; 515 } 516 517 static __init int rfds_parse_cmdline(char *str) 518 { 519 if (!str) 520 return -EINVAL; 521 522 if (!boot_cpu_has_bug(X86_BUG_RFDS)) 523 return 0; 524 525 if (!strcmp(str, "off")) 526 rfds_mitigation = RFDS_MITIGATION_OFF; 527 else if (!strcmp(str, "on")) 528 rfds_mitigation = RFDS_MITIGATION_VERW; 529 530 return 0; 531 } 532 early_param("reg_file_data_sampling", rfds_parse_cmdline); 533 534 #undef pr_fmt 535 #define pr_fmt(fmt) "" fmt 536 537 static void __init md_clear_update_mitigation(void) 538 { 539 if (cpu_mitigations_off()) 540 return; 541 542 if (!boot_cpu_has(X86_FEATURE_CLEAR_CPU_BUF)) 543 goto out; 544 545 /* 546 * X86_FEATURE_CLEAR_CPU_BUF is now enabled. Update MDS, TAA and MMIO 547 * Stale Data mitigation, if necessary. 548 */ 549 if (mds_mitigation == MDS_MITIGATION_OFF && 550 boot_cpu_has_bug(X86_BUG_MDS)) { 551 mds_mitigation = MDS_MITIGATION_FULL; 552 mds_select_mitigation(); 553 } 554 if (taa_mitigation == TAA_MITIGATION_OFF && 555 boot_cpu_has_bug(X86_BUG_TAA)) { 556 taa_mitigation = TAA_MITIGATION_VERW; 557 taa_select_mitigation(); 558 } 559 /* 560 * MMIO_MITIGATION_OFF is not checked here so that mmio_stale_data_clear 561 * gets updated correctly as per X86_FEATURE_CLEAR_CPU_BUF state. 562 */ 563 if (boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) { 564 mmio_mitigation = MMIO_MITIGATION_VERW; 565 mmio_select_mitigation(); 566 } 567 if (rfds_mitigation == RFDS_MITIGATION_OFF && 568 boot_cpu_has_bug(X86_BUG_RFDS)) { 569 rfds_mitigation = RFDS_MITIGATION_VERW; 570 rfds_select_mitigation(); 571 } 572 out: 573 if (boot_cpu_has_bug(X86_BUG_MDS)) 574 pr_info("MDS: %s\n", mds_strings[mds_mitigation]); 575 if (boot_cpu_has_bug(X86_BUG_TAA)) 576 pr_info("TAA: %s\n", taa_strings[taa_mitigation]); 577 if (boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) 578 pr_info("MMIO Stale Data: %s\n", mmio_strings[mmio_mitigation]); 579 else if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN)) 580 pr_info("MMIO Stale Data: Unknown: No mitigations\n"); 581 if (boot_cpu_has_bug(X86_BUG_RFDS)) 582 pr_info("Register File Data Sampling: %s\n", rfds_strings[rfds_mitigation]); 583 } 584 585 static void __init md_clear_select_mitigation(void) 586 { 587 mds_select_mitigation(); 588 taa_select_mitigation(); 589 mmio_select_mitigation(); 590 rfds_select_mitigation(); 591 592 /* 593 * As these mitigations are inter-related and rely on VERW instruction 594 * to clear the microarchitural buffers, update and print their status 595 * after mitigation selection is done for each of these vulnerabilities. 596 */ 597 md_clear_update_mitigation(); 598 } 599 600 #undef pr_fmt 601 #define pr_fmt(fmt) "SRBDS: " fmt 602 603 enum srbds_mitigations { 604 SRBDS_MITIGATION_OFF, 605 SRBDS_MITIGATION_UCODE_NEEDED, 606 SRBDS_MITIGATION_FULL, 607 SRBDS_MITIGATION_TSX_OFF, 608 SRBDS_MITIGATION_HYPERVISOR, 609 }; 610 611 static enum srbds_mitigations srbds_mitigation __ro_after_init = 612 IS_ENABLED(CONFIG_MITIGATION_SRBDS) ? SRBDS_MITIGATION_FULL : SRBDS_MITIGATION_OFF; 613 614 static const char * const srbds_strings[] = { 615 [SRBDS_MITIGATION_OFF] = "Vulnerable", 616 [SRBDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode", 617 [SRBDS_MITIGATION_FULL] = "Mitigation: Microcode", 618 [SRBDS_MITIGATION_TSX_OFF] = "Mitigation: TSX disabled", 619 [SRBDS_MITIGATION_HYPERVISOR] = "Unknown: Dependent on hypervisor status", 620 }; 621 622 static bool srbds_off; 623 624 void update_srbds_msr(void) 625 { 626 u64 mcu_ctrl; 627 628 if (!boot_cpu_has_bug(X86_BUG_SRBDS)) 629 return; 630 631 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) 632 return; 633 634 if (srbds_mitigation == SRBDS_MITIGATION_UCODE_NEEDED) 635 return; 636 637 /* 638 * A MDS_NO CPU for which SRBDS mitigation is not needed due to TSX 639 * being disabled and it hasn't received the SRBDS MSR microcode. 640 */ 641 if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL)) 642 return; 643 644 rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); 645 646 switch (srbds_mitigation) { 647 case SRBDS_MITIGATION_OFF: 648 case SRBDS_MITIGATION_TSX_OFF: 649 mcu_ctrl |= RNGDS_MITG_DIS; 650 break; 651 case SRBDS_MITIGATION_FULL: 652 mcu_ctrl &= ~RNGDS_MITG_DIS; 653 break; 654 default: 655 break; 656 } 657 658 wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); 659 } 660 661 static void __init srbds_select_mitigation(void) 662 { 663 if (!boot_cpu_has_bug(X86_BUG_SRBDS)) 664 return; 665 666 /* 667 * Check to see if this is one of the MDS_NO systems supporting TSX that 668 * are only exposed to SRBDS when TSX is enabled or when CPU is affected 669 * by Processor MMIO Stale Data vulnerability. 670 */ 671 if ((x86_arch_cap_msr & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM) && 672 !boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) 673 srbds_mitigation = SRBDS_MITIGATION_TSX_OFF; 674 else if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) 675 srbds_mitigation = SRBDS_MITIGATION_HYPERVISOR; 676 else if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL)) 677 srbds_mitigation = SRBDS_MITIGATION_UCODE_NEEDED; 678 else if (cpu_mitigations_off() || srbds_off) 679 srbds_mitigation = SRBDS_MITIGATION_OFF; 680 681 update_srbds_msr(); 682 pr_info("%s\n", srbds_strings[srbds_mitigation]); 683 } 684 685 static int __init srbds_parse_cmdline(char *str) 686 { 687 if (!str) 688 return -EINVAL; 689 690 if (!boot_cpu_has_bug(X86_BUG_SRBDS)) 691 return 0; 692 693 srbds_off = !strcmp(str, "off"); 694 return 0; 695 } 696 early_param("srbds", srbds_parse_cmdline); 697 698 #undef pr_fmt 699 #define pr_fmt(fmt) "L1D Flush : " fmt 700 701 enum l1d_flush_mitigations { 702 L1D_FLUSH_OFF = 0, 703 L1D_FLUSH_ON, 704 }; 705 706 static enum l1d_flush_mitigations l1d_flush_mitigation __initdata = L1D_FLUSH_OFF; 707 708 static void __init l1d_flush_select_mitigation(void) 709 { 710 if (!l1d_flush_mitigation || !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) 711 return; 712 713 static_branch_enable(&switch_mm_cond_l1d_flush); 714 pr_info("Conditional flush on switch_mm() enabled\n"); 715 } 716 717 static int __init l1d_flush_parse_cmdline(char *str) 718 { 719 if (!strcmp(str, "on")) 720 l1d_flush_mitigation = L1D_FLUSH_ON; 721 722 return 0; 723 } 724 early_param("l1d_flush", l1d_flush_parse_cmdline); 725 726 #undef pr_fmt 727 #define pr_fmt(fmt) "GDS: " fmt 728 729 enum gds_mitigations { 730 GDS_MITIGATION_OFF, 731 GDS_MITIGATION_UCODE_NEEDED, 732 GDS_MITIGATION_FORCE, 733 GDS_MITIGATION_FULL, 734 GDS_MITIGATION_FULL_LOCKED, 735 GDS_MITIGATION_HYPERVISOR, 736 }; 737 738 static enum gds_mitigations gds_mitigation __ro_after_init = 739 IS_ENABLED(CONFIG_MITIGATION_GDS) ? GDS_MITIGATION_FULL : GDS_MITIGATION_OFF; 740 741 static const char * const gds_strings[] = { 742 [GDS_MITIGATION_OFF] = "Vulnerable", 743 [GDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode", 744 [GDS_MITIGATION_FORCE] = "Mitigation: AVX disabled, no microcode", 745 [GDS_MITIGATION_FULL] = "Mitigation: Microcode", 746 [GDS_MITIGATION_FULL_LOCKED] = "Mitigation: Microcode (locked)", 747 [GDS_MITIGATION_HYPERVISOR] = "Unknown: Dependent on hypervisor status", 748 }; 749 750 bool gds_ucode_mitigated(void) 751 { 752 return (gds_mitigation == GDS_MITIGATION_FULL || 753 gds_mitigation == GDS_MITIGATION_FULL_LOCKED); 754 } 755 EXPORT_SYMBOL_GPL(gds_ucode_mitigated); 756 757 void update_gds_msr(void) 758 { 759 u64 mcu_ctrl_after; 760 u64 mcu_ctrl; 761 762 switch (gds_mitigation) { 763 case GDS_MITIGATION_OFF: 764 rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); 765 mcu_ctrl |= GDS_MITG_DIS; 766 break; 767 case GDS_MITIGATION_FULL_LOCKED: 768 /* 769 * The LOCKED state comes from the boot CPU. APs might not have 770 * the same state. Make sure the mitigation is enabled on all 771 * CPUs. 772 */ 773 case GDS_MITIGATION_FULL: 774 rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); 775 mcu_ctrl &= ~GDS_MITG_DIS; 776 break; 777 case GDS_MITIGATION_FORCE: 778 case GDS_MITIGATION_UCODE_NEEDED: 779 case GDS_MITIGATION_HYPERVISOR: 780 return; 781 } 782 783 wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); 784 785 /* 786 * Check to make sure that the WRMSR value was not ignored. Writes to 787 * GDS_MITG_DIS will be ignored if this processor is locked but the boot 788 * processor was not. 789 */ 790 rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl_after); 791 WARN_ON_ONCE(mcu_ctrl != mcu_ctrl_after); 792 } 793 794 static void __init gds_select_mitigation(void) 795 { 796 u64 mcu_ctrl; 797 798 if (!boot_cpu_has_bug(X86_BUG_GDS)) 799 return; 800 801 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { 802 gds_mitigation = GDS_MITIGATION_HYPERVISOR; 803 goto out; 804 } 805 806 if (cpu_mitigations_off()) 807 gds_mitigation = GDS_MITIGATION_OFF; 808 /* Will verify below that mitigation _can_ be disabled */ 809 810 /* No microcode */ 811 if (!(x86_arch_cap_msr & ARCH_CAP_GDS_CTRL)) { 812 if (gds_mitigation == GDS_MITIGATION_FORCE) { 813 /* 814 * This only needs to be done on the boot CPU so do it 815 * here rather than in update_gds_msr() 816 */ 817 setup_clear_cpu_cap(X86_FEATURE_AVX); 818 pr_warn("Microcode update needed! Disabling AVX as mitigation.\n"); 819 } else { 820 gds_mitigation = GDS_MITIGATION_UCODE_NEEDED; 821 } 822 goto out; 823 } 824 825 /* Microcode has mitigation, use it */ 826 if (gds_mitigation == GDS_MITIGATION_FORCE) 827 gds_mitigation = GDS_MITIGATION_FULL; 828 829 rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); 830 if (mcu_ctrl & GDS_MITG_LOCKED) { 831 if (gds_mitigation == GDS_MITIGATION_OFF) 832 pr_warn("Mitigation locked. Disable failed.\n"); 833 834 /* 835 * The mitigation is selected from the boot CPU. All other CPUs 836 * _should_ have the same state. If the boot CPU isn't locked 837 * but others are then update_gds_msr() will WARN() of the state 838 * mismatch. If the boot CPU is locked update_gds_msr() will 839 * ensure the other CPUs have the mitigation enabled. 840 */ 841 gds_mitigation = GDS_MITIGATION_FULL_LOCKED; 842 } 843 844 update_gds_msr(); 845 out: 846 pr_info("%s\n", gds_strings[gds_mitigation]); 847 } 848 849 static int __init gds_parse_cmdline(char *str) 850 { 851 if (!str) 852 return -EINVAL; 853 854 if (!boot_cpu_has_bug(X86_BUG_GDS)) 855 return 0; 856 857 if (!strcmp(str, "off")) 858 gds_mitigation = GDS_MITIGATION_OFF; 859 else if (!strcmp(str, "force")) 860 gds_mitigation = GDS_MITIGATION_FORCE; 861 862 return 0; 863 } 864 early_param("gather_data_sampling", gds_parse_cmdline); 865 866 #undef pr_fmt 867 #define pr_fmt(fmt) "Spectre V1 : " fmt 868 869 enum spectre_v1_mitigation { 870 SPECTRE_V1_MITIGATION_NONE, 871 SPECTRE_V1_MITIGATION_AUTO, 872 }; 873 874 static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init = 875 IS_ENABLED(CONFIG_MITIGATION_SPECTRE_V1) ? 876 SPECTRE_V1_MITIGATION_AUTO : SPECTRE_V1_MITIGATION_NONE; 877 878 static const char * const spectre_v1_strings[] = { 879 [SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers", 880 [SPECTRE_V1_MITIGATION_AUTO] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization", 881 }; 882 883 /* 884 * Does SMAP provide full mitigation against speculative kernel access to 885 * userspace? 886 */ 887 static bool smap_works_speculatively(void) 888 { 889 if (!boot_cpu_has(X86_FEATURE_SMAP)) 890 return false; 891 892 /* 893 * On CPUs which are vulnerable to Meltdown, SMAP does not 894 * prevent speculative access to user data in the L1 cache. 895 * Consider SMAP to be non-functional as a mitigation on these 896 * CPUs. 897 */ 898 if (boot_cpu_has(X86_BUG_CPU_MELTDOWN)) 899 return false; 900 901 return true; 902 } 903 904 static void __init spectre_v1_select_mitigation(void) 905 { 906 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) { 907 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE; 908 return; 909 } 910 911 if (spectre_v1_mitigation == SPECTRE_V1_MITIGATION_AUTO) { 912 /* 913 * With Spectre v1, a user can speculatively control either 914 * path of a conditional swapgs with a user-controlled GS 915 * value. The mitigation is to add lfences to both code paths. 916 * 917 * If FSGSBASE is enabled, the user can put a kernel address in 918 * GS, in which case SMAP provides no protection. 919 * 920 * If FSGSBASE is disabled, the user can only put a user space 921 * address in GS. That makes an attack harder, but still 922 * possible if there's no SMAP protection. 923 */ 924 if (boot_cpu_has(X86_FEATURE_FSGSBASE) || 925 !smap_works_speculatively()) { 926 /* 927 * Mitigation can be provided from SWAPGS itself or 928 * PTI as the CR3 write in the Meltdown mitigation 929 * is serializing. 930 * 931 * If neither is there, mitigate with an LFENCE to 932 * stop speculation through swapgs. 933 */ 934 if (boot_cpu_has_bug(X86_BUG_SWAPGS) && 935 !boot_cpu_has(X86_FEATURE_PTI)) 936 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER); 937 938 /* 939 * Enable lfences in the kernel entry (non-swapgs) 940 * paths, to prevent user entry from speculatively 941 * skipping swapgs. 942 */ 943 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL); 944 } 945 } 946 947 pr_info("%s\n", spectre_v1_strings[spectre_v1_mitigation]); 948 } 949 950 static int __init nospectre_v1_cmdline(char *str) 951 { 952 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE; 953 return 0; 954 } 955 early_param("nospectre_v1", nospectre_v1_cmdline); 956 957 enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = SPECTRE_V2_NONE; 958 959 #undef pr_fmt 960 #define pr_fmt(fmt) "RETBleed: " fmt 961 962 enum retbleed_mitigation { 963 RETBLEED_MITIGATION_NONE, 964 RETBLEED_MITIGATION_UNRET, 965 RETBLEED_MITIGATION_IBPB, 966 RETBLEED_MITIGATION_IBRS, 967 RETBLEED_MITIGATION_EIBRS, 968 RETBLEED_MITIGATION_STUFF, 969 }; 970 971 enum retbleed_mitigation_cmd { 972 RETBLEED_CMD_OFF, 973 RETBLEED_CMD_AUTO, 974 RETBLEED_CMD_UNRET, 975 RETBLEED_CMD_IBPB, 976 RETBLEED_CMD_STUFF, 977 }; 978 979 static const char * const retbleed_strings[] = { 980 [RETBLEED_MITIGATION_NONE] = "Vulnerable", 981 [RETBLEED_MITIGATION_UNRET] = "Mitigation: untrained return thunk", 982 [RETBLEED_MITIGATION_IBPB] = "Mitigation: IBPB", 983 [RETBLEED_MITIGATION_IBRS] = "Mitigation: IBRS", 984 [RETBLEED_MITIGATION_EIBRS] = "Mitigation: Enhanced IBRS", 985 [RETBLEED_MITIGATION_STUFF] = "Mitigation: Stuffing", 986 }; 987 988 static enum retbleed_mitigation retbleed_mitigation __ro_after_init = 989 RETBLEED_MITIGATION_NONE; 990 static enum retbleed_mitigation_cmd retbleed_cmd __ro_after_init = 991 IS_ENABLED(CONFIG_MITIGATION_RETBLEED) ? RETBLEED_CMD_AUTO : RETBLEED_CMD_OFF; 992 993 static int __ro_after_init retbleed_nosmt = false; 994 995 static int __init retbleed_parse_cmdline(char *str) 996 { 997 if (!str) 998 return -EINVAL; 999 1000 while (str) { 1001 char *next = strchr(str, ','); 1002 if (next) { 1003 *next = 0; 1004 next++; 1005 } 1006 1007 if (!strcmp(str, "off")) { 1008 retbleed_cmd = RETBLEED_CMD_OFF; 1009 } else if (!strcmp(str, "auto")) { 1010 retbleed_cmd = RETBLEED_CMD_AUTO; 1011 } else if (!strcmp(str, "unret")) { 1012 retbleed_cmd = RETBLEED_CMD_UNRET; 1013 } else if (!strcmp(str, "ibpb")) { 1014 retbleed_cmd = RETBLEED_CMD_IBPB; 1015 } else if (!strcmp(str, "stuff")) { 1016 retbleed_cmd = RETBLEED_CMD_STUFF; 1017 } else if (!strcmp(str, "nosmt")) { 1018 retbleed_nosmt = true; 1019 } else if (!strcmp(str, "force")) { 1020 setup_force_cpu_bug(X86_BUG_RETBLEED); 1021 } else { 1022 pr_err("Ignoring unknown retbleed option (%s).", str); 1023 } 1024 1025 str = next; 1026 } 1027 1028 return 0; 1029 } 1030 early_param("retbleed", retbleed_parse_cmdline); 1031 1032 #define RETBLEED_UNTRAIN_MSG "WARNING: BTB untrained return thunk mitigation is only effective on AMD/Hygon!\n" 1033 #define RETBLEED_INTEL_MSG "WARNING: Spectre v2 mitigation leaves CPU vulnerable to RETBleed attacks, data leaks possible!\n" 1034 1035 static void __init retbleed_select_mitigation(void) 1036 { 1037 bool mitigate_smt = false; 1038 1039 if (!boot_cpu_has_bug(X86_BUG_RETBLEED) || cpu_mitigations_off()) 1040 return; 1041 1042 switch (retbleed_cmd) { 1043 case RETBLEED_CMD_OFF: 1044 return; 1045 1046 case RETBLEED_CMD_UNRET: 1047 if (IS_ENABLED(CONFIG_MITIGATION_UNRET_ENTRY)) { 1048 retbleed_mitigation = RETBLEED_MITIGATION_UNRET; 1049 } else { 1050 pr_err("WARNING: kernel not compiled with MITIGATION_UNRET_ENTRY.\n"); 1051 goto do_cmd_auto; 1052 } 1053 break; 1054 1055 case RETBLEED_CMD_IBPB: 1056 if (!boot_cpu_has(X86_FEATURE_IBPB)) { 1057 pr_err("WARNING: CPU does not support IBPB.\n"); 1058 goto do_cmd_auto; 1059 } else if (IS_ENABLED(CONFIG_MITIGATION_IBPB_ENTRY)) { 1060 retbleed_mitigation = RETBLEED_MITIGATION_IBPB; 1061 } else { 1062 pr_err("WARNING: kernel not compiled with MITIGATION_IBPB_ENTRY.\n"); 1063 goto do_cmd_auto; 1064 } 1065 break; 1066 1067 case RETBLEED_CMD_STUFF: 1068 if (IS_ENABLED(CONFIG_MITIGATION_CALL_DEPTH_TRACKING) && 1069 spectre_v2_enabled == SPECTRE_V2_RETPOLINE) { 1070 retbleed_mitigation = RETBLEED_MITIGATION_STUFF; 1071 1072 } else { 1073 if (IS_ENABLED(CONFIG_MITIGATION_CALL_DEPTH_TRACKING)) 1074 pr_err("WARNING: retbleed=stuff depends on spectre_v2=retpoline\n"); 1075 else 1076 pr_err("WARNING: kernel not compiled with MITIGATION_CALL_DEPTH_TRACKING.\n"); 1077 1078 goto do_cmd_auto; 1079 } 1080 break; 1081 1082 do_cmd_auto: 1083 case RETBLEED_CMD_AUTO: 1084 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 1085 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) { 1086 if (IS_ENABLED(CONFIG_MITIGATION_UNRET_ENTRY)) 1087 retbleed_mitigation = RETBLEED_MITIGATION_UNRET; 1088 else if (IS_ENABLED(CONFIG_MITIGATION_IBPB_ENTRY) && 1089 boot_cpu_has(X86_FEATURE_IBPB)) 1090 retbleed_mitigation = RETBLEED_MITIGATION_IBPB; 1091 } 1092 1093 /* 1094 * The Intel mitigation (IBRS or eIBRS) was already selected in 1095 * spectre_v2_select_mitigation(). 'retbleed_mitigation' will 1096 * be set accordingly below. 1097 */ 1098 1099 break; 1100 } 1101 1102 switch (retbleed_mitigation) { 1103 case RETBLEED_MITIGATION_UNRET: 1104 setup_force_cpu_cap(X86_FEATURE_RETHUNK); 1105 setup_force_cpu_cap(X86_FEATURE_UNRET); 1106 1107 x86_return_thunk = retbleed_return_thunk; 1108 1109 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD && 1110 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON) 1111 pr_err(RETBLEED_UNTRAIN_MSG); 1112 1113 mitigate_smt = true; 1114 break; 1115 1116 case RETBLEED_MITIGATION_IBPB: 1117 setup_force_cpu_cap(X86_FEATURE_ENTRY_IBPB); 1118 setup_force_cpu_cap(X86_FEATURE_IBPB_ON_VMEXIT); 1119 mitigate_smt = true; 1120 break; 1121 1122 case RETBLEED_MITIGATION_STUFF: 1123 setup_force_cpu_cap(X86_FEATURE_RETHUNK); 1124 setup_force_cpu_cap(X86_FEATURE_CALL_DEPTH); 1125 1126 x86_return_thunk = call_depth_return_thunk; 1127 break; 1128 1129 default: 1130 break; 1131 } 1132 1133 if (mitigate_smt && !boot_cpu_has(X86_FEATURE_STIBP) && 1134 (retbleed_nosmt || cpu_mitigations_auto_nosmt())) 1135 cpu_smt_disable(false); 1136 1137 /* 1138 * Let IBRS trump all on Intel without affecting the effects of the 1139 * retbleed= cmdline option except for call depth based stuffing 1140 */ 1141 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) { 1142 switch (spectre_v2_enabled) { 1143 case SPECTRE_V2_IBRS: 1144 retbleed_mitigation = RETBLEED_MITIGATION_IBRS; 1145 break; 1146 case SPECTRE_V2_EIBRS: 1147 case SPECTRE_V2_EIBRS_RETPOLINE: 1148 case SPECTRE_V2_EIBRS_LFENCE: 1149 retbleed_mitigation = RETBLEED_MITIGATION_EIBRS; 1150 break; 1151 default: 1152 if (retbleed_mitigation != RETBLEED_MITIGATION_STUFF) 1153 pr_err(RETBLEED_INTEL_MSG); 1154 } 1155 } 1156 1157 pr_info("%s\n", retbleed_strings[retbleed_mitigation]); 1158 } 1159 1160 #undef pr_fmt 1161 #define pr_fmt(fmt) "Spectre V2 : " fmt 1162 1163 static enum spectre_v2_user_mitigation spectre_v2_user_stibp __ro_after_init = 1164 SPECTRE_V2_USER_NONE; 1165 static enum spectre_v2_user_mitigation spectre_v2_user_ibpb __ro_after_init = 1166 SPECTRE_V2_USER_NONE; 1167 1168 #ifdef CONFIG_MITIGATION_RETPOLINE 1169 static bool spectre_v2_bad_module; 1170 1171 bool retpoline_module_ok(bool has_retpoline) 1172 { 1173 if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) 1174 return true; 1175 1176 pr_err("System may be vulnerable to spectre v2\n"); 1177 spectre_v2_bad_module = true; 1178 return false; 1179 } 1180 1181 static inline const char *spectre_v2_module_string(void) 1182 { 1183 return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; 1184 } 1185 #else 1186 static inline const char *spectre_v2_module_string(void) { return ""; } 1187 #endif 1188 1189 #define SPECTRE_V2_LFENCE_MSG "WARNING: LFENCE mitigation is not recommended for this CPU, data leaks possible!\n" 1190 #define SPECTRE_V2_EIBRS_EBPF_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS on, data leaks possible via Spectre v2 BHB attacks!\n" 1191 #define SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS+LFENCE mitigation and SMT, data leaks possible via Spectre v2 BHB attacks!\n" 1192 #define SPECTRE_V2_IBRS_PERF_MSG "WARNING: IBRS mitigation selected on Enhanced IBRS CPU, this may cause unnecessary performance loss\n" 1193 1194 #ifdef CONFIG_BPF_SYSCALL 1195 void unpriv_ebpf_notify(int new_state) 1196 { 1197 if (new_state) 1198 return; 1199 1200 /* Unprivileged eBPF is enabled */ 1201 1202 switch (spectre_v2_enabled) { 1203 case SPECTRE_V2_EIBRS: 1204 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG); 1205 break; 1206 case SPECTRE_V2_EIBRS_LFENCE: 1207 if (sched_smt_active()) 1208 pr_err(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG); 1209 break; 1210 default: 1211 break; 1212 } 1213 } 1214 #endif 1215 1216 static inline bool match_option(const char *arg, int arglen, const char *opt) 1217 { 1218 int len = strlen(opt); 1219 1220 return len == arglen && !strncmp(arg, opt, len); 1221 } 1222 1223 /* The kernel command line selection for spectre v2 */ 1224 enum spectre_v2_mitigation_cmd { 1225 SPECTRE_V2_CMD_NONE, 1226 SPECTRE_V2_CMD_AUTO, 1227 SPECTRE_V2_CMD_FORCE, 1228 SPECTRE_V2_CMD_RETPOLINE, 1229 SPECTRE_V2_CMD_RETPOLINE_GENERIC, 1230 SPECTRE_V2_CMD_RETPOLINE_LFENCE, 1231 SPECTRE_V2_CMD_EIBRS, 1232 SPECTRE_V2_CMD_EIBRS_RETPOLINE, 1233 SPECTRE_V2_CMD_EIBRS_LFENCE, 1234 SPECTRE_V2_CMD_IBRS, 1235 }; 1236 1237 enum spectre_v2_user_cmd { 1238 SPECTRE_V2_USER_CMD_NONE, 1239 SPECTRE_V2_USER_CMD_AUTO, 1240 SPECTRE_V2_USER_CMD_FORCE, 1241 SPECTRE_V2_USER_CMD_PRCTL, 1242 SPECTRE_V2_USER_CMD_PRCTL_IBPB, 1243 SPECTRE_V2_USER_CMD_SECCOMP, 1244 SPECTRE_V2_USER_CMD_SECCOMP_IBPB, 1245 }; 1246 1247 static const char * const spectre_v2_user_strings[] = { 1248 [SPECTRE_V2_USER_NONE] = "User space: Vulnerable", 1249 [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection", 1250 [SPECTRE_V2_USER_STRICT_PREFERRED] = "User space: Mitigation: STIBP always-on protection", 1251 [SPECTRE_V2_USER_PRCTL] = "User space: Mitigation: STIBP via prctl", 1252 [SPECTRE_V2_USER_SECCOMP] = "User space: Mitigation: STIBP via seccomp and prctl", 1253 }; 1254 1255 static const struct { 1256 const char *option; 1257 enum spectre_v2_user_cmd cmd; 1258 bool secure; 1259 } v2_user_options[] __initconst = { 1260 { "auto", SPECTRE_V2_USER_CMD_AUTO, false }, 1261 { "off", SPECTRE_V2_USER_CMD_NONE, false }, 1262 { "on", SPECTRE_V2_USER_CMD_FORCE, true }, 1263 { "prctl", SPECTRE_V2_USER_CMD_PRCTL, false }, 1264 { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB, false }, 1265 { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP, false }, 1266 { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB, false }, 1267 }; 1268 1269 static void __init spec_v2_user_print_cond(const char *reason, bool secure) 1270 { 1271 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) 1272 pr_info("spectre_v2_user=%s forced on command line.\n", reason); 1273 } 1274 1275 static __ro_after_init enum spectre_v2_mitigation_cmd spectre_v2_cmd; 1276 1277 static enum spectre_v2_user_cmd __init 1278 spectre_v2_parse_user_cmdline(void) 1279 { 1280 char arg[20]; 1281 int ret, i; 1282 1283 switch (spectre_v2_cmd) { 1284 case SPECTRE_V2_CMD_NONE: 1285 return SPECTRE_V2_USER_CMD_NONE; 1286 case SPECTRE_V2_CMD_FORCE: 1287 return SPECTRE_V2_USER_CMD_FORCE; 1288 default: 1289 break; 1290 } 1291 1292 ret = cmdline_find_option(boot_command_line, "spectre_v2_user", 1293 arg, sizeof(arg)); 1294 if (ret < 0) 1295 return SPECTRE_V2_USER_CMD_AUTO; 1296 1297 for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) { 1298 if (match_option(arg, ret, v2_user_options[i].option)) { 1299 spec_v2_user_print_cond(v2_user_options[i].option, 1300 v2_user_options[i].secure); 1301 return v2_user_options[i].cmd; 1302 } 1303 } 1304 1305 pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg); 1306 return SPECTRE_V2_USER_CMD_AUTO; 1307 } 1308 1309 static inline bool spectre_v2_in_ibrs_mode(enum spectre_v2_mitigation mode) 1310 { 1311 return spectre_v2_in_eibrs_mode(mode) || mode == SPECTRE_V2_IBRS; 1312 } 1313 1314 static void __init 1315 spectre_v2_user_select_mitigation(void) 1316 { 1317 enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE; 1318 bool smt_possible = IS_ENABLED(CONFIG_SMP); 1319 enum spectre_v2_user_cmd cmd; 1320 1321 if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP)) 1322 return; 1323 1324 if (cpu_smt_control == CPU_SMT_FORCE_DISABLED || 1325 cpu_smt_control == CPU_SMT_NOT_SUPPORTED) 1326 smt_possible = false; 1327 1328 cmd = spectre_v2_parse_user_cmdline(); 1329 switch (cmd) { 1330 case SPECTRE_V2_USER_CMD_NONE: 1331 goto set_mode; 1332 case SPECTRE_V2_USER_CMD_FORCE: 1333 mode = SPECTRE_V2_USER_STRICT; 1334 break; 1335 case SPECTRE_V2_USER_CMD_AUTO: 1336 case SPECTRE_V2_USER_CMD_PRCTL: 1337 case SPECTRE_V2_USER_CMD_PRCTL_IBPB: 1338 mode = SPECTRE_V2_USER_PRCTL; 1339 break; 1340 case SPECTRE_V2_USER_CMD_SECCOMP: 1341 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: 1342 if (IS_ENABLED(CONFIG_SECCOMP)) 1343 mode = SPECTRE_V2_USER_SECCOMP; 1344 else 1345 mode = SPECTRE_V2_USER_PRCTL; 1346 break; 1347 } 1348 1349 /* Initialize Indirect Branch Prediction Barrier */ 1350 if (boot_cpu_has(X86_FEATURE_IBPB)) { 1351 setup_force_cpu_cap(X86_FEATURE_USE_IBPB); 1352 1353 spectre_v2_user_ibpb = mode; 1354 switch (cmd) { 1355 case SPECTRE_V2_USER_CMD_NONE: 1356 break; 1357 case SPECTRE_V2_USER_CMD_FORCE: 1358 case SPECTRE_V2_USER_CMD_PRCTL_IBPB: 1359 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: 1360 static_branch_enable(&switch_mm_always_ibpb); 1361 spectre_v2_user_ibpb = SPECTRE_V2_USER_STRICT; 1362 break; 1363 case SPECTRE_V2_USER_CMD_PRCTL: 1364 case SPECTRE_V2_USER_CMD_AUTO: 1365 case SPECTRE_V2_USER_CMD_SECCOMP: 1366 static_branch_enable(&switch_mm_cond_ibpb); 1367 break; 1368 } 1369 1370 pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n", 1371 static_key_enabled(&switch_mm_always_ibpb) ? 1372 "always-on" : "conditional"); 1373 } 1374 1375 /* 1376 * If no STIBP, Intel enhanced IBRS is enabled, or SMT impossible, STIBP 1377 * is not required. 1378 * 1379 * Intel's Enhanced IBRS also protects against cross-thread branch target 1380 * injection in user-mode as the IBRS bit remains always set which 1381 * implicitly enables cross-thread protections. However, in legacy IBRS 1382 * mode, the IBRS bit is set only on kernel entry and cleared on return 1383 * to userspace. AMD Automatic IBRS also does not protect userspace. 1384 * These modes therefore disable the implicit cross-thread protection, 1385 * so allow for STIBP to be selected in those cases. 1386 */ 1387 if (!boot_cpu_has(X86_FEATURE_STIBP) || 1388 !smt_possible || 1389 (spectre_v2_in_eibrs_mode(spectre_v2_enabled) && 1390 !boot_cpu_has(X86_FEATURE_AUTOIBRS))) 1391 return; 1392 1393 /* 1394 * At this point, an STIBP mode other than "off" has been set. 1395 * If STIBP support is not being forced, check if STIBP always-on 1396 * is preferred. 1397 */ 1398 if (mode != SPECTRE_V2_USER_STRICT && 1399 boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON)) 1400 mode = SPECTRE_V2_USER_STRICT_PREFERRED; 1401 1402 if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET || 1403 retbleed_mitigation == RETBLEED_MITIGATION_IBPB) { 1404 if (mode != SPECTRE_V2_USER_STRICT && 1405 mode != SPECTRE_V2_USER_STRICT_PREFERRED) 1406 pr_info("Selecting STIBP always-on mode to complement retbleed mitigation\n"); 1407 mode = SPECTRE_V2_USER_STRICT_PREFERRED; 1408 } 1409 1410 spectre_v2_user_stibp = mode; 1411 1412 set_mode: 1413 pr_info("%s\n", spectre_v2_user_strings[mode]); 1414 } 1415 1416 static const char * const spectre_v2_strings[] = { 1417 [SPECTRE_V2_NONE] = "Vulnerable", 1418 [SPECTRE_V2_RETPOLINE] = "Mitigation: Retpolines", 1419 [SPECTRE_V2_LFENCE] = "Mitigation: LFENCE", 1420 [SPECTRE_V2_EIBRS] = "Mitigation: Enhanced / Automatic IBRS", 1421 [SPECTRE_V2_EIBRS_LFENCE] = "Mitigation: Enhanced / Automatic IBRS + LFENCE", 1422 [SPECTRE_V2_EIBRS_RETPOLINE] = "Mitigation: Enhanced / Automatic IBRS + Retpolines", 1423 [SPECTRE_V2_IBRS] = "Mitigation: IBRS", 1424 }; 1425 1426 static const struct { 1427 const char *option; 1428 enum spectre_v2_mitigation_cmd cmd; 1429 bool secure; 1430 } mitigation_options[] __initconst = { 1431 { "off", SPECTRE_V2_CMD_NONE, false }, 1432 { "on", SPECTRE_V2_CMD_FORCE, true }, 1433 { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, 1434 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_LFENCE, false }, 1435 { "retpoline,lfence", SPECTRE_V2_CMD_RETPOLINE_LFENCE, false }, 1436 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, 1437 { "eibrs", SPECTRE_V2_CMD_EIBRS, false }, 1438 { "eibrs,lfence", SPECTRE_V2_CMD_EIBRS_LFENCE, false }, 1439 { "eibrs,retpoline", SPECTRE_V2_CMD_EIBRS_RETPOLINE, false }, 1440 { "auto", SPECTRE_V2_CMD_AUTO, false }, 1441 { "ibrs", SPECTRE_V2_CMD_IBRS, false }, 1442 }; 1443 1444 static void __init spec_v2_print_cond(const char *reason, bool secure) 1445 { 1446 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) 1447 pr_info("%s selected on command line.\n", reason); 1448 } 1449 1450 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) 1451 { 1452 enum spectre_v2_mitigation_cmd cmd; 1453 char arg[20]; 1454 int ret, i; 1455 1456 cmd = IS_ENABLED(CONFIG_MITIGATION_SPECTRE_V2) ? SPECTRE_V2_CMD_AUTO : SPECTRE_V2_CMD_NONE; 1457 if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") || 1458 cpu_mitigations_off()) 1459 return SPECTRE_V2_CMD_NONE; 1460 1461 ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); 1462 if (ret < 0) 1463 return cmd; 1464 1465 for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { 1466 if (!match_option(arg, ret, mitigation_options[i].option)) 1467 continue; 1468 cmd = mitigation_options[i].cmd; 1469 break; 1470 } 1471 1472 if (i >= ARRAY_SIZE(mitigation_options)) { 1473 pr_err("unknown option (%s). Switching to default mode\n", arg); 1474 return cmd; 1475 } 1476 1477 if ((cmd == SPECTRE_V2_CMD_RETPOLINE || 1478 cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE || 1479 cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC || 1480 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE || 1481 cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) && 1482 !IS_ENABLED(CONFIG_MITIGATION_RETPOLINE)) { 1483 pr_err("%s selected but not compiled in. Switching to AUTO select\n", 1484 mitigation_options[i].option); 1485 return SPECTRE_V2_CMD_AUTO; 1486 } 1487 1488 if ((cmd == SPECTRE_V2_CMD_EIBRS || 1489 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE || 1490 cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) && 1491 !boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { 1492 pr_err("%s selected but CPU doesn't have Enhanced or Automatic IBRS. Switching to AUTO select\n", 1493 mitigation_options[i].option); 1494 return SPECTRE_V2_CMD_AUTO; 1495 } 1496 1497 if ((cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE || 1498 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE) && 1499 !boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { 1500 pr_err("%s selected, but CPU doesn't have a serializing LFENCE. Switching to AUTO select\n", 1501 mitigation_options[i].option); 1502 return SPECTRE_V2_CMD_AUTO; 1503 } 1504 1505 if (cmd == SPECTRE_V2_CMD_IBRS && !IS_ENABLED(CONFIG_MITIGATION_IBRS_ENTRY)) { 1506 pr_err("%s selected but not compiled in. Switching to AUTO select\n", 1507 mitigation_options[i].option); 1508 return SPECTRE_V2_CMD_AUTO; 1509 } 1510 1511 if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) { 1512 pr_err("%s selected but not Intel CPU. Switching to AUTO select\n", 1513 mitigation_options[i].option); 1514 return SPECTRE_V2_CMD_AUTO; 1515 } 1516 1517 if (cmd == SPECTRE_V2_CMD_IBRS && !boot_cpu_has(X86_FEATURE_IBRS)) { 1518 pr_err("%s selected but CPU doesn't have IBRS. Switching to AUTO select\n", 1519 mitigation_options[i].option); 1520 return SPECTRE_V2_CMD_AUTO; 1521 } 1522 1523 if (cmd == SPECTRE_V2_CMD_IBRS && cpu_feature_enabled(X86_FEATURE_XENPV)) { 1524 pr_err("%s selected but running as XenPV guest. Switching to AUTO select\n", 1525 mitigation_options[i].option); 1526 return SPECTRE_V2_CMD_AUTO; 1527 } 1528 1529 spec_v2_print_cond(mitigation_options[i].option, 1530 mitigation_options[i].secure); 1531 return cmd; 1532 } 1533 1534 static enum spectre_v2_mitigation __init spectre_v2_select_retpoline(void) 1535 { 1536 if (!IS_ENABLED(CONFIG_MITIGATION_RETPOLINE)) { 1537 pr_err("Kernel not compiled with retpoline; no mitigation available!"); 1538 return SPECTRE_V2_NONE; 1539 } 1540 1541 return SPECTRE_V2_RETPOLINE; 1542 } 1543 1544 static bool __ro_after_init rrsba_disabled; 1545 1546 /* Disable in-kernel use of non-RSB RET predictors */ 1547 static void __init spec_ctrl_disable_kernel_rrsba(void) 1548 { 1549 if (rrsba_disabled) 1550 return; 1551 1552 if (!(x86_arch_cap_msr & ARCH_CAP_RRSBA)) { 1553 rrsba_disabled = true; 1554 return; 1555 } 1556 1557 if (!boot_cpu_has(X86_FEATURE_RRSBA_CTRL)) 1558 return; 1559 1560 x86_spec_ctrl_base |= SPEC_CTRL_RRSBA_DIS_S; 1561 update_spec_ctrl(x86_spec_ctrl_base); 1562 rrsba_disabled = true; 1563 } 1564 1565 static void __init spectre_v2_determine_rsb_fill_type_at_vmexit(enum spectre_v2_mitigation mode) 1566 { 1567 /* 1568 * Similar to context switches, there are two types of RSB attacks 1569 * after VM exit: 1570 * 1571 * 1) RSB underflow 1572 * 1573 * 2) Poisoned RSB entry 1574 * 1575 * When retpoline is enabled, both are mitigated by filling/clearing 1576 * the RSB. 1577 * 1578 * When IBRS is enabled, while #1 would be mitigated by the IBRS branch 1579 * prediction isolation protections, RSB still needs to be cleared 1580 * because of #2. Note that SMEP provides no protection here, unlike 1581 * user-space-poisoned RSB entries. 1582 * 1583 * eIBRS should protect against RSB poisoning, but if the EIBRS_PBRSB 1584 * bug is present then a LITE version of RSB protection is required, 1585 * just a single call needs to retire before a RET is executed. 1586 */ 1587 switch (mode) { 1588 case SPECTRE_V2_NONE: 1589 return; 1590 1591 case SPECTRE_V2_EIBRS_LFENCE: 1592 case SPECTRE_V2_EIBRS: 1593 if (boot_cpu_has_bug(X86_BUG_EIBRS_PBRSB)) { 1594 setup_force_cpu_cap(X86_FEATURE_RSB_VMEXIT_LITE); 1595 pr_info("Spectre v2 / PBRSB-eIBRS: Retire a single CALL on VMEXIT\n"); 1596 } 1597 return; 1598 1599 case SPECTRE_V2_EIBRS_RETPOLINE: 1600 case SPECTRE_V2_RETPOLINE: 1601 case SPECTRE_V2_LFENCE: 1602 case SPECTRE_V2_IBRS: 1603 setup_force_cpu_cap(X86_FEATURE_RSB_VMEXIT); 1604 pr_info("Spectre v2 / SpectreRSB : Filling RSB on VMEXIT\n"); 1605 return; 1606 } 1607 1608 pr_warn_once("Unknown Spectre v2 mode, disabling RSB mitigation at VM exit"); 1609 dump_stack(); 1610 } 1611 1612 /* 1613 * Set BHI_DIS_S to prevent indirect branches in kernel to be influenced by 1614 * branch history in userspace. Not needed if BHI_NO is set. 1615 */ 1616 static bool __init spec_ctrl_bhi_dis(void) 1617 { 1618 if (!boot_cpu_has(X86_FEATURE_BHI_CTRL)) 1619 return false; 1620 1621 x86_spec_ctrl_base |= SPEC_CTRL_BHI_DIS_S; 1622 update_spec_ctrl(x86_spec_ctrl_base); 1623 setup_force_cpu_cap(X86_FEATURE_CLEAR_BHB_HW); 1624 1625 return true; 1626 } 1627 1628 enum bhi_mitigations { 1629 BHI_MITIGATION_OFF, 1630 BHI_MITIGATION_ON, 1631 BHI_MITIGATION_VMEXIT_ONLY, 1632 }; 1633 1634 static enum bhi_mitigations bhi_mitigation __ro_after_init = 1635 IS_ENABLED(CONFIG_MITIGATION_SPECTRE_BHI) ? BHI_MITIGATION_ON : BHI_MITIGATION_OFF; 1636 1637 static int __init spectre_bhi_parse_cmdline(char *str) 1638 { 1639 if (!str) 1640 return -EINVAL; 1641 1642 if (!strcmp(str, "off")) 1643 bhi_mitigation = BHI_MITIGATION_OFF; 1644 else if (!strcmp(str, "on")) 1645 bhi_mitigation = BHI_MITIGATION_ON; 1646 else if (!strcmp(str, "vmexit")) 1647 bhi_mitigation = BHI_MITIGATION_VMEXIT_ONLY; 1648 else 1649 pr_err("Ignoring unknown spectre_bhi option (%s)", str); 1650 1651 return 0; 1652 } 1653 early_param("spectre_bhi", spectre_bhi_parse_cmdline); 1654 1655 static void __init bhi_select_mitigation(void) 1656 { 1657 if (bhi_mitigation == BHI_MITIGATION_OFF) 1658 return; 1659 1660 /* Retpoline mitigates against BHI unless the CPU has RRSBA behavior */ 1661 if (boot_cpu_has(X86_FEATURE_RETPOLINE) && 1662 !boot_cpu_has(X86_FEATURE_RETPOLINE_LFENCE)) { 1663 spec_ctrl_disable_kernel_rrsba(); 1664 if (rrsba_disabled) 1665 return; 1666 } 1667 1668 /* Mitigate in hardware if supported */ 1669 if (spec_ctrl_bhi_dis()) 1670 return; 1671 1672 if (!IS_ENABLED(CONFIG_X86_64)) 1673 return; 1674 1675 if (bhi_mitigation == BHI_MITIGATION_VMEXIT_ONLY) { 1676 pr_info("Spectre BHI mitigation: SW BHB clearing on VM exit only\n"); 1677 setup_force_cpu_cap(X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT); 1678 return; 1679 } 1680 1681 pr_info("Spectre BHI mitigation: SW BHB clearing on syscall and VM exit\n"); 1682 setup_force_cpu_cap(X86_FEATURE_CLEAR_BHB_LOOP); 1683 setup_force_cpu_cap(X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT); 1684 } 1685 1686 static void __init spectre_v2_select_mitigation(void) 1687 { 1688 enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); 1689 enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; 1690 1691 /* 1692 * If the CPU is not affected and the command line mode is NONE or AUTO 1693 * then nothing to do. 1694 */ 1695 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && 1696 (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) 1697 return; 1698 1699 switch (cmd) { 1700 case SPECTRE_V2_CMD_NONE: 1701 return; 1702 1703 case SPECTRE_V2_CMD_FORCE: 1704 case SPECTRE_V2_CMD_AUTO: 1705 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { 1706 mode = SPECTRE_V2_EIBRS; 1707 break; 1708 } 1709 1710 if (IS_ENABLED(CONFIG_MITIGATION_IBRS_ENTRY) && 1711 boot_cpu_has_bug(X86_BUG_RETBLEED) && 1712 retbleed_cmd != RETBLEED_CMD_OFF && 1713 retbleed_cmd != RETBLEED_CMD_STUFF && 1714 boot_cpu_has(X86_FEATURE_IBRS) && 1715 boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) { 1716 mode = SPECTRE_V2_IBRS; 1717 break; 1718 } 1719 1720 mode = spectre_v2_select_retpoline(); 1721 break; 1722 1723 case SPECTRE_V2_CMD_RETPOLINE_LFENCE: 1724 pr_err(SPECTRE_V2_LFENCE_MSG); 1725 mode = SPECTRE_V2_LFENCE; 1726 break; 1727 1728 case SPECTRE_V2_CMD_RETPOLINE_GENERIC: 1729 mode = SPECTRE_V2_RETPOLINE; 1730 break; 1731 1732 case SPECTRE_V2_CMD_RETPOLINE: 1733 mode = spectre_v2_select_retpoline(); 1734 break; 1735 1736 case SPECTRE_V2_CMD_IBRS: 1737 mode = SPECTRE_V2_IBRS; 1738 break; 1739 1740 case SPECTRE_V2_CMD_EIBRS: 1741 mode = SPECTRE_V2_EIBRS; 1742 break; 1743 1744 case SPECTRE_V2_CMD_EIBRS_LFENCE: 1745 mode = SPECTRE_V2_EIBRS_LFENCE; 1746 break; 1747 1748 case SPECTRE_V2_CMD_EIBRS_RETPOLINE: 1749 mode = SPECTRE_V2_EIBRS_RETPOLINE; 1750 break; 1751 } 1752 1753 if (mode == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled()) 1754 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG); 1755 1756 if (spectre_v2_in_ibrs_mode(mode)) { 1757 if (boot_cpu_has(X86_FEATURE_AUTOIBRS)) { 1758 msr_set_bit(MSR_EFER, _EFER_AUTOIBRS); 1759 } else { 1760 x86_spec_ctrl_base |= SPEC_CTRL_IBRS; 1761 update_spec_ctrl(x86_spec_ctrl_base); 1762 } 1763 } 1764 1765 switch (mode) { 1766 case SPECTRE_V2_NONE: 1767 case SPECTRE_V2_EIBRS: 1768 break; 1769 1770 case SPECTRE_V2_IBRS: 1771 setup_force_cpu_cap(X86_FEATURE_KERNEL_IBRS); 1772 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) 1773 pr_warn(SPECTRE_V2_IBRS_PERF_MSG); 1774 break; 1775 1776 case SPECTRE_V2_LFENCE: 1777 case SPECTRE_V2_EIBRS_LFENCE: 1778 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_LFENCE); 1779 fallthrough; 1780 1781 case SPECTRE_V2_RETPOLINE: 1782 case SPECTRE_V2_EIBRS_RETPOLINE: 1783 setup_force_cpu_cap(X86_FEATURE_RETPOLINE); 1784 break; 1785 } 1786 1787 /* 1788 * Disable alternate RSB predictions in kernel when indirect CALLs and 1789 * JMPs gets protection against BHI and Intramode-BTI, but RET 1790 * prediction from a non-RSB predictor is still a risk. 1791 */ 1792 if (mode == SPECTRE_V2_EIBRS_LFENCE || 1793 mode == SPECTRE_V2_EIBRS_RETPOLINE || 1794 mode == SPECTRE_V2_RETPOLINE) 1795 spec_ctrl_disable_kernel_rrsba(); 1796 1797 if (boot_cpu_has(X86_BUG_BHI)) 1798 bhi_select_mitigation(); 1799 1800 spectre_v2_enabled = mode; 1801 pr_info("%s\n", spectre_v2_strings[mode]); 1802 1803 /* 1804 * If Spectre v2 protection has been enabled, fill the RSB during a 1805 * context switch. In general there are two types of RSB attacks 1806 * across context switches, for which the CALLs/RETs may be unbalanced. 1807 * 1808 * 1) RSB underflow 1809 * 1810 * Some Intel parts have "bottomless RSB". When the RSB is empty, 1811 * speculated return targets may come from the branch predictor, 1812 * which could have a user-poisoned BTB or BHB entry. 1813 * 1814 * AMD has it even worse: *all* returns are speculated from the BTB, 1815 * regardless of the state of the RSB. 1816 * 1817 * When IBRS or eIBRS is enabled, the "user -> kernel" attack 1818 * scenario is mitigated by the IBRS branch prediction isolation 1819 * properties, so the RSB buffer filling wouldn't be necessary to 1820 * protect against this type of attack. 1821 * 1822 * The "user -> user" attack scenario is mitigated by RSB filling. 1823 * 1824 * 2) Poisoned RSB entry 1825 * 1826 * If the 'next' in-kernel return stack is shorter than 'prev', 1827 * 'next' could be tricked into speculating with a user-poisoned RSB 1828 * entry. 1829 * 1830 * The "user -> kernel" attack scenario is mitigated by SMEP and 1831 * eIBRS. 1832 * 1833 * The "user -> user" scenario, also known as SpectreBHB, requires 1834 * RSB clearing. 1835 * 1836 * So to mitigate all cases, unconditionally fill RSB on context 1837 * switches. 1838 * 1839 * FIXME: Is this pointless for retbleed-affected AMD? 1840 */ 1841 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); 1842 pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n"); 1843 1844 spectre_v2_determine_rsb_fill_type_at_vmexit(mode); 1845 1846 /* 1847 * Retpoline protects the kernel, but doesn't protect firmware. IBRS 1848 * and Enhanced IBRS protect firmware too, so enable IBRS around 1849 * firmware calls only when IBRS / Enhanced / Automatic IBRS aren't 1850 * otherwise enabled. 1851 * 1852 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because 1853 * the user might select retpoline on the kernel command line and if 1854 * the CPU supports Enhanced IBRS, kernel might un-intentionally not 1855 * enable IBRS around firmware calls. 1856 */ 1857 if (boot_cpu_has_bug(X86_BUG_RETBLEED) && 1858 boot_cpu_has(X86_FEATURE_IBPB) && 1859 (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 1860 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)) { 1861 1862 if (retbleed_cmd != RETBLEED_CMD_IBPB) { 1863 setup_force_cpu_cap(X86_FEATURE_USE_IBPB_FW); 1864 pr_info("Enabling Speculation Barrier for firmware calls\n"); 1865 } 1866 1867 } else if (boot_cpu_has(X86_FEATURE_IBRS) && !spectre_v2_in_ibrs_mode(mode)) { 1868 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); 1869 pr_info("Enabling Restricted Speculation for firmware calls\n"); 1870 } 1871 1872 /* Set up IBPB and STIBP depending on the general spectre V2 command */ 1873 spectre_v2_cmd = cmd; 1874 } 1875 1876 static void update_stibp_msr(void * __unused) 1877 { 1878 u64 val = spec_ctrl_current() | (x86_spec_ctrl_base & SPEC_CTRL_STIBP); 1879 update_spec_ctrl(val); 1880 } 1881 1882 /* Update x86_spec_ctrl_base in case SMT state changed. */ 1883 static void update_stibp_strict(void) 1884 { 1885 u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP; 1886 1887 if (sched_smt_active()) 1888 mask |= SPEC_CTRL_STIBP; 1889 1890 if (mask == x86_spec_ctrl_base) 1891 return; 1892 1893 pr_info("Update user space SMT mitigation: STIBP %s\n", 1894 mask & SPEC_CTRL_STIBP ? "always-on" : "off"); 1895 x86_spec_ctrl_base = mask; 1896 on_each_cpu(update_stibp_msr, NULL, 1); 1897 } 1898 1899 /* Update the static key controlling the evaluation of TIF_SPEC_IB */ 1900 static void update_indir_branch_cond(void) 1901 { 1902 if (sched_smt_active()) 1903 static_branch_enable(&switch_to_cond_stibp); 1904 else 1905 static_branch_disable(&switch_to_cond_stibp); 1906 } 1907 1908 #undef pr_fmt 1909 #define pr_fmt(fmt) fmt 1910 1911 /* Update the static key controlling the MDS CPU buffer clear in idle */ 1912 static void update_mds_branch_idle(void) 1913 { 1914 /* 1915 * Enable the idle clearing if SMT is active on CPUs which are 1916 * affected only by MSBDS and not any other MDS variant. 1917 * 1918 * The other variants cannot be mitigated when SMT is enabled, so 1919 * clearing the buffers on idle just to prevent the Store Buffer 1920 * repartitioning leak would be a window dressing exercise. 1921 */ 1922 if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY)) 1923 return; 1924 1925 if (sched_smt_active()) { 1926 static_branch_enable(&mds_idle_clear); 1927 } else if (mmio_mitigation == MMIO_MITIGATION_OFF || 1928 (x86_arch_cap_msr & ARCH_CAP_FBSDP_NO)) { 1929 static_branch_disable(&mds_idle_clear); 1930 } 1931 } 1932 1933 #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n" 1934 #define TAA_MSG_SMT "TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.\n" 1935 #define MMIO_MSG_SMT "MMIO Stale Data CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/processor_mmio_stale_data.html for more details.\n" 1936 1937 void cpu_bugs_smt_update(void) 1938 { 1939 mutex_lock(&spec_ctrl_mutex); 1940 1941 if (sched_smt_active() && unprivileged_ebpf_enabled() && 1942 spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE) 1943 pr_warn_once(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG); 1944 1945 switch (spectre_v2_user_stibp) { 1946 case SPECTRE_V2_USER_NONE: 1947 break; 1948 case SPECTRE_V2_USER_STRICT: 1949 case SPECTRE_V2_USER_STRICT_PREFERRED: 1950 update_stibp_strict(); 1951 break; 1952 case SPECTRE_V2_USER_PRCTL: 1953 case SPECTRE_V2_USER_SECCOMP: 1954 update_indir_branch_cond(); 1955 break; 1956 } 1957 1958 switch (mds_mitigation) { 1959 case MDS_MITIGATION_FULL: 1960 case MDS_MITIGATION_VMWERV: 1961 if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY)) 1962 pr_warn_once(MDS_MSG_SMT); 1963 update_mds_branch_idle(); 1964 break; 1965 case MDS_MITIGATION_OFF: 1966 break; 1967 } 1968 1969 switch (taa_mitigation) { 1970 case TAA_MITIGATION_VERW: 1971 case TAA_MITIGATION_UCODE_NEEDED: 1972 if (sched_smt_active()) 1973 pr_warn_once(TAA_MSG_SMT); 1974 break; 1975 case TAA_MITIGATION_TSX_DISABLED: 1976 case TAA_MITIGATION_OFF: 1977 break; 1978 } 1979 1980 switch (mmio_mitigation) { 1981 case MMIO_MITIGATION_VERW: 1982 case MMIO_MITIGATION_UCODE_NEEDED: 1983 if (sched_smt_active()) 1984 pr_warn_once(MMIO_MSG_SMT); 1985 break; 1986 case MMIO_MITIGATION_OFF: 1987 break; 1988 } 1989 1990 mutex_unlock(&spec_ctrl_mutex); 1991 } 1992 1993 #undef pr_fmt 1994 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt 1995 1996 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; 1997 1998 /* The kernel command line selection */ 1999 enum ssb_mitigation_cmd { 2000 SPEC_STORE_BYPASS_CMD_NONE, 2001 SPEC_STORE_BYPASS_CMD_AUTO, 2002 SPEC_STORE_BYPASS_CMD_ON, 2003 SPEC_STORE_BYPASS_CMD_PRCTL, 2004 SPEC_STORE_BYPASS_CMD_SECCOMP, 2005 }; 2006 2007 static const char * const ssb_strings[] = { 2008 [SPEC_STORE_BYPASS_NONE] = "Vulnerable", 2009 [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", 2010 [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", 2011 [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", 2012 }; 2013 2014 static const struct { 2015 const char *option; 2016 enum ssb_mitigation_cmd cmd; 2017 } ssb_mitigation_options[] __initconst = { 2018 { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ 2019 { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ 2020 { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ 2021 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ 2022 { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ 2023 }; 2024 2025 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) 2026 { 2027 enum ssb_mitigation_cmd cmd; 2028 char arg[20]; 2029 int ret, i; 2030 2031 cmd = IS_ENABLED(CONFIG_MITIGATION_SSB) ? 2032 SPEC_STORE_BYPASS_CMD_AUTO : SPEC_STORE_BYPASS_CMD_NONE; 2033 if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable") || 2034 cpu_mitigations_off()) { 2035 return SPEC_STORE_BYPASS_CMD_NONE; 2036 } else { 2037 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", 2038 arg, sizeof(arg)); 2039 if (ret < 0) 2040 return cmd; 2041 2042 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { 2043 if (!match_option(arg, ret, ssb_mitigation_options[i].option)) 2044 continue; 2045 2046 cmd = ssb_mitigation_options[i].cmd; 2047 break; 2048 } 2049 2050 if (i >= ARRAY_SIZE(ssb_mitigation_options)) { 2051 pr_err("unknown option (%s). Switching to default mode\n", arg); 2052 return cmd; 2053 } 2054 } 2055 2056 return cmd; 2057 } 2058 2059 static enum ssb_mitigation __init __ssb_select_mitigation(void) 2060 { 2061 enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; 2062 enum ssb_mitigation_cmd cmd; 2063 2064 if (!boot_cpu_has(X86_FEATURE_SSBD)) 2065 return mode; 2066 2067 cmd = ssb_parse_cmdline(); 2068 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && 2069 (cmd == SPEC_STORE_BYPASS_CMD_NONE || 2070 cmd == SPEC_STORE_BYPASS_CMD_AUTO)) 2071 return mode; 2072 2073 switch (cmd) { 2074 case SPEC_STORE_BYPASS_CMD_SECCOMP: 2075 /* 2076 * Choose prctl+seccomp as the default mode if seccomp is 2077 * enabled. 2078 */ 2079 if (IS_ENABLED(CONFIG_SECCOMP)) 2080 mode = SPEC_STORE_BYPASS_SECCOMP; 2081 else 2082 mode = SPEC_STORE_BYPASS_PRCTL; 2083 break; 2084 case SPEC_STORE_BYPASS_CMD_ON: 2085 mode = SPEC_STORE_BYPASS_DISABLE; 2086 break; 2087 case SPEC_STORE_BYPASS_CMD_AUTO: 2088 case SPEC_STORE_BYPASS_CMD_PRCTL: 2089 mode = SPEC_STORE_BYPASS_PRCTL; 2090 break; 2091 case SPEC_STORE_BYPASS_CMD_NONE: 2092 break; 2093 } 2094 2095 /* 2096 * We have three CPU feature flags that are in play here: 2097 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. 2098 * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass 2099 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation 2100 */ 2101 if (mode == SPEC_STORE_BYPASS_DISABLE) { 2102 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); 2103 /* 2104 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may 2105 * use a completely different MSR and bit dependent on family. 2106 */ 2107 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) && 2108 !static_cpu_has(X86_FEATURE_AMD_SSBD)) { 2109 x86_amd_ssb_disable(); 2110 } else { 2111 x86_spec_ctrl_base |= SPEC_CTRL_SSBD; 2112 update_spec_ctrl(x86_spec_ctrl_base); 2113 } 2114 } 2115 2116 return mode; 2117 } 2118 2119 static void ssb_select_mitigation(void) 2120 { 2121 ssb_mode = __ssb_select_mitigation(); 2122 2123 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 2124 pr_info("%s\n", ssb_strings[ssb_mode]); 2125 } 2126 2127 #undef pr_fmt 2128 #define pr_fmt(fmt) "Speculation prctl: " fmt 2129 2130 static void task_update_spec_tif(struct task_struct *tsk) 2131 { 2132 /* Force the update of the real TIF bits */ 2133 set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE); 2134 2135 /* 2136 * Immediately update the speculation control MSRs for the current 2137 * task, but for a non-current task delay setting the CPU 2138 * mitigation until it is scheduled next. 2139 * 2140 * This can only happen for SECCOMP mitigation. For PRCTL it's 2141 * always the current task. 2142 */ 2143 if (tsk == current) 2144 speculation_ctrl_update_current(); 2145 } 2146 2147 static int l1d_flush_prctl_set(struct task_struct *task, unsigned long ctrl) 2148 { 2149 2150 if (!static_branch_unlikely(&switch_mm_cond_l1d_flush)) 2151 return -EPERM; 2152 2153 switch (ctrl) { 2154 case PR_SPEC_ENABLE: 2155 set_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH); 2156 return 0; 2157 case PR_SPEC_DISABLE: 2158 clear_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH); 2159 return 0; 2160 default: 2161 return -ERANGE; 2162 } 2163 } 2164 2165 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) 2166 { 2167 if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && 2168 ssb_mode != SPEC_STORE_BYPASS_SECCOMP) 2169 return -ENXIO; 2170 2171 switch (ctrl) { 2172 case PR_SPEC_ENABLE: 2173 /* If speculation is force disabled, enable is not allowed */ 2174 if (task_spec_ssb_force_disable(task)) 2175 return -EPERM; 2176 task_clear_spec_ssb_disable(task); 2177 task_clear_spec_ssb_noexec(task); 2178 task_update_spec_tif(task); 2179 break; 2180 case PR_SPEC_DISABLE: 2181 task_set_spec_ssb_disable(task); 2182 task_clear_spec_ssb_noexec(task); 2183 task_update_spec_tif(task); 2184 break; 2185 case PR_SPEC_FORCE_DISABLE: 2186 task_set_spec_ssb_disable(task); 2187 task_set_spec_ssb_force_disable(task); 2188 task_clear_spec_ssb_noexec(task); 2189 task_update_spec_tif(task); 2190 break; 2191 case PR_SPEC_DISABLE_NOEXEC: 2192 if (task_spec_ssb_force_disable(task)) 2193 return -EPERM; 2194 task_set_spec_ssb_disable(task); 2195 task_set_spec_ssb_noexec(task); 2196 task_update_spec_tif(task); 2197 break; 2198 default: 2199 return -ERANGE; 2200 } 2201 return 0; 2202 } 2203 2204 static bool is_spec_ib_user_controlled(void) 2205 { 2206 return spectre_v2_user_ibpb == SPECTRE_V2_USER_PRCTL || 2207 spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP || 2208 spectre_v2_user_stibp == SPECTRE_V2_USER_PRCTL || 2209 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP; 2210 } 2211 2212 static int ib_prctl_set(struct task_struct *task, unsigned long ctrl) 2213 { 2214 switch (ctrl) { 2215 case PR_SPEC_ENABLE: 2216 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE && 2217 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE) 2218 return 0; 2219 2220 /* 2221 * With strict mode for both IBPB and STIBP, the instruction 2222 * code paths avoid checking this task flag and instead, 2223 * unconditionally run the instruction. However, STIBP and IBPB 2224 * are independent and either can be set to conditionally 2225 * enabled regardless of the mode of the other. 2226 * 2227 * If either is set to conditional, allow the task flag to be 2228 * updated, unless it was force-disabled by a previous prctl 2229 * call. Currently, this is possible on an AMD CPU which has the 2230 * feature X86_FEATURE_AMD_STIBP_ALWAYS_ON. In this case, if the 2231 * kernel is booted with 'spectre_v2_user=seccomp', then 2232 * spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP and 2233 * spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED. 2234 */ 2235 if (!is_spec_ib_user_controlled() || 2236 task_spec_ib_force_disable(task)) 2237 return -EPERM; 2238 2239 task_clear_spec_ib_disable(task); 2240 task_update_spec_tif(task); 2241 break; 2242 case PR_SPEC_DISABLE: 2243 case PR_SPEC_FORCE_DISABLE: 2244 /* 2245 * Indirect branch speculation is always allowed when 2246 * mitigation is force disabled. 2247 */ 2248 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE && 2249 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE) 2250 return -EPERM; 2251 2252 if (!is_spec_ib_user_controlled()) 2253 return 0; 2254 2255 task_set_spec_ib_disable(task); 2256 if (ctrl == PR_SPEC_FORCE_DISABLE) 2257 task_set_spec_ib_force_disable(task); 2258 task_update_spec_tif(task); 2259 if (task == current) 2260 indirect_branch_prediction_barrier(); 2261 break; 2262 default: 2263 return -ERANGE; 2264 } 2265 return 0; 2266 } 2267 2268 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, 2269 unsigned long ctrl) 2270 { 2271 switch (which) { 2272 case PR_SPEC_STORE_BYPASS: 2273 return ssb_prctl_set(task, ctrl); 2274 case PR_SPEC_INDIRECT_BRANCH: 2275 return ib_prctl_set(task, ctrl); 2276 case PR_SPEC_L1D_FLUSH: 2277 return l1d_flush_prctl_set(task, ctrl); 2278 default: 2279 return -ENODEV; 2280 } 2281 } 2282 2283 #ifdef CONFIG_SECCOMP 2284 void arch_seccomp_spec_mitigate(struct task_struct *task) 2285 { 2286 if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) 2287 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); 2288 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP || 2289 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP) 2290 ib_prctl_set(task, PR_SPEC_FORCE_DISABLE); 2291 } 2292 #endif 2293 2294 static int l1d_flush_prctl_get(struct task_struct *task) 2295 { 2296 if (!static_branch_unlikely(&switch_mm_cond_l1d_flush)) 2297 return PR_SPEC_FORCE_DISABLE; 2298 2299 if (test_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH)) 2300 return PR_SPEC_PRCTL | PR_SPEC_ENABLE; 2301 else 2302 return PR_SPEC_PRCTL | PR_SPEC_DISABLE; 2303 } 2304 2305 static int ssb_prctl_get(struct task_struct *task) 2306 { 2307 switch (ssb_mode) { 2308 case SPEC_STORE_BYPASS_NONE: 2309 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 2310 return PR_SPEC_ENABLE; 2311 return PR_SPEC_NOT_AFFECTED; 2312 case SPEC_STORE_BYPASS_DISABLE: 2313 return PR_SPEC_DISABLE; 2314 case SPEC_STORE_BYPASS_SECCOMP: 2315 case SPEC_STORE_BYPASS_PRCTL: 2316 if (task_spec_ssb_force_disable(task)) 2317 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; 2318 if (task_spec_ssb_noexec(task)) 2319 return PR_SPEC_PRCTL | PR_SPEC_DISABLE_NOEXEC; 2320 if (task_spec_ssb_disable(task)) 2321 return PR_SPEC_PRCTL | PR_SPEC_DISABLE; 2322 return PR_SPEC_PRCTL | PR_SPEC_ENABLE; 2323 } 2324 BUG(); 2325 } 2326 2327 static int ib_prctl_get(struct task_struct *task) 2328 { 2329 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) 2330 return PR_SPEC_NOT_AFFECTED; 2331 2332 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE && 2333 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE) 2334 return PR_SPEC_ENABLE; 2335 else if (is_spec_ib_user_controlled()) { 2336 if (task_spec_ib_force_disable(task)) 2337 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; 2338 if (task_spec_ib_disable(task)) 2339 return PR_SPEC_PRCTL | PR_SPEC_DISABLE; 2340 return PR_SPEC_PRCTL | PR_SPEC_ENABLE; 2341 } else if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT || 2342 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT || 2343 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED) 2344 return PR_SPEC_DISABLE; 2345 else 2346 return PR_SPEC_NOT_AFFECTED; 2347 } 2348 2349 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) 2350 { 2351 switch (which) { 2352 case PR_SPEC_STORE_BYPASS: 2353 return ssb_prctl_get(task); 2354 case PR_SPEC_INDIRECT_BRANCH: 2355 return ib_prctl_get(task); 2356 case PR_SPEC_L1D_FLUSH: 2357 return l1d_flush_prctl_get(task); 2358 default: 2359 return -ENODEV; 2360 } 2361 } 2362 2363 void x86_spec_ctrl_setup_ap(void) 2364 { 2365 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) 2366 update_spec_ctrl(x86_spec_ctrl_base); 2367 2368 if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) 2369 x86_amd_ssb_disable(); 2370 } 2371 2372 bool itlb_multihit_kvm_mitigation; 2373 EXPORT_SYMBOL_GPL(itlb_multihit_kvm_mitigation); 2374 2375 #undef pr_fmt 2376 #define pr_fmt(fmt) "L1TF: " fmt 2377 2378 /* Default mitigation for L1TF-affected CPUs */ 2379 enum l1tf_mitigations l1tf_mitigation __ro_after_init = 2380 IS_ENABLED(CONFIG_MITIGATION_L1TF) ? L1TF_MITIGATION_FLUSH : L1TF_MITIGATION_OFF; 2381 #if IS_ENABLED(CONFIG_KVM_INTEL) 2382 EXPORT_SYMBOL_GPL(l1tf_mitigation); 2383 #endif 2384 enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; 2385 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation); 2386 2387 /* 2388 * These CPUs all support 44bits physical address space internally in the 2389 * cache but CPUID can report a smaller number of physical address bits. 2390 * 2391 * The L1TF mitigation uses the top most address bit for the inversion of 2392 * non present PTEs. When the installed memory reaches into the top most 2393 * address bit due to memory holes, which has been observed on machines 2394 * which report 36bits physical address bits and have 32G RAM installed, 2395 * then the mitigation range check in l1tf_select_mitigation() triggers. 2396 * This is a false positive because the mitigation is still possible due to 2397 * the fact that the cache uses 44bit internally. Use the cache bits 2398 * instead of the reported physical bits and adjust them on the affected 2399 * machines to 44bit if the reported bits are less than 44. 2400 */ 2401 static void override_cache_bits(struct cpuinfo_x86 *c) 2402 { 2403 if (c->x86 != 6) 2404 return; 2405 2406 switch (c->x86_vfm) { 2407 case INTEL_NEHALEM: 2408 case INTEL_WESTMERE: 2409 case INTEL_SANDYBRIDGE: 2410 case INTEL_IVYBRIDGE: 2411 case INTEL_HASWELL: 2412 case INTEL_HASWELL_L: 2413 case INTEL_HASWELL_G: 2414 case INTEL_BROADWELL: 2415 case INTEL_BROADWELL_G: 2416 case INTEL_SKYLAKE_L: 2417 case INTEL_SKYLAKE: 2418 case INTEL_KABYLAKE_L: 2419 case INTEL_KABYLAKE: 2420 if (c->x86_cache_bits < 44) 2421 c->x86_cache_bits = 44; 2422 break; 2423 } 2424 } 2425 2426 static void __init l1tf_select_mitigation(void) 2427 { 2428 u64 half_pa; 2429 2430 if (!boot_cpu_has_bug(X86_BUG_L1TF)) 2431 return; 2432 2433 if (cpu_mitigations_off()) 2434 l1tf_mitigation = L1TF_MITIGATION_OFF; 2435 else if (cpu_mitigations_auto_nosmt()) 2436 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; 2437 2438 override_cache_bits(&boot_cpu_data); 2439 2440 switch (l1tf_mitigation) { 2441 case L1TF_MITIGATION_OFF: 2442 case L1TF_MITIGATION_FLUSH_NOWARN: 2443 case L1TF_MITIGATION_FLUSH: 2444 break; 2445 case L1TF_MITIGATION_FLUSH_NOSMT: 2446 case L1TF_MITIGATION_FULL: 2447 cpu_smt_disable(false); 2448 break; 2449 case L1TF_MITIGATION_FULL_FORCE: 2450 cpu_smt_disable(true); 2451 break; 2452 } 2453 2454 #if CONFIG_PGTABLE_LEVELS == 2 2455 pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n"); 2456 return; 2457 #endif 2458 2459 half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT; 2460 if (l1tf_mitigation != L1TF_MITIGATION_OFF && 2461 e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) { 2462 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n"); 2463 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n", 2464 half_pa); 2465 pr_info("However, doing so will make a part of your RAM unusable.\n"); 2466 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n"); 2467 return; 2468 } 2469 2470 setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV); 2471 } 2472 2473 static int __init l1tf_cmdline(char *str) 2474 { 2475 if (!boot_cpu_has_bug(X86_BUG_L1TF)) 2476 return 0; 2477 2478 if (!str) 2479 return -EINVAL; 2480 2481 if (!strcmp(str, "off")) 2482 l1tf_mitigation = L1TF_MITIGATION_OFF; 2483 else if (!strcmp(str, "flush,nowarn")) 2484 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN; 2485 else if (!strcmp(str, "flush")) 2486 l1tf_mitigation = L1TF_MITIGATION_FLUSH; 2487 else if (!strcmp(str, "flush,nosmt")) 2488 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; 2489 else if (!strcmp(str, "full")) 2490 l1tf_mitigation = L1TF_MITIGATION_FULL; 2491 else if (!strcmp(str, "full,force")) 2492 l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE; 2493 2494 return 0; 2495 } 2496 early_param("l1tf", l1tf_cmdline); 2497 2498 #undef pr_fmt 2499 #define pr_fmt(fmt) "Speculative Return Stack Overflow: " fmt 2500 2501 enum srso_mitigation { 2502 SRSO_MITIGATION_NONE, 2503 SRSO_MITIGATION_UCODE_NEEDED, 2504 SRSO_MITIGATION_SAFE_RET_UCODE_NEEDED, 2505 SRSO_MITIGATION_MICROCODE, 2506 SRSO_MITIGATION_SAFE_RET, 2507 SRSO_MITIGATION_IBPB, 2508 SRSO_MITIGATION_IBPB_ON_VMEXIT, 2509 }; 2510 2511 enum srso_mitigation_cmd { 2512 SRSO_CMD_OFF, 2513 SRSO_CMD_MICROCODE, 2514 SRSO_CMD_SAFE_RET, 2515 SRSO_CMD_IBPB, 2516 SRSO_CMD_IBPB_ON_VMEXIT, 2517 }; 2518 2519 static const char * const srso_strings[] = { 2520 [SRSO_MITIGATION_NONE] = "Vulnerable", 2521 [SRSO_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode", 2522 [SRSO_MITIGATION_SAFE_RET_UCODE_NEEDED] = "Vulnerable: Safe RET, no microcode", 2523 [SRSO_MITIGATION_MICROCODE] = "Vulnerable: Microcode, no safe RET", 2524 [SRSO_MITIGATION_SAFE_RET] = "Mitigation: Safe RET", 2525 [SRSO_MITIGATION_IBPB] = "Mitigation: IBPB", 2526 [SRSO_MITIGATION_IBPB_ON_VMEXIT] = "Mitigation: IBPB on VMEXIT only" 2527 }; 2528 2529 static enum srso_mitigation srso_mitigation __ro_after_init = SRSO_MITIGATION_NONE; 2530 static enum srso_mitigation_cmd srso_cmd __ro_after_init = SRSO_CMD_SAFE_RET; 2531 2532 static int __init srso_parse_cmdline(char *str) 2533 { 2534 if (!str) 2535 return -EINVAL; 2536 2537 if (!strcmp(str, "off")) 2538 srso_cmd = SRSO_CMD_OFF; 2539 else if (!strcmp(str, "microcode")) 2540 srso_cmd = SRSO_CMD_MICROCODE; 2541 else if (!strcmp(str, "safe-ret")) 2542 srso_cmd = SRSO_CMD_SAFE_RET; 2543 else if (!strcmp(str, "ibpb")) 2544 srso_cmd = SRSO_CMD_IBPB; 2545 else if (!strcmp(str, "ibpb-vmexit")) 2546 srso_cmd = SRSO_CMD_IBPB_ON_VMEXIT; 2547 else 2548 pr_err("Ignoring unknown SRSO option (%s).", str); 2549 2550 return 0; 2551 } 2552 early_param("spec_rstack_overflow", srso_parse_cmdline); 2553 2554 #define SRSO_NOTICE "WARNING: See https://kernel.org/doc/html/latest/admin-guide/hw-vuln/srso.html for mitigation options." 2555 2556 static void __init srso_select_mitigation(void) 2557 { 2558 bool has_microcode = boot_cpu_has(X86_FEATURE_IBPB_BRTYPE); 2559 2560 if (!boot_cpu_has_bug(X86_BUG_SRSO) || 2561 cpu_mitigations_off() || 2562 srso_cmd == SRSO_CMD_OFF) { 2563 if (boot_cpu_has(X86_FEATURE_SBPB)) 2564 x86_pred_cmd = PRED_CMD_SBPB; 2565 return; 2566 } 2567 2568 if (has_microcode) { 2569 /* 2570 * Zen1/2 with SMT off aren't vulnerable after the right 2571 * IBPB microcode has been applied. 2572 * 2573 * Zen1/2 don't have SBPB, no need to try to enable it here. 2574 */ 2575 if (boot_cpu_data.x86 < 0x19 && !cpu_smt_possible()) { 2576 setup_force_cpu_cap(X86_FEATURE_SRSO_NO); 2577 return; 2578 } 2579 2580 if (retbleed_mitigation == RETBLEED_MITIGATION_IBPB) { 2581 srso_mitigation = SRSO_MITIGATION_IBPB; 2582 goto out; 2583 } 2584 } else { 2585 pr_warn("IBPB-extending microcode not applied!\n"); 2586 pr_warn(SRSO_NOTICE); 2587 2588 /* may be overwritten by SRSO_CMD_SAFE_RET below */ 2589 srso_mitigation = SRSO_MITIGATION_UCODE_NEEDED; 2590 } 2591 2592 switch (srso_cmd) { 2593 case SRSO_CMD_MICROCODE: 2594 if (has_microcode) { 2595 srso_mitigation = SRSO_MITIGATION_MICROCODE; 2596 pr_warn(SRSO_NOTICE); 2597 } 2598 break; 2599 2600 case SRSO_CMD_SAFE_RET: 2601 if (IS_ENABLED(CONFIG_MITIGATION_SRSO)) { 2602 /* 2603 * Enable the return thunk for generated code 2604 * like ftrace, static_call, etc. 2605 */ 2606 setup_force_cpu_cap(X86_FEATURE_RETHUNK); 2607 setup_force_cpu_cap(X86_FEATURE_UNRET); 2608 2609 if (boot_cpu_data.x86 == 0x19) { 2610 setup_force_cpu_cap(X86_FEATURE_SRSO_ALIAS); 2611 x86_return_thunk = srso_alias_return_thunk; 2612 } else { 2613 setup_force_cpu_cap(X86_FEATURE_SRSO); 2614 x86_return_thunk = srso_return_thunk; 2615 } 2616 if (has_microcode) 2617 srso_mitigation = SRSO_MITIGATION_SAFE_RET; 2618 else 2619 srso_mitigation = SRSO_MITIGATION_SAFE_RET_UCODE_NEEDED; 2620 } else { 2621 pr_err("WARNING: kernel not compiled with MITIGATION_SRSO.\n"); 2622 } 2623 break; 2624 2625 case SRSO_CMD_IBPB: 2626 if (IS_ENABLED(CONFIG_MITIGATION_IBPB_ENTRY)) { 2627 if (has_microcode) { 2628 setup_force_cpu_cap(X86_FEATURE_ENTRY_IBPB); 2629 srso_mitigation = SRSO_MITIGATION_IBPB; 2630 } 2631 } else { 2632 pr_err("WARNING: kernel not compiled with MITIGATION_IBPB_ENTRY.\n"); 2633 } 2634 break; 2635 2636 case SRSO_CMD_IBPB_ON_VMEXIT: 2637 if (IS_ENABLED(CONFIG_MITIGATION_SRSO)) { 2638 if (!boot_cpu_has(X86_FEATURE_ENTRY_IBPB) && has_microcode) { 2639 setup_force_cpu_cap(X86_FEATURE_IBPB_ON_VMEXIT); 2640 srso_mitigation = SRSO_MITIGATION_IBPB_ON_VMEXIT; 2641 } 2642 } else { 2643 pr_err("WARNING: kernel not compiled with MITIGATION_SRSO.\n"); 2644 } 2645 break; 2646 default: 2647 break; 2648 } 2649 2650 out: 2651 pr_info("%s\n", srso_strings[srso_mitigation]); 2652 } 2653 2654 #undef pr_fmt 2655 #define pr_fmt(fmt) fmt 2656 2657 #ifdef CONFIG_SYSFS 2658 2659 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion" 2660 2661 #if IS_ENABLED(CONFIG_KVM_INTEL) 2662 static const char * const l1tf_vmx_states[] = { 2663 [VMENTER_L1D_FLUSH_AUTO] = "auto", 2664 [VMENTER_L1D_FLUSH_NEVER] = "vulnerable", 2665 [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes", 2666 [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes", 2667 [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled", 2668 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary" 2669 }; 2670 2671 static ssize_t l1tf_show_state(char *buf) 2672 { 2673 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) 2674 return sysfs_emit(buf, "%s\n", L1TF_DEFAULT_MSG); 2675 2676 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED || 2677 (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER && 2678 sched_smt_active())) { 2679 return sysfs_emit(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG, 2680 l1tf_vmx_states[l1tf_vmx_mitigation]); 2681 } 2682 2683 return sysfs_emit(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG, 2684 l1tf_vmx_states[l1tf_vmx_mitigation], 2685 sched_smt_active() ? "vulnerable" : "disabled"); 2686 } 2687 2688 static ssize_t itlb_multihit_show_state(char *buf) 2689 { 2690 if (!boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || 2691 !boot_cpu_has(X86_FEATURE_VMX)) 2692 return sysfs_emit(buf, "KVM: Mitigation: VMX unsupported\n"); 2693 else if (!(cr4_read_shadow() & X86_CR4_VMXE)) 2694 return sysfs_emit(buf, "KVM: Mitigation: VMX disabled\n"); 2695 else if (itlb_multihit_kvm_mitigation) 2696 return sysfs_emit(buf, "KVM: Mitigation: Split huge pages\n"); 2697 else 2698 return sysfs_emit(buf, "KVM: Vulnerable\n"); 2699 } 2700 #else 2701 static ssize_t l1tf_show_state(char *buf) 2702 { 2703 return sysfs_emit(buf, "%s\n", L1TF_DEFAULT_MSG); 2704 } 2705 2706 static ssize_t itlb_multihit_show_state(char *buf) 2707 { 2708 return sysfs_emit(buf, "Processor vulnerable\n"); 2709 } 2710 #endif 2711 2712 static ssize_t mds_show_state(char *buf) 2713 { 2714 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { 2715 return sysfs_emit(buf, "%s; SMT Host state unknown\n", 2716 mds_strings[mds_mitigation]); 2717 } 2718 2719 if (boot_cpu_has(X86_BUG_MSBDS_ONLY)) { 2720 return sysfs_emit(buf, "%s; SMT %s\n", mds_strings[mds_mitigation], 2721 (mds_mitigation == MDS_MITIGATION_OFF ? "vulnerable" : 2722 sched_smt_active() ? "mitigated" : "disabled")); 2723 } 2724 2725 return sysfs_emit(buf, "%s; SMT %s\n", mds_strings[mds_mitigation], 2726 sched_smt_active() ? "vulnerable" : "disabled"); 2727 } 2728 2729 static ssize_t tsx_async_abort_show_state(char *buf) 2730 { 2731 if ((taa_mitigation == TAA_MITIGATION_TSX_DISABLED) || 2732 (taa_mitigation == TAA_MITIGATION_OFF)) 2733 return sysfs_emit(buf, "%s\n", taa_strings[taa_mitigation]); 2734 2735 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { 2736 return sysfs_emit(buf, "%s; SMT Host state unknown\n", 2737 taa_strings[taa_mitigation]); 2738 } 2739 2740 return sysfs_emit(buf, "%s; SMT %s\n", taa_strings[taa_mitigation], 2741 sched_smt_active() ? "vulnerable" : "disabled"); 2742 } 2743 2744 static ssize_t mmio_stale_data_show_state(char *buf) 2745 { 2746 if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN)) 2747 return sysfs_emit(buf, "Unknown: No mitigations\n"); 2748 2749 if (mmio_mitigation == MMIO_MITIGATION_OFF) 2750 return sysfs_emit(buf, "%s\n", mmio_strings[mmio_mitigation]); 2751 2752 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { 2753 return sysfs_emit(buf, "%s; SMT Host state unknown\n", 2754 mmio_strings[mmio_mitigation]); 2755 } 2756 2757 return sysfs_emit(buf, "%s; SMT %s\n", mmio_strings[mmio_mitigation], 2758 sched_smt_active() ? "vulnerable" : "disabled"); 2759 } 2760 2761 static ssize_t rfds_show_state(char *buf) 2762 { 2763 return sysfs_emit(buf, "%s\n", rfds_strings[rfds_mitigation]); 2764 } 2765 2766 static char *stibp_state(void) 2767 { 2768 if (spectre_v2_in_eibrs_mode(spectre_v2_enabled) && 2769 !boot_cpu_has(X86_FEATURE_AUTOIBRS)) 2770 return ""; 2771 2772 switch (spectre_v2_user_stibp) { 2773 case SPECTRE_V2_USER_NONE: 2774 return "; STIBP: disabled"; 2775 case SPECTRE_V2_USER_STRICT: 2776 return "; STIBP: forced"; 2777 case SPECTRE_V2_USER_STRICT_PREFERRED: 2778 return "; STIBP: always-on"; 2779 case SPECTRE_V2_USER_PRCTL: 2780 case SPECTRE_V2_USER_SECCOMP: 2781 if (static_key_enabled(&switch_to_cond_stibp)) 2782 return "; STIBP: conditional"; 2783 } 2784 return ""; 2785 } 2786 2787 static char *ibpb_state(void) 2788 { 2789 if (boot_cpu_has(X86_FEATURE_IBPB)) { 2790 if (static_key_enabled(&switch_mm_always_ibpb)) 2791 return "; IBPB: always-on"; 2792 if (static_key_enabled(&switch_mm_cond_ibpb)) 2793 return "; IBPB: conditional"; 2794 return "; IBPB: disabled"; 2795 } 2796 return ""; 2797 } 2798 2799 static char *pbrsb_eibrs_state(void) 2800 { 2801 if (boot_cpu_has_bug(X86_BUG_EIBRS_PBRSB)) { 2802 if (boot_cpu_has(X86_FEATURE_RSB_VMEXIT_LITE) || 2803 boot_cpu_has(X86_FEATURE_RSB_VMEXIT)) 2804 return "; PBRSB-eIBRS: SW sequence"; 2805 else 2806 return "; PBRSB-eIBRS: Vulnerable"; 2807 } else { 2808 return "; PBRSB-eIBRS: Not affected"; 2809 } 2810 } 2811 2812 static const char *spectre_bhi_state(void) 2813 { 2814 if (!boot_cpu_has_bug(X86_BUG_BHI)) 2815 return "; BHI: Not affected"; 2816 else if (boot_cpu_has(X86_FEATURE_CLEAR_BHB_HW)) 2817 return "; BHI: BHI_DIS_S"; 2818 else if (boot_cpu_has(X86_FEATURE_CLEAR_BHB_LOOP)) 2819 return "; BHI: SW loop, KVM: SW loop"; 2820 else if (boot_cpu_has(X86_FEATURE_RETPOLINE) && 2821 !boot_cpu_has(X86_FEATURE_RETPOLINE_LFENCE) && 2822 rrsba_disabled) 2823 return "; BHI: Retpoline"; 2824 else if (boot_cpu_has(X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT)) 2825 return "; BHI: Vulnerable, KVM: SW loop"; 2826 2827 return "; BHI: Vulnerable"; 2828 } 2829 2830 static ssize_t spectre_v2_show_state(char *buf) 2831 { 2832 if (spectre_v2_enabled == SPECTRE_V2_LFENCE) 2833 return sysfs_emit(buf, "Vulnerable: LFENCE\n"); 2834 2835 if (spectre_v2_enabled == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled()) 2836 return sysfs_emit(buf, "Vulnerable: eIBRS with unprivileged eBPF\n"); 2837 2838 if (sched_smt_active() && unprivileged_ebpf_enabled() && 2839 spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE) 2840 return sysfs_emit(buf, "Vulnerable: eIBRS+LFENCE with unprivileged eBPF and SMT\n"); 2841 2842 return sysfs_emit(buf, "%s%s%s%s%s%s%s%s\n", 2843 spectre_v2_strings[spectre_v2_enabled], 2844 ibpb_state(), 2845 boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? "; IBRS_FW" : "", 2846 stibp_state(), 2847 boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? "; RSB filling" : "", 2848 pbrsb_eibrs_state(), 2849 spectre_bhi_state(), 2850 /* this should always be at the end */ 2851 spectre_v2_module_string()); 2852 } 2853 2854 static ssize_t srbds_show_state(char *buf) 2855 { 2856 return sysfs_emit(buf, "%s\n", srbds_strings[srbds_mitigation]); 2857 } 2858 2859 static ssize_t retbleed_show_state(char *buf) 2860 { 2861 if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET || 2862 retbleed_mitigation == RETBLEED_MITIGATION_IBPB) { 2863 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD && 2864 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON) 2865 return sysfs_emit(buf, "Vulnerable: untrained return thunk / IBPB on non-AMD based uarch\n"); 2866 2867 return sysfs_emit(buf, "%s; SMT %s\n", retbleed_strings[retbleed_mitigation], 2868 !sched_smt_active() ? "disabled" : 2869 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT || 2870 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED ? 2871 "enabled with STIBP protection" : "vulnerable"); 2872 } 2873 2874 return sysfs_emit(buf, "%s\n", retbleed_strings[retbleed_mitigation]); 2875 } 2876 2877 static ssize_t srso_show_state(char *buf) 2878 { 2879 if (boot_cpu_has(X86_FEATURE_SRSO_NO)) 2880 return sysfs_emit(buf, "Mitigation: SMT disabled\n"); 2881 2882 return sysfs_emit(buf, "%s\n", srso_strings[srso_mitigation]); 2883 } 2884 2885 static ssize_t gds_show_state(char *buf) 2886 { 2887 return sysfs_emit(buf, "%s\n", gds_strings[gds_mitigation]); 2888 } 2889 2890 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, 2891 char *buf, unsigned int bug) 2892 { 2893 if (!boot_cpu_has_bug(bug)) 2894 return sysfs_emit(buf, "Not affected\n"); 2895 2896 switch (bug) { 2897 case X86_BUG_CPU_MELTDOWN: 2898 if (boot_cpu_has(X86_FEATURE_PTI)) 2899 return sysfs_emit(buf, "Mitigation: PTI\n"); 2900 2901 if (hypervisor_is_type(X86_HYPER_XEN_PV)) 2902 return sysfs_emit(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n"); 2903 2904 break; 2905 2906 case X86_BUG_SPECTRE_V1: 2907 return sysfs_emit(buf, "%s\n", spectre_v1_strings[spectre_v1_mitigation]); 2908 2909 case X86_BUG_SPECTRE_V2: 2910 return spectre_v2_show_state(buf); 2911 2912 case X86_BUG_SPEC_STORE_BYPASS: 2913 return sysfs_emit(buf, "%s\n", ssb_strings[ssb_mode]); 2914 2915 case X86_BUG_L1TF: 2916 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV)) 2917 return l1tf_show_state(buf); 2918 break; 2919 2920 case X86_BUG_MDS: 2921 return mds_show_state(buf); 2922 2923 case X86_BUG_TAA: 2924 return tsx_async_abort_show_state(buf); 2925 2926 case X86_BUG_ITLB_MULTIHIT: 2927 return itlb_multihit_show_state(buf); 2928 2929 case X86_BUG_SRBDS: 2930 return srbds_show_state(buf); 2931 2932 case X86_BUG_MMIO_STALE_DATA: 2933 case X86_BUG_MMIO_UNKNOWN: 2934 return mmio_stale_data_show_state(buf); 2935 2936 case X86_BUG_RETBLEED: 2937 return retbleed_show_state(buf); 2938 2939 case X86_BUG_SRSO: 2940 return srso_show_state(buf); 2941 2942 case X86_BUG_GDS: 2943 return gds_show_state(buf); 2944 2945 case X86_BUG_RFDS: 2946 return rfds_show_state(buf); 2947 2948 default: 2949 break; 2950 } 2951 2952 return sysfs_emit(buf, "Vulnerable\n"); 2953 } 2954 2955 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) 2956 { 2957 return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); 2958 } 2959 2960 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) 2961 { 2962 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); 2963 } 2964 2965 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) 2966 { 2967 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); 2968 } 2969 2970 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) 2971 { 2972 return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); 2973 } 2974 2975 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf) 2976 { 2977 return cpu_show_common(dev, attr, buf, X86_BUG_L1TF); 2978 } 2979 2980 ssize_t cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf) 2981 { 2982 return cpu_show_common(dev, attr, buf, X86_BUG_MDS); 2983 } 2984 2985 ssize_t cpu_show_tsx_async_abort(struct device *dev, struct device_attribute *attr, char *buf) 2986 { 2987 return cpu_show_common(dev, attr, buf, X86_BUG_TAA); 2988 } 2989 2990 ssize_t cpu_show_itlb_multihit(struct device *dev, struct device_attribute *attr, char *buf) 2991 { 2992 return cpu_show_common(dev, attr, buf, X86_BUG_ITLB_MULTIHIT); 2993 } 2994 2995 ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *buf) 2996 { 2997 return cpu_show_common(dev, attr, buf, X86_BUG_SRBDS); 2998 } 2999 3000 ssize_t cpu_show_mmio_stale_data(struct device *dev, struct device_attribute *attr, char *buf) 3001 { 3002 if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN)) 3003 return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_UNKNOWN); 3004 else 3005 return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_STALE_DATA); 3006 } 3007 3008 ssize_t cpu_show_retbleed(struct device *dev, struct device_attribute *attr, char *buf) 3009 { 3010 return cpu_show_common(dev, attr, buf, X86_BUG_RETBLEED); 3011 } 3012 3013 ssize_t cpu_show_spec_rstack_overflow(struct device *dev, struct device_attribute *attr, char *buf) 3014 { 3015 return cpu_show_common(dev, attr, buf, X86_BUG_SRSO); 3016 } 3017 3018 ssize_t cpu_show_gds(struct device *dev, struct device_attribute *attr, char *buf) 3019 { 3020 return cpu_show_common(dev, attr, buf, X86_BUG_GDS); 3021 } 3022 3023 ssize_t cpu_show_reg_file_data_sampling(struct device *dev, struct device_attribute *attr, char *buf) 3024 { 3025 return cpu_show_common(dev, attr, buf, X86_BUG_RFDS); 3026 } 3027 #endif 3028 3029 void __warn_thunk(void) 3030 { 3031 WARN_ONCE(1, "Unpatched return thunk in use. This should not happen!\n"); 3032 } 3033