1 #include <linux/init.h> 2 #include <linux/bitops.h> 3 #include <linux/mm.h> 4 5 #include <asm/io.h> 6 #include <asm/processor.h> 7 #include <asm/apic.h> 8 9 #ifdef CONFIG_X86_64 10 # include <asm/numa_64.h> 11 # include <asm/mmconfig.h> 12 # include <asm/cacheflush.h> 13 #endif 14 15 #include "cpu.h" 16 17 #ifdef CONFIG_X86_32 18 /* 19 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 20 * misexecution of code under Linux. Owners of such processors should 21 * contact AMD for precise details and a CPU swap. 22 * 23 * See http://www.multimania.com/poulot/k6bug.html 24 * http://www.amd.com/K6/k6docs/revgd.html 25 * 26 * The following test is erm.. interesting. AMD neglected to up 27 * the chip setting when fixing the bug but they also tweaked some 28 * performance at the same time.. 29 */ 30 31 extern void vide(void); 32 __asm__(".align 4\nvide: ret"); 33 34 static void __cpuinit init_amd_k5(struct cpuinfo_x86 *c) 35 { 36 /* 37 * General Systems BIOSen alias the cpu frequency registers 38 * of the Elan at 0x000df000. Unfortuantly, one of the Linux 39 * drivers subsequently pokes it, and changes the CPU speed. 40 * Workaround : Remove the unneeded alias. 41 */ 42 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 43 #define CBAR_ENB (0x80000000) 44 #define CBAR_KEY (0X000000CB) 45 if (c->x86_model == 9 || c->x86_model == 10) { 46 if (inl (CBAR) & CBAR_ENB) 47 outl (0 | CBAR_KEY, CBAR); 48 } 49 } 50 51 52 static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c) 53 { 54 u32 l, h; 55 int mbytes = num_physpages >> (20-PAGE_SHIFT); 56 57 if (c->x86_model < 6) { 58 /* Based on AMD doc 20734R - June 2000 */ 59 if (c->x86_model == 0) { 60 clear_cpu_cap(c, X86_FEATURE_APIC); 61 set_cpu_cap(c, X86_FEATURE_PGE); 62 } 63 return; 64 } 65 66 if (c->x86_model == 6 && c->x86_mask == 1) { 67 const int K6_BUG_LOOP = 1000000; 68 int n; 69 void (*f_vide)(void); 70 unsigned long d, d2; 71 72 printk(KERN_INFO "AMD K6 stepping B detected - "); 73 74 /* 75 * It looks like AMD fixed the 2.6.2 bug and improved indirect 76 * calls at the same time. 77 */ 78 79 n = K6_BUG_LOOP; 80 f_vide = vide; 81 rdtscl(d); 82 while (n--) 83 f_vide(); 84 rdtscl(d2); 85 d = d2-d; 86 87 if (d > 20*K6_BUG_LOOP) 88 printk("system stability may be impaired when more than 32 MB are used.\n"); 89 else 90 printk("probably OK (after B9730xxxx).\n"); 91 printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n"); 92 } 93 94 /* K6 with old style WHCR */ 95 if (c->x86_model < 8 || 96 (c->x86_model == 8 && c->x86_mask < 8)) { 97 /* We can only write allocate on the low 508Mb */ 98 if (mbytes > 508) 99 mbytes = 508; 100 101 rdmsr(MSR_K6_WHCR, l, h); 102 if ((l&0x0000FFFF) == 0) { 103 unsigned long flags; 104 l = (1<<0)|((mbytes/4)<<1); 105 local_irq_save(flags); 106 wbinvd(); 107 wrmsr(MSR_K6_WHCR, l, h); 108 local_irq_restore(flags); 109 printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n", 110 mbytes); 111 } 112 return; 113 } 114 115 if ((c->x86_model == 8 && c->x86_mask > 7) || 116 c->x86_model == 9 || c->x86_model == 13) { 117 /* The more serious chips .. */ 118 119 if (mbytes > 4092) 120 mbytes = 4092; 121 122 rdmsr(MSR_K6_WHCR, l, h); 123 if ((l&0xFFFF0000) == 0) { 124 unsigned long flags; 125 l = ((mbytes>>2)<<22)|(1<<16); 126 local_irq_save(flags); 127 wbinvd(); 128 wrmsr(MSR_K6_WHCR, l, h); 129 local_irq_restore(flags); 130 printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n", 131 mbytes); 132 } 133 134 return; 135 } 136 137 if (c->x86_model == 10) { 138 /* AMD Geode LX is model 10 */ 139 /* placeholder for any needed mods */ 140 return; 141 } 142 } 143 144 static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c) 145 { 146 u32 l, h; 147 148 /* 149 * Bit 15 of Athlon specific MSR 15, needs to be 0 150 * to enable SSE on Palomino/Morgan/Barton CPU's. 151 * If the BIOS didn't enable it already, enable it here. 152 */ 153 if (c->x86_model >= 6 && c->x86_model <= 10) { 154 if (!cpu_has(c, X86_FEATURE_XMM)) { 155 printk(KERN_INFO "Enabling disabled K7/SSE Support.\n"); 156 rdmsr(MSR_K7_HWCR, l, h); 157 l &= ~0x00008000; 158 wrmsr(MSR_K7_HWCR, l, h); 159 set_cpu_cap(c, X86_FEATURE_XMM); 160 } 161 } 162 163 /* 164 * It's been determined by AMD that Athlons since model 8 stepping 1 165 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 166 * As per AMD technical note 27212 0.2 167 */ 168 if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) { 169 rdmsr(MSR_K7_CLK_CTL, l, h); 170 if ((l & 0xfff00000) != 0x20000000) { 171 printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l, 172 ((l & 0x000fffff)|0x20000000)); 173 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 174 } 175 } 176 177 set_cpu_cap(c, X86_FEATURE_K7); 178 } 179 #endif 180 181 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) 182 static int __cpuinit nearby_node(int apicid) 183 { 184 int i, node; 185 186 for (i = apicid - 1; i >= 0; i--) { 187 node = apicid_to_node[i]; 188 if (node != NUMA_NO_NODE && node_online(node)) 189 return node; 190 } 191 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 192 node = apicid_to_node[i]; 193 if (node != NUMA_NO_NODE && node_online(node)) 194 return node; 195 } 196 return first_node(node_online_map); /* Shouldn't happen */ 197 } 198 #endif 199 200 /* 201 * On a AMD dual core setup the lower bits of the APIC id distingush the cores. 202 * Assumes number of cores is a power of two. 203 */ 204 static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c) 205 { 206 #ifdef CONFIG_X86_HT 207 unsigned bits; 208 209 bits = c->x86_coreid_bits; 210 211 /* Low order bits define the core id (index of core in socket) */ 212 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); 213 /* Convert the initial APIC ID into the socket ID */ 214 c->phys_proc_id = c->initial_apicid >> bits; 215 #endif 216 } 217 218 static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c) 219 { 220 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) 221 int cpu = smp_processor_id(); 222 int node; 223 unsigned apicid = hard_smp_processor_id(); 224 225 node = c->phys_proc_id; 226 if (apicid_to_node[apicid] != NUMA_NO_NODE) 227 node = apicid_to_node[apicid]; 228 if (!node_online(node)) { 229 /* Two possibilities here: 230 - The CPU is missing memory and no node was created. 231 In that case try picking one from a nearby CPU 232 - The APIC IDs differ from the HyperTransport node IDs 233 which the K8 northbridge parsing fills in. 234 Assume they are all increased by a constant offset, 235 but in the same order as the HT nodeids. 236 If that doesn't result in a usable node fall back to the 237 path for the previous case. */ 238 239 int ht_nodeid = c->initial_apicid; 240 241 if (ht_nodeid >= 0 && 242 apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 243 node = apicid_to_node[ht_nodeid]; 244 /* Pick a nearby node */ 245 if (!node_online(node)) 246 node = nearby_node(apicid); 247 } 248 numa_set_node(cpu, node); 249 250 printk(KERN_INFO "CPU %d/0x%x -> Node %d\n", cpu, apicid, node); 251 #endif 252 } 253 254 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c) 255 { 256 #ifdef CONFIG_X86_HT 257 unsigned bits, ecx; 258 259 /* Multi core CPU? */ 260 if (c->extended_cpuid_level < 0x80000008) 261 return; 262 263 ecx = cpuid_ecx(0x80000008); 264 265 c->x86_max_cores = (ecx & 0xff) + 1; 266 267 /* CPU telling us the core id bits shift? */ 268 bits = (ecx >> 12) & 0xF; 269 270 /* Otherwise recompute */ 271 if (bits == 0) { 272 while ((1 << bits) < c->x86_max_cores) 273 bits++; 274 } 275 276 c->x86_coreid_bits = bits; 277 #endif 278 } 279 280 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c) 281 { 282 early_init_amd_mc(c); 283 284 /* 285 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 286 * with P/T states and does not stop in deep C-states 287 */ 288 if (c->x86_power & (1 << 8)) { 289 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 290 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 291 } 292 293 #ifdef CONFIG_X86_64 294 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 295 #else 296 /* Set MTRR capability flag if appropriate */ 297 if (c->x86 == 5) 298 if (c->x86_model == 13 || c->x86_model == 9 || 299 (c->x86_model == 8 && c->x86_mask >= 8)) 300 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 301 #endif 302 } 303 304 static void __cpuinit init_amd(struct cpuinfo_x86 *c) 305 { 306 #ifdef CONFIG_SMP 307 unsigned long long value; 308 309 /* 310 * Disable TLB flush filter by setting HWCR.FFDIS on K8 311 * bit 6 of msr C001_0015 312 * 313 * Errata 63 for SH-B3 steppings 314 * Errata 122 for all steppings (F+ have it disabled by default) 315 */ 316 if (c->x86 == 0xf) { 317 rdmsrl(MSR_K7_HWCR, value); 318 value |= 1 << 6; 319 wrmsrl(MSR_K7_HWCR, value); 320 } 321 #endif 322 323 early_init_amd(c); 324 325 /* 326 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 327 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 328 */ 329 clear_cpu_cap(c, 0*32+31); 330 331 #ifdef CONFIG_X86_64 332 /* On C+ stepping K8 rep microcode works well for copy/memset */ 333 if (c->x86 == 0xf) { 334 u32 level; 335 336 level = cpuid_eax(1); 337 if((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) 338 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 339 } 340 if (c->x86 == 0x10 || c->x86 == 0x11) 341 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 342 #else 343 344 /* 345 * FIXME: We should handle the K5 here. Set up the write 346 * range and also turn on MSR 83 bits 4 and 31 (write alloc, 347 * no bus pipeline) 348 */ 349 350 switch (c->x86) { 351 case 4: 352 init_amd_k5(c); 353 break; 354 case 5: 355 init_amd_k6(c); 356 break; 357 case 6: /* An Athlon/Duron */ 358 init_amd_k7(c); 359 break; 360 } 361 362 /* K6s reports MCEs but don't actually have all the MSRs */ 363 if (c->x86 < 6) 364 clear_cpu_cap(c, X86_FEATURE_MCE); 365 #endif 366 367 /* Enable workaround for FXSAVE leak */ 368 if (c->x86 >= 6) 369 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK); 370 371 if (!c->x86_model_id[0]) { 372 switch (c->x86) { 373 case 0xf: 374 /* Should distinguish Models here, but this is only 375 a fallback anyways. */ 376 strcpy(c->x86_model_id, "Hammer"); 377 break; 378 } 379 } 380 381 display_cacheinfo(c); 382 383 /* Multi core CPU? */ 384 if (c->extended_cpuid_level >= 0x80000008) { 385 amd_detect_cmp(c); 386 srat_detect_node(c); 387 } 388 389 #ifdef CONFIG_X86_32 390 detect_ht(c); 391 #endif 392 393 if (c->extended_cpuid_level >= 0x80000006) { 394 if ((c->x86 >= 0x0f) && (cpuid_edx(0x80000006) & 0xf000)) 395 num_cache_leaves = 4; 396 else 397 num_cache_leaves = 3; 398 } 399 400 if (c->x86 >= 0xf && c->x86 <= 0x11) 401 set_cpu_cap(c, X86_FEATURE_K8); 402 403 if (cpu_has_xmm2) { 404 /* MFENCE stops RDTSC speculation */ 405 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); 406 } 407 408 #ifdef CONFIG_X86_64 409 if (c->x86 == 0x10) { 410 /* do this for boot cpu */ 411 if (c == &boot_cpu_data) 412 check_enable_amd_mmconf_dmi(); 413 414 fam10h_check_enable_mmcfg(); 415 } 416 417 if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) { 418 unsigned long long tseg; 419 420 /* 421 * Split up direct mapping around the TSEG SMM area. 422 * Don't do it for gbpages because there seems very little 423 * benefit in doing so. 424 */ 425 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { 426 printk(KERN_DEBUG "tseg: %010llx\n", tseg); 427 if ((tseg>>PMD_SHIFT) < 428 (max_low_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) || 429 ((tseg>>PMD_SHIFT) < 430 (max_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) && 431 (tseg>>PMD_SHIFT) >= (1ULL<<(32 - PMD_SHIFT)))) 432 set_memory_4k((unsigned long)__va(tseg), 1); 433 } 434 } 435 #endif 436 } 437 438 #ifdef CONFIG_X86_32 439 static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) 440 { 441 /* AMD errata T13 (order #21922) */ 442 if ((c->x86 == 6)) { 443 if (c->x86_model == 3 && c->x86_mask == 0) /* Duron Rev A0 */ 444 size = 64; 445 if (c->x86_model == 4 && 446 (c->x86_mask == 0 || c->x86_mask == 1)) /* Tbird rev A1/A2 */ 447 size = 256; 448 } 449 return size; 450 } 451 #endif 452 453 static struct cpu_dev amd_cpu_dev __cpuinitdata = { 454 .c_vendor = "AMD", 455 .c_ident = { "AuthenticAMD" }, 456 #ifdef CONFIG_X86_32 457 .c_models = { 458 { .vendor = X86_VENDOR_AMD, .family = 4, .model_names = 459 { 460 [3] = "486 DX/2", 461 [7] = "486 DX/2-WB", 462 [8] = "486 DX/4", 463 [9] = "486 DX/4-WB", 464 [14] = "Am5x86-WT", 465 [15] = "Am5x86-WB" 466 } 467 }, 468 }, 469 .c_size_cache = amd_size_cache, 470 #endif 471 .c_early_init = early_init_amd, 472 .c_init = init_amd, 473 .c_x86_vendor = X86_VENDOR_AMD, 474 }; 475 476 cpu_dev_register(amd_cpu_dev); 477