1 // SPDX-License-Identifier: GPL-2.0-only 2 #include <linux/export.h> 3 #include <linux/bitops.h> 4 #include <linux/elf.h> 5 #include <linux/mm.h> 6 7 #include <linux/io.h> 8 #include <linux/sched.h> 9 #include <linux/sched/clock.h> 10 #include <linux/random.h> 11 #include <linux/topology.h> 12 #include <asm/amd/fch.h> 13 #include <asm/processor.h> 14 #include <asm/apic.h> 15 #include <asm/cacheinfo.h> 16 #include <asm/cpu.h> 17 #include <asm/cpu_device_id.h> 18 #include <asm/spec-ctrl.h> 19 #include <asm/smp.h> 20 #include <asm/numa.h> 21 #include <asm/pci-direct.h> 22 #include <asm/delay.h> 23 #include <asm/debugreg.h> 24 #include <asm/resctrl.h> 25 #include <asm/msr.h> 26 #include <asm/sev.h> 27 28 #ifdef CONFIG_X86_64 29 # include <asm/mmconfig.h> 30 #endif 31 32 #include "cpu.h" 33 34 u16 invlpgb_count_max __ro_after_init; 35 36 static inline int rdmsrq_amd_safe(unsigned msr, u64 *p) 37 { 38 u32 gprs[8] = { 0 }; 39 int err; 40 41 WARN_ONCE((boot_cpu_data.x86 != 0xf), 42 "%s should only be used on K8!\n", __func__); 43 44 gprs[1] = msr; 45 gprs[7] = 0x9c5a203a; 46 47 err = rdmsr_safe_regs(gprs); 48 49 *p = gprs[0] | ((u64)gprs[2] << 32); 50 51 return err; 52 } 53 54 static inline int wrmsrq_amd_safe(unsigned msr, u64 val) 55 { 56 u32 gprs[8] = { 0 }; 57 58 WARN_ONCE((boot_cpu_data.x86 != 0xf), 59 "%s should only be used on K8!\n", __func__); 60 61 gprs[0] = (u32)val; 62 gprs[1] = msr; 63 gprs[2] = val >> 32; 64 gprs[7] = 0x9c5a203a; 65 66 return wrmsr_safe_regs(gprs); 67 } 68 69 /* 70 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 71 * misexecution of code under Linux. Owners of such processors should 72 * contact AMD for precise details and a CPU swap. 73 * 74 * See http://www.multimania.com/poulot/k6bug.html 75 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" 76 * (Publication # 21266 Issue Date: August 1998) 77 * 78 * The following test is erm.. interesting. AMD neglected to up 79 * the chip setting when fixing the bug but they also tweaked some 80 * performance at the same time.. 81 */ 82 83 #ifdef CONFIG_X86_32 84 extern __visible void vide(void); 85 __asm__(".text\n" 86 ".globl vide\n" 87 ".type vide, @function\n" 88 ".align 4\n" 89 "vide: ret\n"); 90 #endif 91 92 static void init_amd_k5(struct cpuinfo_x86 *c) 93 { 94 #ifdef CONFIG_X86_32 95 /* 96 * General Systems BIOSen alias the cpu frequency registers 97 * of the Elan at 0x000df000. Unfortunately, one of the Linux 98 * drivers subsequently pokes it, and changes the CPU speed. 99 * Workaround : Remove the unneeded alias. 100 */ 101 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 102 #define CBAR_ENB (0x80000000) 103 #define CBAR_KEY (0X000000CB) 104 if (c->x86_model == 9 || c->x86_model == 10) { 105 if (inl(CBAR) & CBAR_ENB) 106 outl(0 | CBAR_KEY, CBAR); 107 } 108 #endif 109 } 110 111 static void init_amd_k6(struct cpuinfo_x86 *c) 112 { 113 #ifdef CONFIG_X86_32 114 u32 l, h; 115 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); 116 117 if (c->x86_model < 6) { 118 /* Based on AMD doc 20734R - June 2000 */ 119 if (c->x86_model == 0) { 120 clear_cpu_cap(c, X86_FEATURE_APIC); 121 set_cpu_cap(c, X86_FEATURE_PGE); 122 } 123 return; 124 } 125 126 if (c->x86_model == 6 && c->x86_stepping == 1) { 127 const int K6_BUG_LOOP = 1000000; 128 int n; 129 void (*f_vide)(void); 130 u64 d, d2; 131 132 pr_info("AMD K6 stepping B detected - "); 133 134 /* 135 * It looks like AMD fixed the 2.6.2 bug and improved indirect 136 * calls at the same time. 137 */ 138 139 n = K6_BUG_LOOP; 140 f_vide = vide; 141 OPTIMIZER_HIDE_VAR(f_vide); 142 d = rdtsc(); 143 while (n--) 144 f_vide(); 145 d2 = rdtsc(); 146 d = d2-d; 147 148 if (d > 20*K6_BUG_LOOP) 149 pr_cont("system stability may be impaired when more than 32 MB are used.\n"); 150 else 151 pr_cont("probably OK (after B9730xxxx).\n"); 152 } 153 154 /* K6 with old style WHCR */ 155 if (c->x86_model < 8 || 156 (c->x86_model == 8 && c->x86_stepping < 8)) { 157 /* We can only write allocate on the low 508Mb */ 158 if (mbytes > 508) 159 mbytes = 508; 160 161 rdmsr(MSR_K6_WHCR, l, h); 162 if ((l&0x0000FFFF) == 0) { 163 unsigned long flags; 164 l = (1<<0)|((mbytes/4)<<1); 165 local_irq_save(flags); 166 wbinvd(); 167 wrmsr(MSR_K6_WHCR, l, h); 168 local_irq_restore(flags); 169 pr_info("Enabling old style K6 write allocation for %d Mb\n", 170 mbytes); 171 } 172 return; 173 } 174 175 if ((c->x86_model == 8 && c->x86_stepping > 7) || 176 c->x86_model == 9 || c->x86_model == 13) { 177 /* The more serious chips .. */ 178 179 if (mbytes > 4092) 180 mbytes = 4092; 181 182 rdmsr(MSR_K6_WHCR, l, h); 183 if ((l&0xFFFF0000) == 0) { 184 unsigned long flags; 185 l = ((mbytes>>2)<<22)|(1<<16); 186 local_irq_save(flags); 187 wbinvd(); 188 wrmsr(MSR_K6_WHCR, l, h); 189 local_irq_restore(flags); 190 pr_info("Enabling new style K6 write allocation for %d Mb\n", 191 mbytes); 192 } 193 194 return; 195 } 196 197 if (c->x86_model == 10) { 198 /* AMD Geode LX is model 10 */ 199 /* placeholder for any needed mods */ 200 return; 201 } 202 #endif 203 } 204 205 static void init_amd_k7(struct cpuinfo_x86 *c) 206 { 207 #ifdef CONFIG_X86_32 208 u32 l, h; 209 210 /* 211 * Bit 15 of Athlon specific MSR 15, needs to be 0 212 * to enable SSE on Palomino/Morgan/Barton CPU's. 213 * If the BIOS didn't enable it already, enable it here. 214 */ 215 if (c->x86_model >= 6 && c->x86_model <= 10) { 216 if (!cpu_has(c, X86_FEATURE_XMM)) { 217 pr_info("Enabling disabled K7/SSE Support.\n"); 218 msr_clear_bit(MSR_K7_HWCR, 15); 219 set_cpu_cap(c, X86_FEATURE_XMM); 220 } 221 } 222 223 /* 224 * It's been determined by AMD that Athlons since model 8 stepping 1 225 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 226 * As per AMD technical note 27212 0.2 227 */ 228 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) { 229 rdmsr(MSR_K7_CLK_CTL, l, h); 230 if ((l & 0xfff00000) != 0x20000000) { 231 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", 232 l, ((l & 0x000fffff)|0x20000000)); 233 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 234 } 235 } 236 237 /* calling is from identify_secondary_cpu() ? */ 238 if (!c->cpu_index) 239 return; 240 241 /* 242 * Certain Athlons might work (for various values of 'work') in SMP 243 * but they are not certified as MP capable. 244 */ 245 /* Athlon 660/661 is valid. */ 246 if ((c->x86_model == 6) && ((c->x86_stepping == 0) || 247 (c->x86_stepping == 1))) 248 return; 249 250 /* Duron 670 is valid */ 251 if ((c->x86_model == 7) && (c->x86_stepping == 0)) 252 return; 253 254 /* 255 * Athlon 662, Duron 671, and Athlon >model 7 have capability 256 * bit. It's worth noting that the A5 stepping (662) of some 257 * Athlon XP's have the MP bit set. 258 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for 259 * more. 260 */ 261 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) || 262 ((c->x86_model == 7) && (c->x86_stepping >= 1)) || 263 (c->x86_model > 7)) 264 if (cpu_has(c, X86_FEATURE_MP)) 265 return; 266 267 /* If we get here, not a certified SMP capable AMD system. */ 268 269 /* 270 * Don't taint if we are running SMP kernel on a single non-MP 271 * approved Athlon 272 */ 273 WARN_ONCE(1, "WARNING: This combination of AMD" 274 " processors is not suitable for SMP.\n"); 275 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 276 #endif 277 } 278 279 #ifdef CONFIG_NUMA 280 /* 281 * To workaround broken NUMA config. Read the comment in 282 * srat_detect_node(). 283 */ 284 static int nearby_node(int apicid) 285 { 286 int i, node; 287 288 for (i = apicid - 1; i >= 0; i--) { 289 node = __apicid_to_node[i]; 290 if (node != NUMA_NO_NODE && node_online(node)) 291 return node; 292 } 293 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 294 node = __apicid_to_node[i]; 295 if (node != NUMA_NO_NODE && node_online(node)) 296 return node; 297 } 298 return first_node(node_online_map); /* Shouldn't happen */ 299 } 300 #endif 301 302 static void srat_detect_node(struct cpuinfo_x86 *c) 303 { 304 #ifdef CONFIG_NUMA 305 int cpu = smp_processor_id(); 306 int node; 307 unsigned apicid = c->topo.apicid; 308 309 node = numa_cpu_node(cpu); 310 if (node == NUMA_NO_NODE) 311 node = per_cpu_llc_id(cpu); 312 313 /* 314 * On multi-fabric platform (e.g. Numascale NumaChip) a 315 * platform-specific handler needs to be called to fixup some 316 * IDs of the CPU. 317 */ 318 if (x86_cpuinit.fixup_cpu_id) 319 x86_cpuinit.fixup_cpu_id(c, node); 320 321 if (!node_online(node)) { 322 /* 323 * Two possibilities here: 324 * 325 * - The CPU is missing memory and no node was created. In 326 * that case try picking one from a nearby CPU. 327 * 328 * - The APIC IDs differ from the HyperTransport node IDs 329 * which the K8 northbridge parsing fills in. Assume 330 * they are all increased by a constant offset, but in 331 * the same order as the HT nodeids. If that doesn't 332 * result in a usable node fall back to the path for the 333 * previous case. 334 * 335 * This workaround operates directly on the mapping between 336 * APIC ID and NUMA node, assuming certain relationship 337 * between APIC ID, HT node ID and NUMA topology. As going 338 * through CPU mapping may alter the outcome, directly 339 * access __apicid_to_node[]. 340 */ 341 int ht_nodeid = c->topo.initial_apicid; 342 343 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 344 node = __apicid_to_node[ht_nodeid]; 345 /* Pick a nearby node */ 346 if (!node_online(node)) 347 node = nearby_node(apicid); 348 } 349 numa_set_node(cpu, node); 350 #endif 351 } 352 353 static void bsp_determine_snp(struct cpuinfo_x86 *c) 354 { 355 #ifdef CONFIG_ARCH_HAS_CC_PLATFORM 356 cc_vendor = CC_VENDOR_AMD; 357 358 if (cpu_has(c, X86_FEATURE_SEV_SNP)) { 359 /* 360 * RMP table entry format is not architectural and is defined by the 361 * per-processor PPR. Restrict SNP support on the known CPU models 362 * for which the RMP table entry format is currently defined or for 363 * processors which support the architecturally defined RMPREAD 364 * instruction. 365 */ 366 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && 367 (cpu_feature_enabled(X86_FEATURE_ZEN3) || 368 cpu_feature_enabled(X86_FEATURE_ZEN4) || 369 cpu_feature_enabled(X86_FEATURE_RMPREAD)) && 370 snp_probe_rmptable_info()) { 371 cc_platform_set(CC_ATTR_HOST_SEV_SNP); 372 } else { 373 setup_clear_cpu_cap(X86_FEATURE_SEV_SNP); 374 cc_platform_clear(CC_ATTR_HOST_SEV_SNP); 375 } 376 } 377 #endif 378 } 379 380 static void bsp_init_amd(struct cpuinfo_x86 *c) 381 { 382 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 383 384 if (c->x86 > 0x10 || 385 (c->x86 == 0x10 && c->x86_model >= 0x2)) { 386 u64 val; 387 388 rdmsrq(MSR_K7_HWCR, val); 389 if (!(val & BIT(24))) 390 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); 391 } 392 } 393 394 if (c->x86 == 0x15) { 395 unsigned long upperbit; 396 u32 cpuid, assoc; 397 398 cpuid = cpuid_edx(0x80000005); 399 assoc = cpuid >> 16 & 0xff; 400 upperbit = ((cpuid >> 24) << 10) / assoc; 401 402 va_align.mask = (upperbit - 1) & PAGE_MASK; 403 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; 404 405 /* A random value per boot for bit slice [12:upper_bit) */ 406 va_align.bits = get_random_u32() & va_align.mask; 407 } 408 409 if (cpu_has(c, X86_FEATURE_MWAITX)) 410 use_mwaitx_delay(); 411 412 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) && 413 !boot_cpu_has(X86_FEATURE_VIRT_SSBD) && 414 c->x86 >= 0x15 && c->x86 <= 0x17) { 415 unsigned int bit; 416 417 switch (c->x86) { 418 case 0x15: bit = 54; break; 419 case 0x16: bit = 33; break; 420 case 0x17: bit = 10; break; 421 default: return; 422 } 423 /* 424 * Try to cache the base value so further operations can 425 * avoid RMW. If that faults, do not enable SSBD. 426 */ 427 if (!rdmsrq_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) { 428 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD); 429 setup_force_cpu_cap(X86_FEATURE_SSBD); 430 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit; 431 } 432 } 433 434 resctrl_cpu_detect(c); 435 436 /* Figure out Zen generations: */ 437 switch (c->x86) { 438 case 0x17: 439 switch (c->x86_model) { 440 case 0x00 ... 0x2f: 441 case 0x50 ... 0x5f: 442 setup_force_cpu_cap(X86_FEATURE_ZEN1); 443 break; 444 case 0x30 ... 0x4f: 445 case 0x60 ... 0x7f: 446 case 0x90 ... 0x91: 447 case 0xa0 ... 0xaf: 448 setup_force_cpu_cap(X86_FEATURE_ZEN2); 449 break; 450 default: 451 goto warn; 452 } 453 break; 454 455 case 0x19: 456 switch (c->x86_model) { 457 case 0x00 ... 0x0f: 458 case 0x20 ... 0x5f: 459 setup_force_cpu_cap(X86_FEATURE_ZEN3); 460 break; 461 case 0x10 ... 0x1f: 462 case 0x60 ... 0xaf: 463 setup_force_cpu_cap(X86_FEATURE_ZEN4); 464 break; 465 default: 466 goto warn; 467 } 468 break; 469 470 case 0x1a: 471 switch (c->x86_model) { 472 case 0x00 ... 0x2f: 473 case 0x40 ... 0x4f: 474 case 0x60 ... 0x7f: 475 setup_force_cpu_cap(X86_FEATURE_ZEN5); 476 break; 477 default: 478 goto warn; 479 } 480 break; 481 482 default: 483 break; 484 } 485 486 bsp_determine_snp(c); 487 return; 488 489 warn: 490 WARN_ONCE(1, "Family 0x%x, model: 0x%x??\n", c->x86, c->x86_model); 491 } 492 493 static void early_detect_mem_encrypt(struct cpuinfo_x86 *c) 494 { 495 u64 msr; 496 497 /* 498 * BIOS support is required for SME and SEV. 499 * For SME: If BIOS has enabled SME then adjust x86_phys_bits by 500 * the SME physical address space reduction value. 501 * If BIOS has not enabled SME then don't advertise the 502 * SME feature (set in scattered.c). 503 * If the kernel has not enabled SME via any means then 504 * don't advertise the SME feature. 505 * For SEV: If BIOS has not enabled SEV then don't advertise SEV and 506 * any additional functionality based on it. 507 * 508 * In all cases, since support for SME and SEV requires long mode, 509 * don't advertise the feature under CONFIG_X86_32. 510 */ 511 if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) { 512 /* Check if memory encryption is enabled */ 513 rdmsrq(MSR_AMD64_SYSCFG, msr); 514 if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT)) 515 goto clear_all; 516 517 /* 518 * Always adjust physical address bits. Even though this 519 * will be a value above 32-bits this is still done for 520 * CONFIG_X86_32 so that accurate values are reported. 521 */ 522 c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f; 523 524 if (IS_ENABLED(CONFIG_X86_32)) 525 goto clear_all; 526 527 if (!sme_me_mask) 528 setup_clear_cpu_cap(X86_FEATURE_SME); 529 530 rdmsrq(MSR_K7_HWCR, msr); 531 if (!(msr & MSR_K7_HWCR_SMMLOCK)) 532 goto clear_sev; 533 534 return; 535 536 clear_all: 537 setup_clear_cpu_cap(X86_FEATURE_SME); 538 clear_sev: 539 setup_clear_cpu_cap(X86_FEATURE_SEV); 540 setup_clear_cpu_cap(X86_FEATURE_SEV_ES); 541 setup_clear_cpu_cap(X86_FEATURE_SEV_SNP); 542 } 543 } 544 545 static void early_init_amd(struct cpuinfo_x86 *c) 546 { 547 u32 dummy; 548 549 if (c->x86 >= 0xf) 550 set_cpu_cap(c, X86_FEATURE_K8); 551 552 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); 553 554 /* 555 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 556 * with P/T states and does not stop in deep C-states 557 */ 558 if (c->x86_power & (1 << 8)) { 559 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 560 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 561 } 562 563 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ 564 if (c->x86_power & BIT(12)) 565 set_cpu_cap(c, X86_FEATURE_ACC_POWER); 566 567 /* Bit 14 indicates the Runtime Average Power Limit interface. */ 568 if (c->x86_power & BIT(14)) 569 set_cpu_cap(c, X86_FEATURE_RAPL); 570 571 #ifdef CONFIG_X86_64 572 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 573 #else 574 /* Set MTRR capability flag if appropriate */ 575 if (c->x86 == 5) 576 if (c->x86_model == 13 || c->x86_model == 9 || 577 (c->x86_model == 8 && c->x86_stepping >= 8)) 578 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 579 #endif 580 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 581 /* 582 * ApicID can always be treated as an 8-bit value for AMD APIC versions 583 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we 584 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families 585 * after 16h. 586 */ 587 if (boot_cpu_has(X86_FEATURE_APIC)) { 588 if (c->x86 > 0x16) 589 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 590 else if (c->x86 >= 0xf) { 591 /* check CPU config space for extended APIC ID */ 592 unsigned int val; 593 594 val = read_pci_config(0, 24, 0, 0x68); 595 if ((val >> 17 & 0x3) == 0x3) 596 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 597 } 598 } 599 #endif 600 601 /* 602 * This is only needed to tell the kernel whether to use VMCALL 603 * and VMMCALL. VMMCALL is never executed except under virt, so 604 * we can set it unconditionally. 605 */ 606 set_cpu_cap(c, X86_FEATURE_VMMCALL); 607 608 /* F16h erratum 793, CVE-2013-6885 */ 609 if (c->x86 == 0x16 && c->x86_model <= 0xf) 610 msr_set_bit(MSR_AMD64_LS_CFG, 15); 611 612 early_detect_mem_encrypt(c); 613 614 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && !cpu_has(c, X86_FEATURE_IBPB_BRTYPE)) { 615 if (c->x86 == 0x17 && boot_cpu_has(X86_FEATURE_AMD_IBPB)) 616 setup_force_cpu_cap(X86_FEATURE_IBPB_BRTYPE); 617 else if (c->x86 >= 0x19 && !wrmsrq_safe(MSR_IA32_PRED_CMD, PRED_CMD_SBPB)) { 618 setup_force_cpu_cap(X86_FEATURE_IBPB_BRTYPE); 619 setup_force_cpu_cap(X86_FEATURE_SBPB); 620 } 621 } 622 } 623 624 static void init_amd_k8(struct cpuinfo_x86 *c) 625 { 626 u32 level; 627 u64 value; 628 629 /* On C+ stepping K8 rep microcode works well for copy/memset */ 630 level = cpuid_eax(1); 631 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) 632 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 633 634 /* 635 * Some BIOSes incorrectly force this feature, but only K8 revision D 636 * (model = 0x14) and later actually support it. 637 * (AMD Erratum #110, docId: 25759). 638 */ 639 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM) && !cpu_has(c, X86_FEATURE_HYPERVISOR)) { 640 clear_cpu_cap(c, X86_FEATURE_LAHF_LM); 641 if (!rdmsrq_amd_safe(0xc001100d, &value)) { 642 value &= ~BIT_64(32); 643 wrmsrq_amd_safe(0xc001100d, value); 644 } 645 } 646 647 if (!c->x86_model_id[0]) 648 strcpy(c->x86_model_id, "Hammer"); 649 650 #ifdef CONFIG_SMP 651 /* 652 * Disable TLB flush filter by setting HWCR.FFDIS on K8 653 * bit 6 of msr C001_0015 654 * 655 * Errata 63 for SH-B3 steppings 656 * Errata 122 for all steppings (F+ have it disabled by default) 657 */ 658 msr_set_bit(MSR_K7_HWCR, 6); 659 #endif 660 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE); 661 662 /* 663 * Check models and steppings affected by erratum 400. This is 664 * used to select the proper idle routine and to enable the 665 * check whether the machine is affected in arch_post_acpi_subsys_init() 666 * which sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check. 667 */ 668 if (c->x86_model > 0x41 || 669 (c->x86_model == 0x41 && c->x86_stepping >= 0x2)) 670 setup_force_cpu_bug(X86_BUG_AMD_E400); 671 } 672 673 static void init_amd_gh(struct cpuinfo_x86 *c) 674 { 675 #ifdef CONFIG_MMCONF_FAM10H 676 /* do this for boot cpu */ 677 if (c == &boot_cpu_data) 678 check_enable_amd_mmconf_dmi(); 679 680 fam10h_check_enable_mmcfg(); 681 #endif 682 683 /* 684 * Disable GART TLB Walk Errors on Fam10h. We do this here because this 685 * is always needed when GART is enabled, even in a kernel which has no 686 * MCE support built in. BIOS should disable GartTlbWlk Errors already. 687 * If it doesn't, we do it here as suggested by the BKDG. 688 * 689 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 690 */ 691 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10); 692 693 /* 694 * On family 10h BIOS may not have properly enabled WC+ support, causing 695 * it to be converted to CD memtype. This may result in performance 696 * degradation for certain nested-paging guests. Prevent this conversion 697 * by clearing bit 24 in MSR_AMD64_BU_CFG2. 698 * 699 * NOTE: we want to use the _safe accessors so as not to #GP kvm 700 * guests on older kvm hosts. 701 */ 702 msr_clear_bit(MSR_AMD64_BU_CFG2, 24); 703 704 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH); 705 706 /* 707 * Check models and steppings affected by erratum 400. This is 708 * used to select the proper idle routine and to enable the 709 * check whether the machine is affected in arch_post_acpi_subsys_init() 710 * which sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check. 711 */ 712 if (c->x86_model > 0x2 || 713 (c->x86_model == 0x2 && c->x86_stepping >= 0x1)) 714 setup_force_cpu_bug(X86_BUG_AMD_E400); 715 } 716 717 static void init_amd_ln(struct cpuinfo_x86 *c) 718 { 719 /* 720 * Apply erratum 665 fix unconditionally so machines without a BIOS 721 * fix work. 722 */ 723 msr_set_bit(MSR_AMD64_DE_CFG, 31); 724 } 725 726 static bool rdrand_force; 727 728 static int __init rdrand_cmdline(char *str) 729 { 730 if (!str) 731 return -EINVAL; 732 733 if (!strcmp(str, "force")) 734 rdrand_force = true; 735 else 736 return -EINVAL; 737 738 return 0; 739 } 740 early_param("rdrand", rdrand_cmdline); 741 742 static void clear_rdrand_cpuid_bit(struct cpuinfo_x86 *c) 743 { 744 /* 745 * Saving of the MSR used to hide the RDRAND support during 746 * suspend/resume is done by arch/x86/power/cpu.c, which is 747 * dependent on CONFIG_PM_SLEEP. 748 */ 749 if (!IS_ENABLED(CONFIG_PM_SLEEP)) 750 return; 751 752 /* 753 * The self-test can clear X86_FEATURE_RDRAND, so check for 754 * RDRAND support using the CPUID function directly. 755 */ 756 if (!(cpuid_ecx(1) & BIT(30)) || rdrand_force) 757 return; 758 759 msr_clear_bit(MSR_AMD64_CPUID_FN_1, 62); 760 761 /* 762 * Verify that the CPUID change has occurred in case the kernel is 763 * running virtualized and the hypervisor doesn't support the MSR. 764 */ 765 if (cpuid_ecx(1) & BIT(30)) { 766 pr_info_once("BIOS may not properly restore RDRAND after suspend, but hypervisor does not support hiding RDRAND via CPUID.\n"); 767 return; 768 } 769 770 clear_cpu_cap(c, X86_FEATURE_RDRAND); 771 pr_info_once("BIOS may not properly restore RDRAND after suspend, hiding RDRAND via CPUID. Use rdrand=force to reenable.\n"); 772 } 773 774 static void init_amd_jg(struct cpuinfo_x86 *c) 775 { 776 /* 777 * Some BIOS implementations do not restore proper RDRAND support 778 * across suspend and resume. Check on whether to hide the RDRAND 779 * instruction support via CPUID. 780 */ 781 clear_rdrand_cpuid_bit(c); 782 } 783 784 static void init_amd_bd(struct cpuinfo_x86 *c) 785 { 786 u64 value; 787 788 /* 789 * The way access filter has a performance penalty on some workloads. 790 * Disable it on the affected CPUs. 791 */ 792 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) { 793 if (!rdmsrq_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) { 794 value |= 0x1E; 795 wrmsrq_safe(MSR_F15H_IC_CFG, value); 796 } 797 } 798 799 /* 800 * Some BIOS implementations do not restore proper RDRAND support 801 * across suspend and resume. Check on whether to hide the RDRAND 802 * instruction support via CPUID. 803 */ 804 clear_rdrand_cpuid_bit(c); 805 } 806 807 static const struct x86_cpu_id erratum_1386_microcode[] = { 808 X86_MATCH_VFM_STEPS(VFM_MAKE(X86_VENDOR_AMD, 0x17, 0x01), 0x2, 0x2, 0x0800126e), 809 X86_MATCH_VFM_STEPS(VFM_MAKE(X86_VENDOR_AMD, 0x17, 0x31), 0x0, 0x0, 0x08301052), 810 {} 811 }; 812 813 static void fix_erratum_1386(struct cpuinfo_x86 *c) 814 { 815 /* 816 * Work around Erratum 1386. The XSAVES instruction malfunctions in 817 * certain circumstances on Zen1/2 uarch, and not all parts have had 818 * updated microcode at the time of writing (March 2023). 819 * 820 * Affected parts all have no supervisor XSAVE states, meaning that 821 * the XSAVEC instruction (which works fine) is equivalent. 822 * 823 * Clear the feature flag only on microcode revisions which 824 * don't have the fix. 825 */ 826 if (x86_match_min_microcode_rev(erratum_1386_microcode)) 827 return; 828 829 clear_cpu_cap(c, X86_FEATURE_XSAVES); 830 } 831 832 void init_spectral_chicken(struct cpuinfo_x86 *c) 833 { 834 #ifdef CONFIG_MITIGATION_UNRET_ENTRY 835 u64 value; 836 837 /* 838 * On Zen2 we offer this chicken (bit) on the altar of Speculation. 839 * 840 * This suppresses speculation from the middle of a basic block, i.e. it 841 * suppresses non-branch predictions. 842 */ 843 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) { 844 if (!rdmsrq_safe(MSR_ZEN2_SPECTRAL_CHICKEN, &value)) { 845 value |= MSR_ZEN2_SPECTRAL_CHICKEN_BIT; 846 wrmsrq_safe(MSR_ZEN2_SPECTRAL_CHICKEN, value); 847 } 848 } 849 #endif 850 } 851 852 static void init_amd_zen_common(void) 853 { 854 setup_force_cpu_cap(X86_FEATURE_ZEN); 855 #ifdef CONFIG_NUMA 856 node_reclaim_distance = 32; 857 #endif 858 } 859 860 static void init_amd_zen1(struct cpuinfo_x86 *c) 861 { 862 fix_erratum_1386(c); 863 864 /* Fix up CPUID bits, but only if not virtualised. */ 865 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) { 866 867 /* Erratum 1076: CPB feature bit not being set in CPUID. */ 868 if (!cpu_has(c, X86_FEATURE_CPB)) 869 set_cpu_cap(c, X86_FEATURE_CPB); 870 } 871 872 pr_notice_once("AMD Zen1 DIV0 bug detected. Disable SMT for full protection.\n"); 873 setup_force_cpu_bug(X86_BUG_DIV0); 874 875 /* 876 * Turn off the Instructions Retired free counter on machines that are 877 * susceptible to erratum #1054 "Instructions Retired Performance 878 * Counter May Be Inaccurate". 879 */ 880 if (c->x86_model < 0x30) { 881 msr_clear_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT); 882 clear_cpu_cap(c, X86_FEATURE_IRPERF); 883 } 884 } 885 886 static bool cpu_has_zenbleed_microcode(void) 887 { 888 u32 good_rev = 0; 889 890 switch (boot_cpu_data.x86_model) { 891 case 0x30 ... 0x3f: good_rev = 0x0830107b; break; 892 case 0x60 ... 0x67: good_rev = 0x0860010c; break; 893 case 0x68 ... 0x6f: good_rev = 0x08608107; break; 894 case 0x70 ... 0x7f: good_rev = 0x08701033; break; 895 case 0xa0 ... 0xaf: good_rev = 0x08a00009; break; 896 897 default: 898 return false; 899 } 900 901 if (boot_cpu_data.microcode < good_rev) 902 return false; 903 904 return true; 905 } 906 907 static void zen2_zenbleed_check(struct cpuinfo_x86 *c) 908 { 909 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) 910 return; 911 912 if (!cpu_has(c, X86_FEATURE_AVX)) 913 return; 914 915 if (!cpu_has_zenbleed_microcode()) { 916 pr_notice_once("Zenbleed: please update your microcode for the most optimal fix\n"); 917 msr_set_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT); 918 } else { 919 msr_clear_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT); 920 } 921 } 922 923 static void init_amd_zen2(struct cpuinfo_x86 *c) 924 { 925 init_spectral_chicken(c); 926 fix_erratum_1386(c); 927 zen2_zenbleed_check(c); 928 } 929 930 static void init_amd_zen3(struct cpuinfo_x86 *c) 931 { 932 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) { 933 /* 934 * Zen3 (Fam19 model < 0x10) parts are not susceptible to 935 * Branch Type Confusion, but predate the allocation of the 936 * BTC_NO bit. 937 */ 938 if (!cpu_has(c, X86_FEATURE_BTC_NO)) 939 set_cpu_cap(c, X86_FEATURE_BTC_NO); 940 } 941 } 942 943 static void init_amd_zen4(struct cpuinfo_x86 *c) 944 { 945 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) 946 msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT); 947 948 /* 949 * These Zen4 SoCs advertise support for virtualized VMLOAD/VMSAVE 950 * in some BIOS versions but they can lead to random host reboots. 951 */ 952 switch (c->x86_model) { 953 case 0x18 ... 0x1f: 954 case 0x60 ... 0x7f: 955 clear_cpu_cap(c, X86_FEATURE_V_VMSAVE_VMLOAD); 956 break; 957 } 958 } 959 960 static void init_amd_zen5(struct cpuinfo_x86 *c) 961 { 962 } 963 964 static void init_amd(struct cpuinfo_x86 *c) 965 { 966 u64 vm_cr; 967 968 early_init_amd(c); 969 970 /* 971 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 972 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 973 */ 974 clear_cpu_cap(c, 0*32+31); 975 976 if (c->x86 >= 0x10) 977 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 978 979 /* AMD FSRM also implies FSRS */ 980 if (cpu_has(c, X86_FEATURE_FSRM)) 981 set_cpu_cap(c, X86_FEATURE_FSRS); 982 983 /* K6s reports MCEs but don't actually have all the MSRs */ 984 if (c->x86 < 6) 985 clear_cpu_cap(c, X86_FEATURE_MCE); 986 987 switch (c->x86) { 988 case 4: init_amd_k5(c); break; 989 case 5: init_amd_k6(c); break; 990 case 6: init_amd_k7(c); break; 991 case 0xf: init_amd_k8(c); break; 992 case 0x10: init_amd_gh(c); break; 993 case 0x12: init_amd_ln(c); break; 994 case 0x15: init_amd_bd(c); break; 995 case 0x16: init_amd_jg(c); break; 996 } 997 998 /* 999 * Save up on some future enablement work and do common Zen 1000 * settings. 1001 */ 1002 if (c->x86 >= 0x17) 1003 init_amd_zen_common(); 1004 1005 if (boot_cpu_has(X86_FEATURE_ZEN1)) 1006 init_amd_zen1(c); 1007 else if (boot_cpu_has(X86_FEATURE_ZEN2)) 1008 init_amd_zen2(c); 1009 else if (boot_cpu_has(X86_FEATURE_ZEN3)) 1010 init_amd_zen3(c); 1011 else if (boot_cpu_has(X86_FEATURE_ZEN4)) 1012 init_amd_zen4(c); 1013 else if (boot_cpu_has(X86_FEATURE_ZEN5)) 1014 init_amd_zen5(c); 1015 1016 /* 1017 * Enable workaround for FXSAVE leak on CPUs 1018 * without a XSaveErPtr feature 1019 */ 1020 if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR))) 1021 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK); 1022 1023 cpu_detect_cache_sizes(c); 1024 1025 srat_detect_node(c); 1026 1027 init_amd_cacheinfo(c); 1028 1029 if (cpu_has(c, X86_FEATURE_SVM)) { 1030 rdmsrq(MSR_VM_CR, vm_cr); 1031 if (vm_cr & SVM_VM_CR_SVM_DIS_MASK) { 1032 pr_notice_once("SVM disabled (by BIOS) in MSR_VM_CR\n"); 1033 clear_cpu_cap(c, X86_FEATURE_SVM); 1034 } 1035 } 1036 1037 if (!cpu_has(c, X86_FEATURE_LFENCE_RDTSC) && cpu_has(c, X86_FEATURE_XMM2)) { 1038 /* 1039 * Use LFENCE for execution serialization. On families which 1040 * don't have that MSR, LFENCE is already serializing. 1041 * msr_set_bit() uses the safe accessors, too, even if the MSR 1042 * is not present. 1043 */ 1044 msr_set_bit(MSR_AMD64_DE_CFG, 1045 MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT); 1046 1047 /* A serializing LFENCE stops RDTSC speculation */ 1048 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 1049 } 1050 1051 /* 1052 * Family 0x12 and above processors have APIC timer 1053 * running in deep C states. 1054 */ 1055 if (c->x86 > 0x11) 1056 set_cpu_cap(c, X86_FEATURE_ARAT); 1057 1058 /* 3DNow or LM implies PREFETCHW */ 1059 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH)) 1060 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM)) 1061 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH); 1062 1063 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */ 1064 if (!cpu_feature_enabled(X86_FEATURE_XENPV)) 1065 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); 1066 1067 /* Enable the Instructions Retired free counter */ 1068 if (cpu_has(c, X86_FEATURE_IRPERF)) 1069 msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT); 1070 1071 check_null_seg_clears_base(c); 1072 1073 /* 1074 * Make sure EFER[AIBRSE - Automatic IBRS Enable] is set. The APs are brought up 1075 * using the trampoline code and as part of it, MSR_EFER gets prepared there in 1076 * order to be replicated onto them. Regardless, set it here again, if not set, 1077 * to protect against any future refactoring/code reorganization which might 1078 * miss setting this important bit. 1079 */ 1080 if (spectre_v2_in_eibrs_mode(spectre_v2_enabled) && 1081 cpu_has(c, X86_FEATURE_AUTOIBRS)) 1082 WARN_ON_ONCE(msr_set_bit(MSR_EFER, _EFER_AUTOIBRS) < 0); 1083 1084 /* AMD CPUs don't need fencing after x2APIC/TSC_DEADLINE MSR writes. */ 1085 clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE); 1086 1087 /* Enable Translation Cache Extension */ 1088 if (cpu_has(c, X86_FEATURE_TCE)) 1089 msr_set_bit(MSR_EFER, _EFER_TCE); 1090 } 1091 1092 #ifdef CONFIG_X86_32 1093 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) 1094 { 1095 /* AMD errata T13 (order #21922) */ 1096 if (c->x86 == 6) { 1097 /* Duron Rev A0 */ 1098 if (c->x86_model == 3 && c->x86_stepping == 0) 1099 size = 64; 1100 /* Tbird rev A1/A2 */ 1101 if (c->x86_model == 4 && 1102 (c->x86_stepping == 0 || c->x86_stepping == 1)) 1103 size = 256; 1104 } 1105 return size; 1106 } 1107 #endif 1108 1109 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) 1110 { 1111 u32 ebx, eax, ecx, edx; 1112 u16 mask = 0xfff; 1113 1114 if (c->x86 < 0xf) 1115 return; 1116 1117 if (c->extended_cpuid_level < 0x80000006) 1118 return; 1119 1120 cpuid(0x80000006, &eax, &ebx, &ecx, &edx); 1121 1122 tlb_lld_4k = (ebx >> 16) & mask; 1123 tlb_lli_4k = ebx & mask; 1124 1125 /* 1126 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB 1127 * characteristics from the CPUID function 0x80000005 instead. 1128 */ 1129 if (c->x86 == 0xf) { 1130 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 1131 mask = 0xff; 1132 } 1133 1134 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 1135 if (!((eax >> 16) & mask)) 1136 tlb_lld_2m = (cpuid_eax(0x80000005) >> 16) & 0xff; 1137 else 1138 tlb_lld_2m = (eax >> 16) & mask; 1139 1140 /* a 4M entry uses two 2M entries */ 1141 tlb_lld_4m = tlb_lld_2m >> 1; 1142 1143 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 1144 if (!(eax & mask)) { 1145 /* Erratum 658 */ 1146 if (c->x86 == 0x15 && c->x86_model <= 0x1f) { 1147 tlb_lli_2m = 1024; 1148 } else { 1149 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 1150 tlb_lli_2m = eax & 0xff; 1151 } 1152 } else 1153 tlb_lli_2m = eax & mask; 1154 1155 tlb_lli_4m = tlb_lli_2m >> 1; 1156 1157 /* Max number of pages INVLPGB can invalidate in one shot */ 1158 if (cpu_has(c, X86_FEATURE_INVLPGB)) 1159 invlpgb_count_max = (cpuid_edx(0x80000008) & 0xffff) + 1; 1160 } 1161 1162 static const struct cpu_dev amd_cpu_dev = { 1163 .c_vendor = "AMD", 1164 .c_ident = { "AuthenticAMD" }, 1165 #ifdef CONFIG_X86_32 1166 .legacy_models = { 1167 { .family = 4, .model_names = 1168 { 1169 [3] = "486 DX/2", 1170 [7] = "486 DX/2-WB", 1171 [8] = "486 DX/4", 1172 [9] = "486 DX/4-WB", 1173 [14] = "Am5x86-WT", 1174 [15] = "Am5x86-WB" 1175 } 1176 }, 1177 }, 1178 .legacy_cache_size = amd_size_cache, 1179 #endif 1180 .c_early_init = early_init_amd, 1181 .c_detect_tlb = cpu_detect_tlb_amd, 1182 .c_bsp_init = bsp_init_amd, 1183 .c_init = init_amd, 1184 .c_x86_vendor = X86_VENDOR_AMD, 1185 }; 1186 1187 cpu_dev_register(amd_cpu_dev); 1188 1189 static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[4], amd_dr_addr_mask); 1190 1191 static unsigned int amd_msr_dr_addr_masks[] = { 1192 MSR_F16H_DR0_ADDR_MASK, 1193 MSR_F16H_DR1_ADDR_MASK, 1194 MSR_F16H_DR1_ADDR_MASK + 1, 1195 MSR_F16H_DR1_ADDR_MASK + 2 1196 }; 1197 1198 void amd_set_dr_addr_mask(unsigned long mask, unsigned int dr) 1199 { 1200 int cpu = smp_processor_id(); 1201 1202 if (!cpu_feature_enabled(X86_FEATURE_BPEXT)) 1203 return; 1204 1205 if (WARN_ON_ONCE(dr >= ARRAY_SIZE(amd_msr_dr_addr_masks))) 1206 return; 1207 1208 if (per_cpu(amd_dr_addr_mask, cpu)[dr] == mask) 1209 return; 1210 1211 wrmsrq(amd_msr_dr_addr_masks[dr], mask); 1212 per_cpu(amd_dr_addr_mask, cpu)[dr] = mask; 1213 } 1214 1215 unsigned long amd_get_dr_addr_mask(unsigned int dr) 1216 { 1217 if (!cpu_feature_enabled(X86_FEATURE_BPEXT)) 1218 return 0; 1219 1220 if (WARN_ON_ONCE(dr >= ARRAY_SIZE(amd_msr_dr_addr_masks))) 1221 return 0; 1222 1223 return per_cpu(amd_dr_addr_mask[dr], smp_processor_id()); 1224 } 1225 EXPORT_SYMBOL_GPL(amd_get_dr_addr_mask); 1226 1227 static void zenbleed_check_cpu(void *unused) 1228 { 1229 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 1230 1231 zen2_zenbleed_check(c); 1232 } 1233 1234 void amd_check_microcode(void) 1235 { 1236 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) 1237 return; 1238 1239 if (cpu_feature_enabled(X86_FEATURE_ZEN2)) 1240 on_each_cpu(zenbleed_check_cpu, NULL, 1); 1241 } 1242 1243 static const char * const s5_reset_reason_txt[] = { 1244 [0] = "thermal pin BP_THERMTRIP_L was tripped", 1245 [1] = "power button was pressed for 4 seconds", 1246 [2] = "shutdown pin was tripped", 1247 [4] = "remote ASF power off command was received", 1248 [9] = "internal CPU thermal limit was tripped", 1249 [16] = "system reset pin BP_SYS_RST_L was tripped", 1250 [17] = "software issued PCI reset", 1251 [18] = "software wrote 0x4 to reset control register 0xCF9", 1252 [19] = "software wrote 0x6 to reset control register 0xCF9", 1253 [20] = "software wrote 0xE to reset control register 0xCF9", 1254 [21] = "ACPI power state transition occurred", 1255 [22] = "keyboard reset pin KB_RST_L was tripped", 1256 [23] = "internal CPU shutdown event occurred", 1257 [24] = "system failed to boot before failed boot timer expired", 1258 [25] = "hardware watchdog timer expired", 1259 [26] = "remote ASF reset command was received", 1260 [27] = "an uncorrected error caused a data fabric sync flood event", 1261 [29] = "FCH and MP1 failed warm reset handshake", 1262 [30] = "a parity error occurred", 1263 [31] = "a software sync flood event occurred", 1264 }; 1265 1266 static __init int print_s5_reset_status_mmio(void) 1267 { 1268 unsigned long value; 1269 void __iomem *addr; 1270 int i; 1271 1272 if (!cpu_feature_enabled(X86_FEATURE_ZEN)) 1273 return 0; 1274 1275 addr = ioremap(FCH_PM_BASE + FCH_PM_S5_RESET_STATUS, sizeof(value)); 1276 if (!addr) 1277 return 0; 1278 1279 value = ioread32(addr); 1280 iounmap(addr); 1281 1282 for (i = 0; i < ARRAY_SIZE(s5_reset_reason_txt); i++) { 1283 if (!(value & BIT(i))) 1284 continue; 1285 1286 if (s5_reset_reason_txt[i]) { 1287 pr_info("x86/amd: Previous system reset reason [0x%08lx]: %s\n", 1288 value, s5_reset_reason_txt[i]); 1289 } 1290 } 1291 1292 return 0; 1293 } 1294 late_initcall(print_s5_reset_status_mmio); 1295