1 #include <linux/export.h> 2 #include <linux/bitops.h> 3 #include <linux/elf.h> 4 #include <linux/mm.h> 5 6 #include <linux/io.h> 7 #include <linux/sched.h> 8 #include <linux/random.h> 9 #include <asm/processor.h> 10 #include <asm/apic.h> 11 #include <asm/cpu.h> 12 #include <asm/smp.h> 13 #include <asm/pci-direct.h> 14 #include <asm/delay.h> 15 16 #ifdef CONFIG_X86_64 17 # include <asm/mmconfig.h> 18 # include <asm/cacheflush.h> 19 #endif 20 21 #include "cpu.h" 22 23 static const int amd_erratum_383[]; 24 static const int amd_erratum_400[]; 25 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); 26 27 /* 28 * nodes_per_socket: Stores the number of nodes per socket. 29 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX 30 * Node Identifiers[10:8] 31 */ 32 static u32 nodes_per_socket = 1; 33 34 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) 35 { 36 u32 gprs[8] = { 0 }; 37 int err; 38 39 WARN_ONCE((boot_cpu_data.x86 != 0xf), 40 "%s should only be used on K8!\n", __func__); 41 42 gprs[1] = msr; 43 gprs[7] = 0x9c5a203a; 44 45 err = rdmsr_safe_regs(gprs); 46 47 *p = gprs[0] | ((u64)gprs[2] << 32); 48 49 return err; 50 } 51 52 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) 53 { 54 u32 gprs[8] = { 0 }; 55 56 WARN_ONCE((boot_cpu_data.x86 != 0xf), 57 "%s should only be used on K8!\n", __func__); 58 59 gprs[0] = (u32)val; 60 gprs[1] = msr; 61 gprs[2] = val >> 32; 62 gprs[7] = 0x9c5a203a; 63 64 return wrmsr_safe_regs(gprs); 65 } 66 67 /* 68 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 69 * misexecution of code under Linux. Owners of such processors should 70 * contact AMD for precise details and a CPU swap. 71 * 72 * See http://www.multimania.com/poulot/k6bug.html 73 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" 74 * (Publication # 21266 Issue Date: August 1998) 75 * 76 * The following test is erm.. interesting. AMD neglected to up 77 * the chip setting when fixing the bug but they also tweaked some 78 * performance at the same time.. 79 */ 80 81 extern __visible void vide(void); 82 __asm__(".globl vide\n" 83 ".type vide, @function\n" 84 ".align 4\n" 85 "vide: ret\n"); 86 87 static void init_amd_k5(struct cpuinfo_x86 *c) 88 { 89 #ifdef CONFIG_X86_32 90 /* 91 * General Systems BIOSen alias the cpu frequency registers 92 * of the Elan at 0x000df000. Unfortunately, one of the Linux 93 * drivers subsequently pokes it, and changes the CPU speed. 94 * Workaround : Remove the unneeded alias. 95 */ 96 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 97 #define CBAR_ENB (0x80000000) 98 #define CBAR_KEY (0X000000CB) 99 if (c->x86_model == 9 || c->x86_model == 10) { 100 if (inl(CBAR) & CBAR_ENB) 101 outl(0 | CBAR_KEY, CBAR); 102 } 103 #endif 104 } 105 106 static void init_amd_k6(struct cpuinfo_x86 *c) 107 { 108 #ifdef CONFIG_X86_32 109 u32 l, h; 110 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); 111 112 if (c->x86_model < 6) { 113 /* Based on AMD doc 20734R - June 2000 */ 114 if (c->x86_model == 0) { 115 clear_cpu_cap(c, X86_FEATURE_APIC); 116 set_cpu_cap(c, X86_FEATURE_PGE); 117 } 118 return; 119 } 120 121 if (c->x86_model == 6 && c->x86_mask == 1) { 122 const int K6_BUG_LOOP = 1000000; 123 int n; 124 void (*f_vide)(void); 125 u64 d, d2; 126 127 pr_info("AMD K6 stepping B detected - "); 128 129 /* 130 * It looks like AMD fixed the 2.6.2 bug and improved indirect 131 * calls at the same time. 132 */ 133 134 n = K6_BUG_LOOP; 135 f_vide = vide; 136 d = rdtsc(); 137 while (n--) 138 f_vide(); 139 d2 = rdtsc(); 140 d = d2-d; 141 142 if (d > 20*K6_BUG_LOOP) 143 pr_cont("system stability may be impaired when more than 32 MB are used.\n"); 144 else 145 pr_cont("probably OK (after B9730xxxx).\n"); 146 } 147 148 /* K6 with old style WHCR */ 149 if (c->x86_model < 8 || 150 (c->x86_model == 8 && c->x86_mask < 8)) { 151 /* We can only write allocate on the low 508Mb */ 152 if (mbytes > 508) 153 mbytes = 508; 154 155 rdmsr(MSR_K6_WHCR, l, h); 156 if ((l&0x0000FFFF) == 0) { 157 unsigned long flags; 158 l = (1<<0)|((mbytes/4)<<1); 159 local_irq_save(flags); 160 wbinvd(); 161 wrmsr(MSR_K6_WHCR, l, h); 162 local_irq_restore(flags); 163 pr_info("Enabling old style K6 write allocation for %d Mb\n", 164 mbytes); 165 } 166 return; 167 } 168 169 if ((c->x86_model == 8 && c->x86_mask > 7) || 170 c->x86_model == 9 || c->x86_model == 13) { 171 /* The more serious chips .. */ 172 173 if (mbytes > 4092) 174 mbytes = 4092; 175 176 rdmsr(MSR_K6_WHCR, l, h); 177 if ((l&0xFFFF0000) == 0) { 178 unsigned long flags; 179 l = ((mbytes>>2)<<22)|(1<<16); 180 local_irq_save(flags); 181 wbinvd(); 182 wrmsr(MSR_K6_WHCR, l, h); 183 local_irq_restore(flags); 184 pr_info("Enabling new style K6 write allocation for %d Mb\n", 185 mbytes); 186 } 187 188 return; 189 } 190 191 if (c->x86_model == 10) { 192 /* AMD Geode LX is model 10 */ 193 /* placeholder for any needed mods */ 194 return; 195 } 196 #endif 197 } 198 199 static void init_amd_k7(struct cpuinfo_x86 *c) 200 { 201 #ifdef CONFIG_X86_32 202 u32 l, h; 203 204 /* 205 * Bit 15 of Athlon specific MSR 15, needs to be 0 206 * to enable SSE on Palomino/Morgan/Barton CPU's. 207 * If the BIOS didn't enable it already, enable it here. 208 */ 209 if (c->x86_model >= 6 && c->x86_model <= 10) { 210 if (!cpu_has(c, X86_FEATURE_XMM)) { 211 pr_info("Enabling disabled K7/SSE Support.\n"); 212 msr_clear_bit(MSR_K7_HWCR, 15); 213 set_cpu_cap(c, X86_FEATURE_XMM); 214 } 215 } 216 217 /* 218 * It's been determined by AMD that Athlons since model 8 stepping 1 219 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 220 * As per AMD technical note 27212 0.2 221 */ 222 if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) { 223 rdmsr(MSR_K7_CLK_CTL, l, h); 224 if ((l & 0xfff00000) != 0x20000000) { 225 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", 226 l, ((l & 0x000fffff)|0x20000000)); 227 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 228 } 229 } 230 231 set_cpu_cap(c, X86_FEATURE_K7); 232 233 /* calling is from identify_secondary_cpu() ? */ 234 if (!c->cpu_index) 235 return; 236 237 /* 238 * Certain Athlons might work (for various values of 'work') in SMP 239 * but they are not certified as MP capable. 240 */ 241 /* Athlon 660/661 is valid. */ 242 if ((c->x86_model == 6) && ((c->x86_mask == 0) || 243 (c->x86_mask == 1))) 244 return; 245 246 /* Duron 670 is valid */ 247 if ((c->x86_model == 7) && (c->x86_mask == 0)) 248 return; 249 250 /* 251 * Athlon 662, Duron 671, and Athlon >model 7 have capability 252 * bit. It's worth noting that the A5 stepping (662) of some 253 * Athlon XP's have the MP bit set. 254 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for 255 * more. 256 */ 257 if (((c->x86_model == 6) && (c->x86_mask >= 2)) || 258 ((c->x86_model == 7) && (c->x86_mask >= 1)) || 259 (c->x86_model > 7)) 260 if (cpu_has(c, X86_FEATURE_MP)) 261 return; 262 263 /* If we get here, not a certified SMP capable AMD system. */ 264 265 /* 266 * Don't taint if we are running SMP kernel on a single non-MP 267 * approved Athlon 268 */ 269 WARN_ONCE(1, "WARNING: This combination of AMD" 270 " processors is not suitable for SMP.\n"); 271 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 272 #endif 273 } 274 275 #ifdef CONFIG_NUMA 276 /* 277 * To workaround broken NUMA config. Read the comment in 278 * srat_detect_node(). 279 */ 280 static int nearby_node(int apicid) 281 { 282 int i, node; 283 284 for (i = apicid - 1; i >= 0; i--) { 285 node = __apicid_to_node[i]; 286 if (node != NUMA_NO_NODE && node_online(node)) 287 return node; 288 } 289 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 290 node = __apicid_to_node[i]; 291 if (node != NUMA_NO_NODE && node_online(node)) 292 return node; 293 } 294 return first_node(node_online_map); /* Shouldn't happen */ 295 } 296 #endif 297 298 /* 299 * Fixup core topology information for 300 * (1) AMD multi-node processors 301 * Assumption: Number of cores in each internal node is the same. 302 * (2) AMD processors supporting compute units 303 */ 304 #ifdef CONFIG_SMP 305 static void amd_get_topology(struct cpuinfo_x86 *c) 306 { 307 u8 node_id; 308 int cpu = smp_processor_id(); 309 310 /* get information required for multi-node processors */ 311 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 312 u32 eax, ebx, ecx, edx; 313 314 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); 315 node_id = ecx & 7; 316 317 /* get compute unit information */ 318 smp_num_siblings = ((ebx >> 8) & 3) + 1; 319 c->x86_max_cores /= smp_num_siblings; 320 c->cpu_core_id = ebx & 0xff; 321 322 /* 323 * We may have multiple LLCs if L3 caches exist, so check if we 324 * have an L3 cache by looking at the L3 cache CPUID leaf. 325 */ 326 if (cpuid_edx(0x80000006)) { 327 if (c->x86 == 0x17) { 328 /* 329 * LLC is at the core complex level. 330 * Core complex id is ApicId[3]. 331 */ 332 per_cpu(cpu_llc_id, cpu) = c->apicid >> 3; 333 } else { 334 /* LLC is at the node level. */ 335 per_cpu(cpu_llc_id, cpu) = node_id; 336 } 337 } 338 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { 339 u64 value; 340 341 rdmsrl(MSR_FAM10H_NODE_ID, value); 342 node_id = value & 7; 343 344 per_cpu(cpu_llc_id, cpu) = node_id; 345 } else 346 return; 347 348 /* fixup multi-node processor information */ 349 if (nodes_per_socket > 1) { 350 u32 cus_per_node; 351 352 set_cpu_cap(c, X86_FEATURE_AMD_DCM); 353 cus_per_node = c->x86_max_cores / nodes_per_socket; 354 355 /* core id has to be in the [0 .. cores_per_node - 1] range */ 356 c->cpu_core_id %= cus_per_node; 357 } 358 } 359 #endif 360 361 /* 362 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores. 363 * Assumes number of cores is a power of two. 364 */ 365 static void amd_detect_cmp(struct cpuinfo_x86 *c) 366 { 367 #ifdef CONFIG_SMP 368 unsigned bits; 369 int cpu = smp_processor_id(); 370 371 bits = c->x86_coreid_bits; 372 /* Low order bits define the core id (index of core in socket) */ 373 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); 374 /* Convert the initial APIC ID into the socket ID */ 375 c->phys_proc_id = c->initial_apicid >> bits; 376 /* use socket ID also for last level cache */ 377 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; 378 amd_get_topology(c); 379 #endif 380 } 381 382 u16 amd_get_nb_id(int cpu) 383 { 384 u16 id = 0; 385 #ifdef CONFIG_SMP 386 id = per_cpu(cpu_llc_id, cpu); 387 #endif 388 return id; 389 } 390 EXPORT_SYMBOL_GPL(amd_get_nb_id); 391 392 u32 amd_get_nodes_per_socket(void) 393 { 394 return nodes_per_socket; 395 } 396 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket); 397 398 static void srat_detect_node(struct cpuinfo_x86 *c) 399 { 400 #ifdef CONFIG_NUMA 401 int cpu = smp_processor_id(); 402 int node; 403 unsigned apicid = c->apicid; 404 405 node = numa_cpu_node(cpu); 406 if (node == NUMA_NO_NODE) 407 node = per_cpu(cpu_llc_id, cpu); 408 409 /* 410 * On multi-fabric platform (e.g. Numascale NumaChip) a 411 * platform-specific handler needs to be called to fixup some 412 * IDs of the CPU. 413 */ 414 if (x86_cpuinit.fixup_cpu_id) 415 x86_cpuinit.fixup_cpu_id(c, node); 416 417 if (!node_online(node)) { 418 /* 419 * Two possibilities here: 420 * 421 * - The CPU is missing memory and no node was created. In 422 * that case try picking one from a nearby CPU. 423 * 424 * - The APIC IDs differ from the HyperTransport node IDs 425 * which the K8 northbridge parsing fills in. Assume 426 * they are all increased by a constant offset, but in 427 * the same order as the HT nodeids. If that doesn't 428 * result in a usable node fall back to the path for the 429 * previous case. 430 * 431 * This workaround operates directly on the mapping between 432 * APIC ID and NUMA node, assuming certain relationship 433 * between APIC ID, HT node ID and NUMA topology. As going 434 * through CPU mapping may alter the outcome, directly 435 * access __apicid_to_node[]. 436 */ 437 int ht_nodeid = c->initial_apicid; 438 439 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 440 node = __apicid_to_node[ht_nodeid]; 441 /* Pick a nearby node */ 442 if (!node_online(node)) 443 node = nearby_node(apicid); 444 } 445 numa_set_node(cpu, node); 446 #endif 447 } 448 449 static void early_init_amd_mc(struct cpuinfo_x86 *c) 450 { 451 #ifdef CONFIG_SMP 452 unsigned bits, ecx; 453 454 /* Multi core CPU? */ 455 if (c->extended_cpuid_level < 0x80000008) 456 return; 457 458 ecx = cpuid_ecx(0x80000008); 459 460 c->x86_max_cores = (ecx & 0xff) + 1; 461 462 /* CPU telling us the core id bits shift? */ 463 bits = (ecx >> 12) & 0xF; 464 465 /* Otherwise recompute */ 466 if (bits == 0) { 467 while ((1 << bits) < c->x86_max_cores) 468 bits++; 469 } 470 471 c->x86_coreid_bits = bits; 472 #endif 473 } 474 475 static void bsp_init_amd(struct cpuinfo_x86 *c) 476 { 477 478 #ifdef CONFIG_X86_64 479 if (c->x86 >= 0xf) { 480 unsigned long long tseg; 481 482 /* 483 * Split up direct mapping around the TSEG SMM area. 484 * Don't do it for gbpages because there seems very little 485 * benefit in doing so. 486 */ 487 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { 488 unsigned long pfn = tseg >> PAGE_SHIFT; 489 490 pr_debug("tseg: %010llx\n", tseg); 491 if (pfn_range_is_mapped(pfn, pfn + 1)) 492 set_memory_4k((unsigned long)__va(tseg), 1); 493 } 494 } 495 #endif 496 497 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 498 499 if (c->x86 > 0x10 || 500 (c->x86 == 0x10 && c->x86_model >= 0x2)) { 501 u64 val; 502 503 rdmsrl(MSR_K7_HWCR, val); 504 if (!(val & BIT(24))) 505 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); 506 } 507 } 508 509 if (c->x86 == 0x15) { 510 unsigned long upperbit; 511 u32 cpuid, assoc; 512 513 cpuid = cpuid_edx(0x80000005); 514 assoc = cpuid >> 16 & 0xff; 515 upperbit = ((cpuid >> 24) << 10) / assoc; 516 517 va_align.mask = (upperbit - 1) & PAGE_MASK; 518 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; 519 520 /* A random value per boot for bit slice [12:upper_bit) */ 521 va_align.bits = get_random_int() & va_align.mask; 522 } 523 524 if (cpu_has(c, X86_FEATURE_MWAITX)) 525 use_mwaitx_delay(); 526 527 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 528 u32 ecx; 529 530 ecx = cpuid_ecx(0x8000001e); 531 nodes_per_socket = ((ecx >> 8) & 7) + 1; 532 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) { 533 u64 value; 534 535 rdmsrl(MSR_FAM10H_NODE_ID, value); 536 nodes_per_socket = ((value >> 3) & 7) + 1; 537 } 538 } 539 540 static void early_init_amd(struct cpuinfo_x86 *c) 541 { 542 early_init_amd_mc(c); 543 544 /* 545 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 546 * with P/T states and does not stop in deep C-states 547 */ 548 if (c->x86_power & (1 << 8)) { 549 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 550 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 551 if (!check_tsc_unstable()) 552 set_sched_clock_stable(); 553 } 554 555 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ 556 if (c->x86_power & BIT(12)) 557 set_cpu_cap(c, X86_FEATURE_ACC_POWER); 558 559 #ifdef CONFIG_X86_64 560 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 561 #else 562 /* Set MTRR capability flag if appropriate */ 563 if (c->x86 == 5) 564 if (c->x86_model == 13 || c->x86_model == 9 || 565 (c->x86_model == 8 && c->x86_mask >= 8)) 566 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 567 #endif 568 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 569 /* 570 * ApicID can always be treated as an 8-bit value for AMD APIC versions 571 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we 572 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families 573 * after 16h. 574 */ 575 if (boot_cpu_has(X86_FEATURE_APIC)) { 576 if (c->x86 > 0x16) 577 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 578 else if (c->x86 >= 0xf) { 579 /* check CPU config space for extended APIC ID */ 580 unsigned int val; 581 582 val = read_pci_config(0, 24, 0, 0x68); 583 if ((val >> 17 & 0x3) == 0x3) 584 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 585 } 586 } 587 #endif 588 589 /* 590 * This is only needed to tell the kernel whether to use VMCALL 591 * and VMMCALL. VMMCALL is never executed except under virt, so 592 * we can set it unconditionally. 593 */ 594 set_cpu_cap(c, X86_FEATURE_VMMCALL); 595 596 /* F16h erratum 793, CVE-2013-6885 */ 597 if (c->x86 == 0x16 && c->x86_model <= 0xf) 598 msr_set_bit(MSR_AMD64_LS_CFG, 15); 599 600 /* 601 * Check whether the machine is affected by erratum 400. This is 602 * used to select the proper idle routine and to enable the check 603 * whether the machine is affected in arch_post_acpi_init(), which 604 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check. 605 */ 606 if (cpu_has_amd_erratum(c, amd_erratum_400)) 607 set_cpu_bug(c, X86_BUG_AMD_E400); 608 } 609 610 static void init_amd_k8(struct cpuinfo_x86 *c) 611 { 612 u32 level; 613 u64 value; 614 615 /* On C+ stepping K8 rep microcode works well for copy/memset */ 616 level = cpuid_eax(1); 617 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) 618 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 619 620 /* 621 * Some BIOSes incorrectly force this feature, but only K8 revision D 622 * (model = 0x14) and later actually support it. 623 * (AMD Erratum #110, docId: 25759). 624 */ 625 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { 626 clear_cpu_cap(c, X86_FEATURE_LAHF_LM); 627 if (!rdmsrl_amd_safe(0xc001100d, &value)) { 628 value &= ~BIT_64(32); 629 wrmsrl_amd_safe(0xc001100d, value); 630 } 631 } 632 633 if (!c->x86_model_id[0]) 634 strcpy(c->x86_model_id, "Hammer"); 635 636 #ifdef CONFIG_SMP 637 /* 638 * Disable TLB flush filter by setting HWCR.FFDIS on K8 639 * bit 6 of msr C001_0015 640 * 641 * Errata 63 for SH-B3 steppings 642 * Errata 122 for all steppings (F+ have it disabled by default) 643 */ 644 msr_set_bit(MSR_K7_HWCR, 6); 645 #endif 646 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE); 647 } 648 649 static void init_amd_gh(struct cpuinfo_x86 *c) 650 { 651 #ifdef CONFIG_X86_64 652 /* do this for boot cpu */ 653 if (c == &boot_cpu_data) 654 check_enable_amd_mmconf_dmi(); 655 656 fam10h_check_enable_mmcfg(); 657 #endif 658 659 /* 660 * Disable GART TLB Walk Errors on Fam10h. We do this here because this 661 * is always needed when GART is enabled, even in a kernel which has no 662 * MCE support built in. BIOS should disable GartTlbWlk Errors already. 663 * If it doesn't, we do it here as suggested by the BKDG. 664 * 665 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 666 */ 667 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10); 668 669 /* 670 * On family 10h BIOS may not have properly enabled WC+ support, causing 671 * it to be converted to CD memtype. This may result in performance 672 * degradation for certain nested-paging guests. Prevent this conversion 673 * by clearing bit 24 in MSR_AMD64_BU_CFG2. 674 * 675 * NOTE: we want to use the _safe accessors so as not to #GP kvm 676 * guests on older kvm hosts. 677 */ 678 msr_clear_bit(MSR_AMD64_BU_CFG2, 24); 679 680 if (cpu_has_amd_erratum(c, amd_erratum_383)) 681 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH); 682 } 683 684 #define MSR_AMD64_DE_CFG 0xC0011029 685 686 static void init_amd_ln(struct cpuinfo_x86 *c) 687 { 688 /* 689 * Apply erratum 665 fix unconditionally so machines without a BIOS 690 * fix work. 691 */ 692 msr_set_bit(MSR_AMD64_DE_CFG, 31); 693 } 694 695 static void init_amd_bd(struct cpuinfo_x86 *c) 696 { 697 u64 value; 698 699 /* re-enable TopologyExtensions if switched off by BIOS */ 700 if ((c->x86_model >= 0x10) && (c->x86_model <= 0x6f) && 701 !cpu_has(c, X86_FEATURE_TOPOEXT)) { 702 703 if (msr_set_bit(0xc0011005, 54) > 0) { 704 rdmsrl(0xc0011005, value); 705 if (value & BIT_64(54)) { 706 set_cpu_cap(c, X86_FEATURE_TOPOEXT); 707 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n"); 708 } 709 } 710 } 711 712 /* 713 * The way access filter has a performance penalty on some workloads. 714 * Disable it on the affected CPUs. 715 */ 716 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) { 717 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) { 718 value |= 0x1E; 719 wrmsrl_safe(MSR_F15H_IC_CFG, value); 720 } 721 } 722 } 723 724 static void init_amd(struct cpuinfo_x86 *c) 725 { 726 u32 dummy; 727 728 early_init_amd(c); 729 730 /* 731 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 732 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 733 */ 734 clear_cpu_cap(c, 0*32+31); 735 736 if (c->x86 >= 0x10) 737 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 738 739 /* get apicid instead of initial apic id from cpuid */ 740 c->apicid = hard_smp_processor_id(); 741 742 /* K6s reports MCEs but don't actually have all the MSRs */ 743 if (c->x86 < 6) 744 clear_cpu_cap(c, X86_FEATURE_MCE); 745 746 switch (c->x86) { 747 case 4: init_amd_k5(c); break; 748 case 5: init_amd_k6(c); break; 749 case 6: init_amd_k7(c); break; 750 case 0xf: init_amd_k8(c); break; 751 case 0x10: init_amd_gh(c); break; 752 case 0x12: init_amd_ln(c); break; 753 case 0x15: init_amd_bd(c); break; 754 } 755 756 /* Enable workaround for FXSAVE leak */ 757 if (c->x86 >= 6) 758 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK); 759 760 cpu_detect_cache_sizes(c); 761 762 /* Multi core CPU? */ 763 if (c->extended_cpuid_level >= 0x80000008) { 764 amd_detect_cmp(c); 765 srat_detect_node(c); 766 } 767 768 #ifdef CONFIG_X86_32 769 detect_ht(c); 770 #endif 771 772 init_amd_cacheinfo(c); 773 774 if (c->x86 >= 0xf) 775 set_cpu_cap(c, X86_FEATURE_K8); 776 777 if (cpu_has(c, X86_FEATURE_XMM2)) { 778 /* MFENCE stops RDTSC speculation */ 779 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); 780 } 781 782 /* 783 * Family 0x12 and above processors have APIC timer 784 * running in deep C states. 785 */ 786 if (c->x86 > 0x11) 787 set_cpu_cap(c, X86_FEATURE_ARAT); 788 789 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); 790 791 /* 3DNow or LM implies PREFETCHW */ 792 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH)) 793 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM)) 794 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH); 795 796 /* AMD CPUs don't reset SS attributes on SYSRET */ 797 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); 798 } 799 800 #ifdef CONFIG_X86_32 801 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) 802 { 803 /* AMD errata T13 (order #21922) */ 804 if ((c->x86 == 6)) { 805 /* Duron Rev A0 */ 806 if (c->x86_model == 3 && c->x86_mask == 0) 807 size = 64; 808 /* Tbird rev A1/A2 */ 809 if (c->x86_model == 4 && 810 (c->x86_mask == 0 || c->x86_mask == 1)) 811 size = 256; 812 } 813 return size; 814 } 815 #endif 816 817 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) 818 { 819 u32 ebx, eax, ecx, edx; 820 u16 mask = 0xfff; 821 822 if (c->x86 < 0xf) 823 return; 824 825 if (c->extended_cpuid_level < 0x80000006) 826 return; 827 828 cpuid(0x80000006, &eax, &ebx, &ecx, &edx); 829 830 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask; 831 tlb_lli_4k[ENTRIES] = ebx & mask; 832 833 /* 834 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB 835 * characteristics from the CPUID function 0x80000005 instead. 836 */ 837 if (c->x86 == 0xf) { 838 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 839 mask = 0xff; 840 } 841 842 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 843 if (!((eax >> 16) & mask)) 844 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff; 845 else 846 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask; 847 848 /* a 4M entry uses two 2M entries */ 849 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1; 850 851 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 852 if (!(eax & mask)) { 853 /* Erratum 658 */ 854 if (c->x86 == 0x15 && c->x86_model <= 0x1f) { 855 tlb_lli_2m[ENTRIES] = 1024; 856 } else { 857 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 858 tlb_lli_2m[ENTRIES] = eax & 0xff; 859 } 860 } else 861 tlb_lli_2m[ENTRIES] = eax & mask; 862 863 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; 864 } 865 866 static const struct cpu_dev amd_cpu_dev = { 867 .c_vendor = "AMD", 868 .c_ident = { "AuthenticAMD" }, 869 #ifdef CONFIG_X86_32 870 .legacy_models = { 871 { .family = 4, .model_names = 872 { 873 [3] = "486 DX/2", 874 [7] = "486 DX/2-WB", 875 [8] = "486 DX/4", 876 [9] = "486 DX/4-WB", 877 [14] = "Am5x86-WT", 878 [15] = "Am5x86-WB" 879 } 880 }, 881 }, 882 .legacy_cache_size = amd_size_cache, 883 #endif 884 .c_early_init = early_init_amd, 885 .c_detect_tlb = cpu_detect_tlb_amd, 886 .c_bsp_init = bsp_init_amd, 887 .c_init = init_amd, 888 .c_x86_vendor = X86_VENDOR_AMD, 889 }; 890 891 cpu_dev_register(amd_cpu_dev); 892 893 /* 894 * AMD errata checking 895 * 896 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or 897 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that 898 * have an OSVW id assigned, which it takes as first argument. Both take a 899 * variable number of family-specific model-stepping ranges created by 900 * AMD_MODEL_RANGE(). 901 * 902 * Example: 903 * 904 * const int amd_erratum_319[] = 905 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), 906 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), 907 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); 908 */ 909 910 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } 911 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } 912 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ 913 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) 914 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) 915 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) 916 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) 917 918 static const int amd_erratum_400[] = 919 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), 920 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); 921 922 static const int amd_erratum_383[] = 923 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); 924 925 926 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) 927 { 928 int osvw_id = *erratum++; 929 u32 range; 930 u32 ms; 931 932 if (osvw_id >= 0 && osvw_id < 65536 && 933 cpu_has(cpu, X86_FEATURE_OSVW)) { 934 u64 osvw_len; 935 936 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); 937 if (osvw_id < osvw_len) { 938 u64 osvw_bits; 939 940 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), 941 osvw_bits); 942 return osvw_bits & (1ULL << (osvw_id & 0x3f)); 943 } 944 } 945 946 /* OSVW unavailable or ID unknown, match family-model-stepping range */ 947 ms = (cpu->x86_model << 4) | cpu->x86_mask; 948 while ((range = *erratum++)) 949 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && 950 (ms >= AMD_MODEL_RANGE_START(range)) && 951 (ms <= AMD_MODEL_RANGE_END(range))) 952 return true; 953 954 return false; 955 } 956 957 void set_dr_addr_mask(unsigned long mask, int dr) 958 { 959 if (!boot_cpu_has(X86_FEATURE_BPEXT)) 960 return; 961 962 switch (dr) { 963 case 0: 964 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0); 965 break; 966 case 1: 967 case 2: 968 case 3: 969 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0); 970 break; 971 default: 972 break; 973 } 974 } 975