1 #include <linux/init.h> 2 #include <linux/bitops.h> 3 #include <linux/mm.h> 4 5 #include <linux/io.h> 6 #include <asm/processor.h> 7 #include <asm/apic.h> 8 #include <asm/cpu.h> 9 #include <asm/pci-direct.h> 10 11 #ifdef CONFIG_X86_64 12 # include <asm/numa_64.h> 13 # include <asm/mmconfig.h> 14 # include <asm/cacheflush.h> 15 #endif 16 17 #include "cpu.h" 18 19 #ifdef CONFIG_X86_32 20 /* 21 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 22 * misexecution of code under Linux. Owners of such processors should 23 * contact AMD for precise details and a CPU swap. 24 * 25 * See http://www.multimania.com/poulot/k6bug.html 26 * http://www.amd.com/K6/k6docs/revgd.html 27 * 28 * The following test is erm.. interesting. AMD neglected to up 29 * the chip setting when fixing the bug but they also tweaked some 30 * performance at the same time.. 31 */ 32 33 extern void vide(void); 34 __asm__(".align 4\nvide: ret"); 35 36 static void __cpuinit init_amd_k5(struct cpuinfo_x86 *c) 37 { 38 /* 39 * General Systems BIOSen alias the cpu frequency registers 40 * of the Elan at 0x000df000. Unfortuantly, one of the Linux 41 * drivers subsequently pokes it, and changes the CPU speed. 42 * Workaround : Remove the unneeded alias. 43 */ 44 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 45 #define CBAR_ENB (0x80000000) 46 #define CBAR_KEY (0X000000CB) 47 if (c->x86_model == 9 || c->x86_model == 10) { 48 if (inl(CBAR) & CBAR_ENB) 49 outl(0 | CBAR_KEY, CBAR); 50 } 51 } 52 53 54 static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c) 55 { 56 u32 l, h; 57 int mbytes = num_physpages >> (20-PAGE_SHIFT); 58 59 if (c->x86_model < 6) { 60 /* Based on AMD doc 20734R - June 2000 */ 61 if (c->x86_model == 0) { 62 clear_cpu_cap(c, X86_FEATURE_APIC); 63 set_cpu_cap(c, X86_FEATURE_PGE); 64 } 65 return; 66 } 67 68 if (c->x86_model == 6 && c->x86_mask == 1) { 69 const int K6_BUG_LOOP = 1000000; 70 int n; 71 void (*f_vide)(void); 72 unsigned long d, d2; 73 74 printk(KERN_INFO "AMD K6 stepping B detected - "); 75 76 /* 77 * It looks like AMD fixed the 2.6.2 bug and improved indirect 78 * calls at the same time. 79 */ 80 81 n = K6_BUG_LOOP; 82 f_vide = vide; 83 rdtscl(d); 84 while (n--) 85 f_vide(); 86 rdtscl(d2); 87 d = d2-d; 88 89 if (d > 20*K6_BUG_LOOP) 90 printk(KERN_CONT 91 "system stability may be impaired when more than 32 MB are used.\n"); 92 else 93 printk(KERN_CONT "probably OK (after B9730xxxx).\n"); 94 printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n"); 95 } 96 97 /* K6 with old style WHCR */ 98 if (c->x86_model < 8 || 99 (c->x86_model == 8 && c->x86_mask < 8)) { 100 /* We can only write allocate on the low 508Mb */ 101 if (mbytes > 508) 102 mbytes = 508; 103 104 rdmsr(MSR_K6_WHCR, l, h); 105 if ((l&0x0000FFFF) == 0) { 106 unsigned long flags; 107 l = (1<<0)|((mbytes/4)<<1); 108 local_irq_save(flags); 109 wbinvd(); 110 wrmsr(MSR_K6_WHCR, l, h); 111 local_irq_restore(flags); 112 printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n", 113 mbytes); 114 } 115 return; 116 } 117 118 if ((c->x86_model == 8 && c->x86_mask > 7) || 119 c->x86_model == 9 || c->x86_model == 13) { 120 /* The more serious chips .. */ 121 122 if (mbytes > 4092) 123 mbytes = 4092; 124 125 rdmsr(MSR_K6_WHCR, l, h); 126 if ((l&0xFFFF0000) == 0) { 127 unsigned long flags; 128 l = ((mbytes>>2)<<22)|(1<<16); 129 local_irq_save(flags); 130 wbinvd(); 131 wrmsr(MSR_K6_WHCR, l, h); 132 local_irq_restore(flags); 133 printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n", 134 mbytes); 135 } 136 137 return; 138 } 139 140 if (c->x86_model == 10) { 141 /* AMD Geode LX is model 10 */ 142 /* placeholder for any needed mods */ 143 return; 144 } 145 } 146 147 static void __cpuinit amd_k7_smp_check(struct cpuinfo_x86 *c) 148 { 149 #ifdef CONFIG_SMP 150 /* calling is from identify_secondary_cpu() ? */ 151 if (c->cpu_index == boot_cpu_id) 152 return; 153 154 /* 155 * Certain Athlons might work (for various values of 'work') in SMP 156 * but they are not certified as MP capable. 157 */ 158 /* Athlon 660/661 is valid. */ 159 if ((c->x86_model == 6) && ((c->x86_mask == 0) || 160 (c->x86_mask == 1))) 161 goto valid_k7; 162 163 /* Duron 670 is valid */ 164 if ((c->x86_model == 7) && (c->x86_mask == 0)) 165 goto valid_k7; 166 167 /* 168 * Athlon 662, Duron 671, and Athlon >model 7 have capability 169 * bit. It's worth noting that the A5 stepping (662) of some 170 * Athlon XP's have the MP bit set. 171 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for 172 * more. 173 */ 174 if (((c->x86_model == 6) && (c->x86_mask >= 2)) || 175 ((c->x86_model == 7) && (c->x86_mask >= 1)) || 176 (c->x86_model > 7)) 177 if (cpu_has_mp) 178 goto valid_k7; 179 180 /* If we get here, not a certified SMP capable AMD system. */ 181 182 /* 183 * Don't taint if we are running SMP kernel on a single non-MP 184 * approved Athlon 185 */ 186 WARN_ONCE(1, "WARNING: This combination of AMD" 187 "processors is not suitable for SMP.\n"); 188 if (!test_taint(TAINT_UNSAFE_SMP)) 189 add_taint(TAINT_UNSAFE_SMP); 190 191 valid_k7: 192 ; 193 #endif 194 } 195 196 static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c) 197 { 198 u32 l, h; 199 200 /* 201 * Bit 15 of Athlon specific MSR 15, needs to be 0 202 * to enable SSE on Palomino/Morgan/Barton CPU's. 203 * If the BIOS didn't enable it already, enable it here. 204 */ 205 if (c->x86_model >= 6 && c->x86_model <= 10) { 206 if (!cpu_has(c, X86_FEATURE_XMM)) { 207 printk(KERN_INFO "Enabling disabled K7/SSE Support.\n"); 208 rdmsr(MSR_K7_HWCR, l, h); 209 l &= ~0x00008000; 210 wrmsr(MSR_K7_HWCR, l, h); 211 set_cpu_cap(c, X86_FEATURE_XMM); 212 } 213 } 214 215 /* 216 * It's been determined by AMD that Athlons since model 8 stepping 1 217 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 218 * As per AMD technical note 27212 0.2 219 */ 220 if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) { 221 rdmsr(MSR_K7_CLK_CTL, l, h); 222 if ((l & 0xfff00000) != 0x20000000) { 223 printk(KERN_INFO 224 "CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", 225 l, ((l & 0x000fffff)|0x20000000)); 226 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 227 } 228 } 229 230 set_cpu_cap(c, X86_FEATURE_K7); 231 232 amd_k7_smp_check(c); 233 } 234 #endif 235 236 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) 237 static int __cpuinit nearby_node(int apicid) 238 { 239 int i, node; 240 241 for (i = apicid - 1; i >= 0; i--) { 242 node = apicid_to_node[i]; 243 if (node != NUMA_NO_NODE && node_online(node)) 244 return node; 245 } 246 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 247 node = apicid_to_node[i]; 248 if (node != NUMA_NO_NODE && node_online(node)) 249 return node; 250 } 251 return first_node(node_online_map); /* Shouldn't happen */ 252 } 253 #endif 254 255 /* 256 * Fixup core topology information for AMD multi-node processors. 257 * Assumption 1: Number of cores in each internal node is the same. 258 * Assumption 2: Mixed systems with both single-node and dual-node 259 * processors are not supported. 260 */ 261 #ifdef CONFIG_X86_HT 262 static void __cpuinit amd_fixup_dcm(struct cpuinfo_x86 *c) 263 { 264 #ifdef CONFIG_PCI 265 u32 t, cpn; 266 u8 n, n_id; 267 int cpu = smp_processor_id(); 268 269 /* fixup topology information only once for a core */ 270 if (cpu_has(c, X86_FEATURE_AMD_DCM)) 271 return; 272 273 /* check for multi-node processor on boot cpu */ 274 t = read_pci_config(0, 24, 3, 0xe8); 275 if (!(t & (1 << 29))) 276 return; 277 278 set_cpu_cap(c, X86_FEATURE_AMD_DCM); 279 280 /* cores per node: each internal node has half the number of cores */ 281 cpn = c->x86_max_cores >> 1; 282 283 /* even-numbered NB_id of this dual-node processor */ 284 n = c->phys_proc_id << 1; 285 286 /* 287 * determine internal node id and assign cores fifty-fifty to 288 * each node of the dual-node processor 289 */ 290 t = read_pci_config(0, 24 + n, 3, 0xe8); 291 n = (t>>30) & 0x3; 292 if (n == 0) { 293 if (c->cpu_core_id < cpn) 294 n_id = 0; 295 else 296 n_id = 1; 297 } else { 298 if (c->cpu_core_id < cpn) 299 n_id = 1; 300 else 301 n_id = 0; 302 } 303 304 /* compute entire NodeID, use llc_shared_map to store sibling info */ 305 per_cpu(cpu_llc_id, cpu) = (c->phys_proc_id << 1) + n_id; 306 307 /* fixup core id to be in range from 0 to cpn */ 308 c->cpu_core_id = c->cpu_core_id % cpn; 309 #endif 310 } 311 #endif 312 313 /* 314 * On a AMD dual core setup the lower bits of the APIC id distingush the cores. 315 * Assumes number of cores is a power of two. 316 */ 317 static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c) 318 { 319 #ifdef CONFIG_X86_HT 320 unsigned bits; 321 int cpu = smp_processor_id(); 322 323 bits = c->x86_coreid_bits; 324 /* Low order bits define the core id (index of core in socket) */ 325 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); 326 /* Convert the initial APIC ID into the socket ID */ 327 c->phys_proc_id = c->initial_apicid >> bits; 328 /* use socket ID also for last level cache */ 329 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; 330 /* fixup topology information on multi-node processors */ 331 if ((c->x86 == 0x10) && (c->x86_model == 9)) 332 amd_fixup_dcm(c); 333 #endif 334 } 335 336 static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c) 337 { 338 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) 339 int cpu = smp_processor_id(); 340 int node; 341 unsigned apicid = c->apicid; 342 343 node = per_cpu(cpu_llc_id, cpu); 344 345 if (apicid_to_node[apicid] != NUMA_NO_NODE) 346 node = apicid_to_node[apicid]; 347 if (!node_online(node)) { 348 /* Two possibilities here: 349 - The CPU is missing memory and no node was created. 350 In that case try picking one from a nearby CPU 351 - The APIC IDs differ from the HyperTransport node IDs 352 which the K8 northbridge parsing fills in. 353 Assume they are all increased by a constant offset, 354 but in the same order as the HT nodeids. 355 If that doesn't result in a usable node fall back to the 356 path for the previous case. */ 357 358 int ht_nodeid = c->initial_apicid; 359 360 if (ht_nodeid >= 0 && 361 apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 362 node = apicid_to_node[ht_nodeid]; 363 /* Pick a nearby node */ 364 if (!node_online(node)) 365 node = nearby_node(apicid); 366 } 367 numa_set_node(cpu, node); 368 369 printk(KERN_INFO "CPU %d/0x%x -> Node %d\n", cpu, apicid, node); 370 #endif 371 } 372 373 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c) 374 { 375 #ifdef CONFIG_X86_HT 376 unsigned bits, ecx; 377 378 /* Multi core CPU? */ 379 if (c->extended_cpuid_level < 0x80000008) 380 return; 381 382 ecx = cpuid_ecx(0x80000008); 383 384 c->x86_max_cores = (ecx & 0xff) + 1; 385 386 /* CPU telling us the core id bits shift? */ 387 bits = (ecx >> 12) & 0xF; 388 389 /* Otherwise recompute */ 390 if (bits == 0) { 391 while ((1 << bits) < c->x86_max_cores) 392 bits++; 393 } 394 395 c->x86_coreid_bits = bits; 396 #endif 397 } 398 399 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c) 400 { 401 early_init_amd_mc(c); 402 403 /* 404 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 405 * with P/T states and does not stop in deep C-states 406 */ 407 if (c->x86_power & (1 << 8)) { 408 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 409 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 410 } 411 412 #ifdef CONFIG_X86_64 413 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 414 #else 415 /* Set MTRR capability flag if appropriate */ 416 if (c->x86 == 5) 417 if (c->x86_model == 13 || c->x86_model == 9 || 418 (c->x86_model == 8 && c->x86_mask >= 8)) 419 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 420 #endif 421 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 422 /* check CPU config space for extended APIC ID */ 423 if (cpu_has_apic && c->x86 >= 0xf) { 424 unsigned int val; 425 val = read_pci_config(0, 24, 0, 0x68); 426 if ((val & ((1 << 17) | (1 << 18))) == ((1 << 17) | (1 << 18))) 427 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 428 } 429 #endif 430 } 431 432 static void __cpuinit init_amd(struct cpuinfo_x86 *c) 433 { 434 #ifdef CONFIG_SMP 435 unsigned long long value; 436 437 /* 438 * Disable TLB flush filter by setting HWCR.FFDIS on K8 439 * bit 6 of msr C001_0015 440 * 441 * Errata 63 for SH-B3 steppings 442 * Errata 122 for all steppings (F+ have it disabled by default) 443 */ 444 if (c->x86 == 0xf) { 445 rdmsrl(MSR_K7_HWCR, value); 446 value |= 1 << 6; 447 wrmsrl(MSR_K7_HWCR, value); 448 } 449 #endif 450 451 early_init_amd(c); 452 453 /* 454 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 455 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 456 */ 457 clear_cpu_cap(c, 0*32+31); 458 459 #ifdef CONFIG_X86_64 460 /* On C+ stepping K8 rep microcode works well for copy/memset */ 461 if (c->x86 == 0xf) { 462 u32 level; 463 464 level = cpuid_eax(1); 465 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) 466 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 467 468 /* 469 * Some BIOSes incorrectly force this feature, but only K8 470 * revision D (model = 0x14) and later actually support it. 471 * (AMD Erratum #110, docId: 25759). 472 */ 473 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { 474 u64 val; 475 476 clear_cpu_cap(c, X86_FEATURE_LAHF_LM); 477 if (!rdmsrl_amd_safe(0xc001100d, &val)) { 478 val &= ~(1ULL << 32); 479 wrmsrl_amd_safe(0xc001100d, val); 480 } 481 } 482 483 } 484 if (c->x86 == 0x10 || c->x86 == 0x11) 485 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 486 487 /* get apicid instead of initial apic id from cpuid */ 488 c->apicid = hard_smp_processor_id(); 489 #else 490 491 /* 492 * FIXME: We should handle the K5 here. Set up the write 493 * range and also turn on MSR 83 bits 4 and 31 (write alloc, 494 * no bus pipeline) 495 */ 496 497 switch (c->x86) { 498 case 4: 499 init_amd_k5(c); 500 break; 501 case 5: 502 init_amd_k6(c); 503 break; 504 case 6: /* An Athlon/Duron */ 505 init_amd_k7(c); 506 break; 507 } 508 509 /* K6s reports MCEs but don't actually have all the MSRs */ 510 if (c->x86 < 6) 511 clear_cpu_cap(c, X86_FEATURE_MCE); 512 #endif 513 514 /* Enable workaround for FXSAVE leak */ 515 if (c->x86 >= 6) 516 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK); 517 518 if (!c->x86_model_id[0]) { 519 switch (c->x86) { 520 case 0xf: 521 /* Should distinguish Models here, but this is only 522 a fallback anyways. */ 523 strcpy(c->x86_model_id, "Hammer"); 524 break; 525 } 526 } 527 528 display_cacheinfo(c); 529 530 /* Multi core CPU? */ 531 if (c->extended_cpuid_level >= 0x80000008) { 532 amd_detect_cmp(c); 533 srat_detect_node(c); 534 } 535 536 #ifdef CONFIG_X86_32 537 detect_ht(c); 538 #endif 539 540 if (c->extended_cpuid_level >= 0x80000006) { 541 if ((c->x86 >= 0x0f) && (cpuid_edx(0x80000006) & 0xf000)) 542 num_cache_leaves = 4; 543 else 544 num_cache_leaves = 3; 545 } 546 547 if (c->x86 >= 0xf && c->x86 <= 0x11) 548 set_cpu_cap(c, X86_FEATURE_K8); 549 550 if (cpu_has_xmm2) { 551 /* MFENCE stops RDTSC speculation */ 552 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); 553 } 554 555 #ifdef CONFIG_X86_64 556 if (c->x86 == 0x10) { 557 /* do this for boot cpu */ 558 if (c == &boot_cpu_data) 559 check_enable_amd_mmconf_dmi(); 560 561 fam10h_check_enable_mmcfg(); 562 } 563 564 if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) { 565 unsigned long long tseg; 566 567 /* 568 * Split up direct mapping around the TSEG SMM area. 569 * Don't do it for gbpages because there seems very little 570 * benefit in doing so. 571 */ 572 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { 573 printk(KERN_DEBUG "tseg: %010llx\n", tseg); 574 if ((tseg>>PMD_SHIFT) < 575 (max_low_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) || 576 ((tseg>>PMD_SHIFT) < 577 (max_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) && 578 (tseg>>PMD_SHIFT) >= (1ULL<<(32 - PMD_SHIFT)))) 579 set_memory_4k((unsigned long)__va(tseg), 1); 580 } 581 } 582 #endif 583 } 584 585 #ifdef CONFIG_X86_32 586 static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, 587 unsigned int size) 588 { 589 /* AMD errata T13 (order #21922) */ 590 if ((c->x86 == 6)) { 591 /* Duron Rev A0 */ 592 if (c->x86_model == 3 && c->x86_mask == 0) 593 size = 64; 594 /* Tbird rev A1/A2 */ 595 if (c->x86_model == 4 && 596 (c->x86_mask == 0 || c->x86_mask == 1)) 597 size = 256; 598 } 599 return size; 600 } 601 #endif 602 603 static const struct cpu_dev __cpuinitconst amd_cpu_dev = { 604 .c_vendor = "AMD", 605 .c_ident = { "AuthenticAMD" }, 606 #ifdef CONFIG_X86_32 607 .c_models = { 608 { .vendor = X86_VENDOR_AMD, .family = 4, .model_names = 609 { 610 [3] = "486 DX/2", 611 [7] = "486 DX/2-WB", 612 [8] = "486 DX/4", 613 [9] = "486 DX/4-WB", 614 [14] = "Am5x86-WT", 615 [15] = "Am5x86-WB" 616 } 617 }, 618 }, 619 .c_size_cache = amd_size_cache, 620 #endif 621 .c_early_init = early_init_amd, 622 .c_init = init_amd, 623 .c_x86_vendor = X86_VENDOR_AMD, 624 }; 625 626 cpu_dev_register(amd_cpu_dev); 627