1 #include <linux/export.h> 2 #include <linux/init.h> 3 #include <linux/bitops.h> 4 #include <linux/elf.h> 5 #include <linux/mm.h> 6 7 #include <linux/io.h> 8 #include <linux/sched.h> 9 #include <asm/processor.h> 10 #include <asm/apic.h> 11 #include <asm/cpu.h> 12 #include <asm/pci-direct.h> 13 14 #ifdef CONFIG_X86_64 15 # include <asm/numa_64.h> 16 # include <asm/mmconfig.h> 17 # include <asm/cacheflush.h> 18 #endif 19 20 #include "cpu.h" 21 22 #ifdef CONFIG_X86_32 23 /* 24 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 25 * misexecution of code under Linux. Owners of such processors should 26 * contact AMD for precise details and a CPU swap. 27 * 28 * See http://www.multimania.com/poulot/k6bug.html 29 * http://www.amd.com/K6/k6docs/revgd.html 30 * 31 * The following test is erm.. interesting. AMD neglected to up 32 * the chip setting when fixing the bug but they also tweaked some 33 * performance at the same time.. 34 */ 35 36 extern void vide(void); 37 __asm__(".align 4\nvide: ret"); 38 39 static void __cpuinit init_amd_k5(struct cpuinfo_x86 *c) 40 { 41 /* 42 * General Systems BIOSen alias the cpu frequency registers 43 * of the Elan at 0x000df000. Unfortuantly, one of the Linux 44 * drivers subsequently pokes it, and changes the CPU speed. 45 * Workaround : Remove the unneeded alias. 46 */ 47 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 48 #define CBAR_ENB (0x80000000) 49 #define CBAR_KEY (0X000000CB) 50 if (c->x86_model == 9 || c->x86_model == 10) { 51 if (inl(CBAR) & CBAR_ENB) 52 outl(0 | CBAR_KEY, CBAR); 53 } 54 } 55 56 57 static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c) 58 { 59 u32 l, h; 60 int mbytes = num_physpages >> (20-PAGE_SHIFT); 61 62 if (c->x86_model < 6) { 63 /* Based on AMD doc 20734R - June 2000 */ 64 if (c->x86_model == 0) { 65 clear_cpu_cap(c, X86_FEATURE_APIC); 66 set_cpu_cap(c, X86_FEATURE_PGE); 67 } 68 return; 69 } 70 71 if (c->x86_model == 6 && c->x86_mask == 1) { 72 const int K6_BUG_LOOP = 1000000; 73 int n; 74 void (*f_vide)(void); 75 unsigned long d, d2; 76 77 printk(KERN_INFO "AMD K6 stepping B detected - "); 78 79 /* 80 * It looks like AMD fixed the 2.6.2 bug and improved indirect 81 * calls at the same time. 82 */ 83 84 n = K6_BUG_LOOP; 85 f_vide = vide; 86 rdtscl(d); 87 while (n--) 88 f_vide(); 89 rdtscl(d2); 90 d = d2-d; 91 92 if (d > 20*K6_BUG_LOOP) 93 printk(KERN_CONT 94 "system stability may be impaired when more than 32 MB are used.\n"); 95 else 96 printk(KERN_CONT "probably OK (after B9730xxxx).\n"); 97 printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n"); 98 } 99 100 /* K6 with old style WHCR */ 101 if (c->x86_model < 8 || 102 (c->x86_model == 8 && c->x86_mask < 8)) { 103 /* We can only write allocate on the low 508Mb */ 104 if (mbytes > 508) 105 mbytes = 508; 106 107 rdmsr(MSR_K6_WHCR, l, h); 108 if ((l&0x0000FFFF) == 0) { 109 unsigned long flags; 110 l = (1<<0)|((mbytes/4)<<1); 111 local_irq_save(flags); 112 wbinvd(); 113 wrmsr(MSR_K6_WHCR, l, h); 114 local_irq_restore(flags); 115 printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n", 116 mbytes); 117 } 118 return; 119 } 120 121 if ((c->x86_model == 8 && c->x86_mask > 7) || 122 c->x86_model == 9 || c->x86_model == 13) { 123 /* The more serious chips .. */ 124 125 if (mbytes > 4092) 126 mbytes = 4092; 127 128 rdmsr(MSR_K6_WHCR, l, h); 129 if ((l&0xFFFF0000) == 0) { 130 unsigned long flags; 131 l = ((mbytes>>2)<<22)|(1<<16); 132 local_irq_save(flags); 133 wbinvd(); 134 wrmsr(MSR_K6_WHCR, l, h); 135 local_irq_restore(flags); 136 printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n", 137 mbytes); 138 } 139 140 return; 141 } 142 143 if (c->x86_model == 10) { 144 /* AMD Geode LX is model 10 */ 145 /* placeholder for any needed mods */ 146 return; 147 } 148 } 149 150 static void __cpuinit amd_k7_smp_check(struct cpuinfo_x86 *c) 151 { 152 /* calling is from identify_secondary_cpu() ? */ 153 if (!c->cpu_index) 154 return; 155 156 /* 157 * Certain Athlons might work (for various values of 'work') in SMP 158 * but they are not certified as MP capable. 159 */ 160 /* Athlon 660/661 is valid. */ 161 if ((c->x86_model == 6) && ((c->x86_mask == 0) || 162 (c->x86_mask == 1))) 163 goto valid_k7; 164 165 /* Duron 670 is valid */ 166 if ((c->x86_model == 7) && (c->x86_mask == 0)) 167 goto valid_k7; 168 169 /* 170 * Athlon 662, Duron 671, and Athlon >model 7 have capability 171 * bit. It's worth noting that the A5 stepping (662) of some 172 * Athlon XP's have the MP bit set. 173 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for 174 * more. 175 */ 176 if (((c->x86_model == 6) && (c->x86_mask >= 2)) || 177 ((c->x86_model == 7) && (c->x86_mask >= 1)) || 178 (c->x86_model > 7)) 179 if (cpu_has_mp) 180 goto valid_k7; 181 182 /* If we get here, not a certified SMP capable AMD system. */ 183 184 /* 185 * Don't taint if we are running SMP kernel on a single non-MP 186 * approved Athlon 187 */ 188 WARN_ONCE(1, "WARNING: This combination of AMD" 189 " processors is not suitable for SMP.\n"); 190 if (!test_taint(TAINT_UNSAFE_SMP)) 191 add_taint(TAINT_UNSAFE_SMP); 192 193 valid_k7: 194 ; 195 } 196 197 static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c) 198 { 199 u32 l, h; 200 201 /* 202 * Bit 15 of Athlon specific MSR 15, needs to be 0 203 * to enable SSE on Palomino/Morgan/Barton CPU's. 204 * If the BIOS didn't enable it already, enable it here. 205 */ 206 if (c->x86_model >= 6 && c->x86_model <= 10) { 207 if (!cpu_has(c, X86_FEATURE_XMM)) { 208 printk(KERN_INFO "Enabling disabled K7/SSE Support.\n"); 209 rdmsr(MSR_K7_HWCR, l, h); 210 l &= ~0x00008000; 211 wrmsr(MSR_K7_HWCR, l, h); 212 set_cpu_cap(c, X86_FEATURE_XMM); 213 } 214 } 215 216 /* 217 * It's been determined by AMD that Athlons since model 8 stepping 1 218 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 219 * As per AMD technical note 27212 0.2 220 */ 221 if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) { 222 rdmsr(MSR_K7_CLK_CTL, l, h); 223 if ((l & 0xfff00000) != 0x20000000) { 224 printk(KERN_INFO 225 "CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", 226 l, ((l & 0x000fffff)|0x20000000)); 227 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 228 } 229 } 230 231 set_cpu_cap(c, X86_FEATURE_K7); 232 233 amd_k7_smp_check(c); 234 } 235 #endif 236 237 #ifdef CONFIG_NUMA 238 /* 239 * To workaround broken NUMA config. Read the comment in 240 * srat_detect_node(). 241 */ 242 static int __cpuinit nearby_node(int apicid) 243 { 244 int i, node; 245 246 for (i = apicid - 1; i >= 0; i--) { 247 node = __apicid_to_node[i]; 248 if (node != NUMA_NO_NODE && node_online(node)) 249 return node; 250 } 251 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 252 node = __apicid_to_node[i]; 253 if (node != NUMA_NO_NODE && node_online(node)) 254 return node; 255 } 256 return first_node(node_online_map); /* Shouldn't happen */ 257 } 258 #endif 259 260 /* 261 * Fixup core topology information for 262 * (1) AMD multi-node processors 263 * Assumption: Number of cores in each internal node is the same. 264 * (2) AMD processors supporting compute units 265 */ 266 #ifdef CONFIG_X86_HT 267 static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c) 268 { 269 u32 nodes, cores_per_cu = 1; 270 u8 node_id; 271 int cpu = smp_processor_id(); 272 273 /* get information required for multi-node processors */ 274 if (cpu_has(c, X86_FEATURE_TOPOEXT)) { 275 u32 eax, ebx, ecx, edx; 276 277 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); 278 nodes = ((ecx >> 8) & 7) + 1; 279 node_id = ecx & 7; 280 281 /* get compute unit information */ 282 smp_num_siblings = ((ebx >> 8) & 3) + 1; 283 c->compute_unit_id = ebx & 0xff; 284 cores_per_cu += ((ebx >> 8) & 3); 285 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { 286 u64 value; 287 288 rdmsrl(MSR_FAM10H_NODE_ID, value); 289 nodes = ((value >> 3) & 7) + 1; 290 node_id = value & 7; 291 } else 292 return; 293 294 /* fixup multi-node processor information */ 295 if (nodes > 1) { 296 u32 cores_per_node; 297 u32 cus_per_node; 298 299 set_cpu_cap(c, X86_FEATURE_AMD_DCM); 300 cores_per_node = c->x86_max_cores / nodes; 301 cus_per_node = cores_per_node / cores_per_cu; 302 303 /* store NodeID, use llc_shared_map to store sibling info */ 304 per_cpu(cpu_llc_id, cpu) = node_id; 305 306 /* core id has to be in the [0 .. cores_per_node - 1] range */ 307 c->cpu_core_id %= cores_per_node; 308 c->compute_unit_id %= cus_per_node; 309 } 310 } 311 #endif 312 313 /* 314 * On a AMD dual core setup the lower bits of the APIC id distingush the cores. 315 * Assumes number of cores is a power of two. 316 */ 317 static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c) 318 { 319 #ifdef CONFIG_X86_HT 320 unsigned bits; 321 int cpu = smp_processor_id(); 322 323 bits = c->x86_coreid_bits; 324 /* Low order bits define the core id (index of core in socket) */ 325 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); 326 /* Convert the initial APIC ID into the socket ID */ 327 c->phys_proc_id = c->initial_apicid >> bits; 328 /* use socket ID also for last level cache */ 329 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; 330 amd_get_topology(c); 331 #endif 332 } 333 334 int amd_get_nb_id(int cpu) 335 { 336 int id = 0; 337 #ifdef CONFIG_SMP 338 id = per_cpu(cpu_llc_id, cpu); 339 #endif 340 return id; 341 } 342 EXPORT_SYMBOL_GPL(amd_get_nb_id); 343 344 static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c) 345 { 346 #ifdef CONFIG_NUMA 347 int cpu = smp_processor_id(); 348 int node; 349 unsigned apicid = c->apicid; 350 351 node = numa_cpu_node(cpu); 352 if (node == NUMA_NO_NODE) 353 node = per_cpu(cpu_llc_id, cpu); 354 355 /* 356 * If core numbers are inconsistent, it's likely a multi-fabric platform, 357 * so invoke platform-specific handler 358 */ 359 if (c->phys_proc_id != node) 360 x86_cpuinit.fixup_cpu_id(c, node); 361 362 if (!node_online(node)) { 363 /* 364 * Two possibilities here: 365 * 366 * - The CPU is missing memory and no node was created. In 367 * that case try picking one from a nearby CPU. 368 * 369 * - The APIC IDs differ from the HyperTransport node IDs 370 * which the K8 northbridge parsing fills in. Assume 371 * they are all increased by a constant offset, but in 372 * the same order as the HT nodeids. If that doesn't 373 * result in a usable node fall back to the path for the 374 * previous case. 375 * 376 * This workaround operates directly on the mapping between 377 * APIC ID and NUMA node, assuming certain relationship 378 * between APIC ID, HT node ID and NUMA topology. As going 379 * through CPU mapping may alter the outcome, directly 380 * access __apicid_to_node[]. 381 */ 382 int ht_nodeid = c->initial_apicid; 383 384 if (ht_nodeid >= 0 && 385 __apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 386 node = __apicid_to_node[ht_nodeid]; 387 /* Pick a nearby node */ 388 if (!node_online(node)) 389 node = nearby_node(apicid); 390 } 391 numa_set_node(cpu, node); 392 #endif 393 } 394 395 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c) 396 { 397 #ifdef CONFIG_X86_HT 398 unsigned bits, ecx; 399 400 /* Multi core CPU? */ 401 if (c->extended_cpuid_level < 0x80000008) 402 return; 403 404 ecx = cpuid_ecx(0x80000008); 405 406 c->x86_max_cores = (ecx & 0xff) + 1; 407 408 /* CPU telling us the core id bits shift? */ 409 bits = (ecx >> 12) & 0xF; 410 411 /* Otherwise recompute */ 412 if (bits == 0) { 413 while ((1 << bits) < c->x86_max_cores) 414 bits++; 415 } 416 417 c->x86_coreid_bits = bits; 418 #endif 419 } 420 421 static void __cpuinit bsp_init_amd(struct cpuinfo_x86 *c) 422 { 423 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 424 425 if (c->x86 > 0x10 || 426 (c->x86 == 0x10 && c->x86_model >= 0x2)) { 427 u64 val; 428 429 rdmsrl(MSR_K7_HWCR, val); 430 if (!(val & BIT(24))) 431 printk(KERN_WARNING FW_BUG "TSC doesn't count " 432 "with P0 frequency!\n"); 433 } 434 } 435 436 if (c->x86 == 0x15) { 437 unsigned long upperbit; 438 u32 cpuid, assoc; 439 440 cpuid = cpuid_edx(0x80000005); 441 assoc = cpuid >> 16 & 0xff; 442 upperbit = ((cpuid >> 24) << 10) / assoc; 443 444 va_align.mask = (upperbit - 1) & PAGE_MASK; 445 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; 446 } 447 } 448 449 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c) 450 { 451 early_init_amd_mc(c); 452 453 /* 454 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 455 * with P/T states and does not stop in deep C-states 456 */ 457 if (c->x86_power & (1 << 8)) { 458 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 459 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 460 if (!check_tsc_unstable()) 461 sched_clock_stable = 1; 462 } 463 464 #ifdef CONFIG_X86_64 465 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 466 #else 467 /* Set MTRR capability flag if appropriate */ 468 if (c->x86 == 5) 469 if (c->x86_model == 13 || c->x86_model == 9 || 470 (c->x86_model == 8 && c->x86_mask >= 8)) 471 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 472 #endif 473 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 474 /* check CPU config space for extended APIC ID */ 475 if (cpu_has_apic && c->x86 >= 0xf) { 476 unsigned int val; 477 val = read_pci_config(0, 24, 0, 0x68); 478 if ((val & ((1 << 17) | (1 << 18))) == ((1 << 17) | (1 << 18))) 479 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 480 } 481 #endif 482 } 483 484 static void __cpuinit init_amd(struct cpuinfo_x86 *c) 485 { 486 u32 dummy; 487 488 #ifdef CONFIG_SMP 489 unsigned long long value; 490 491 /* 492 * Disable TLB flush filter by setting HWCR.FFDIS on K8 493 * bit 6 of msr C001_0015 494 * 495 * Errata 63 for SH-B3 steppings 496 * Errata 122 for all steppings (F+ have it disabled by default) 497 */ 498 if (c->x86 == 0xf) { 499 rdmsrl(MSR_K7_HWCR, value); 500 value |= 1 << 6; 501 wrmsrl(MSR_K7_HWCR, value); 502 } 503 #endif 504 505 early_init_amd(c); 506 507 /* 508 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 509 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 510 */ 511 clear_cpu_cap(c, 0*32+31); 512 513 #ifdef CONFIG_X86_64 514 /* On C+ stepping K8 rep microcode works well for copy/memset */ 515 if (c->x86 == 0xf) { 516 u32 level; 517 518 level = cpuid_eax(1); 519 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) 520 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 521 522 /* 523 * Some BIOSes incorrectly force this feature, but only K8 524 * revision D (model = 0x14) and later actually support it. 525 * (AMD Erratum #110, docId: 25759). 526 */ 527 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { 528 u64 val; 529 530 clear_cpu_cap(c, X86_FEATURE_LAHF_LM); 531 if (!rdmsrl_amd_safe(0xc001100d, &val)) { 532 val &= ~(1ULL << 32); 533 wrmsrl_amd_safe(0xc001100d, val); 534 } 535 } 536 537 } 538 if (c->x86 >= 0x10) 539 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 540 541 /* get apicid instead of initial apic id from cpuid */ 542 c->apicid = hard_smp_processor_id(); 543 #else 544 545 /* 546 * FIXME: We should handle the K5 here. Set up the write 547 * range and also turn on MSR 83 bits 4 and 31 (write alloc, 548 * no bus pipeline) 549 */ 550 551 switch (c->x86) { 552 case 4: 553 init_amd_k5(c); 554 break; 555 case 5: 556 init_amd_k6(c); 557 break; 558 case 6: /* An Athlon/Duron */ 559 init_amd_k7(c); 560 break; 561 } 562 563 /* K6s reports MCEs but don't actually have all the MSRs */ 564 if (c->x86 < 6) 565 clear_cpu_cap(c, X86_FEATURE_MCE); 566 #endif 567 568 /* Enable workaround for FXSAVE leak */ 569 if (c->x86 >= 6) 570 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK); 571 572 if (!c->x86_model_id[0]) { 573 switch (c->x86) { 574 case 0xf: 575 /* Should distinguish Models here, but this is only 576 a fallback anyways. */ 577 strcpy(c->x86_model_id, "Hammer"); 578 break; 579 } 580 } 581 582 cpu_detect_cache_sizes(c); 583 584 /* Multi core CPU? */ 585 if (c->extended_cpuid_level >= 0x80000008) { 586 amd_detect_cmp(c); 587 srat_detect_node(c); 588 } 589 590 #ifdef CONFIG_X86_32 591 detect_ht(c); 592 #endif 593 594 if (c->extended_cpuid_level >= 0x80000006) { 595 if (cpuid_edx(0x80000006) & 0xf000) 596 num_cache_leaves = 4; 597 else 598 num_cache_leaves = 3; 599 } 600 601 if (c->x86 >= 0xf) 602 set_cpu_cap(c, X86_FEATURE_K8); 603 604 if (cpu_has_xmm2) { 605 /* MFENCE stops RDTSC speculation */ 606 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); 607 } 608 609 #ifdef CONFIG_X86_64 610 if (c->x86 == 0x10) { 611 /* do this for boot cpu */ 612 if (c == &boot_cpu_data) 613 check_enable_amd_mmconf_dmi(); 614 615 fam10h_check_enable_mmcfg(); 616 } 617 618 if (c == &boot_cpu_data && c->x86 >= 0xf) { 619 unsigned long long tseg; 620 621 /* 622 * Split up direct mapping around the TSEG SMM area. 623 * Don't do it for gbpages because there seems very little 624 * benefit in doing so. 625 */ 626 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { 627 printk(KERN_DEBUG "tseg: %010llx\n", tseg); 628 if ((tseg>>PMD_SHIFT) < 629 (max_low_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) || 630 ((tseg>>PMD_SHIFT) < 631 (max_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) && 632 (tseg>>PMD_SHIFT) >= (1ULL<<(32 - PMD_SHIFT)))) 633 set_memory_4k((unsigned long)__va(tseg), 1); 634 } 635 } 636 #endif 637 638 /* 639 * Family 0x12 and above processors have APIC timer 640 * running in deep C states. 641 */ 642 if (c->x86 > 0x11) 643 set_cpu_cap(c, X86_FEATURE_ARAT); 644 645 /* 646 * Disable GART TLB Walk Errors on Fam10h. We do this here 647 * because this is always needed when GART is enabled, even in a 648 * kernel which has no MCE support built in. 649 */ 650 if (c->x86 == 0x10) { 651 /* 652 * BIOS should disable GartTlbWlk Errors themself. If 653 * it doesn't do it here as suggested by the BKDG. 654 * 655 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 656 */ 657 u64 mask; 658 int err; 659 660 err = rdmsrl_safe(MSR_AMD64_MCx_MASK(4), &mask); 661 if (err == 0) { 662 mask |= (1 << 10); 663 checking_wrmsrl(MSR_AMD64_MCx_MASK(4), mask); 664 } 665 } 666 667 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); 668 } 669 670 #ifdef CONFIG_X86_32 671 static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, 672 unsigned int size) 673 { 674 /* AMD errata T13 (order #21922) */ 675 if ((c->x86 == 6)) { 676 /* Duron Rev A0 */ 677 if (c->x86_model == 3 && c->x86_mask == 0) 678 size = 64; 679 /* Tbird rev A1/A2 */ 680 if (c->x86_model == 4 && 681 (c->x86_mask == 0 || c->x86_mask == 1)) 682 size = 256; 683 } 684 return size; 685 } 686 #endif 687 688 static const struct cpu_dev __cpuinitconst amd_cpu_dev = { 689 .c_vendor = "AMD", 690 .c_ident = { "AuthenticAMD" }, 691 #ifdef CONFIG_X86_32 692 .c_models = { 693 { .vendor = X86_VENDOR_AMD, .family = 4, .model_names = 694 { 695 [3] = "486 DX/2", 696 [7] = "486 DX/2-WB", 697 [8] = "486 DX/4", 698 [9] = "486 DX/4-WB", 699 [14] = "Am5x86-WT", 700 [15] = "Am5x86-WB" 701 } 702 }, 703 }, 704 .c_size_cache = amd_size_cache, 705 #endif 706 .c_early_init = early_init_amd, 707 .c_bsp_init = bsp_init_amd, 708 .c_init = init_amd, 709 .c_x86_vendor = X86_VENDOR_AMD, 710 }; 711 712 cpu_dev_register(amd_cpu_dev); 713 714 /* 715 * AMD errata checking 716 * 717 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or 718 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that 719 * have an OSVW id assigned, which it takes as first argument. Both take a 720 * variable number of family-specific model-stepping ranges created by 721 * AMD_MODEL_RANGE(). Each erratum also has to be declared as extern const 722 * int[] in arch/x86/include/asm/processor.h. 723 * 724 * Example: 725 * 726 * const int amd_erratum_319[] = 727 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), 728 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), 729 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); 730 */ 731 732 const int amd_erratum_400[] = 733 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), 734 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); 735 EXPORT_SYMBOL_GPL(amd_erratum_400); 736 737 const int amd_erratum_383[] = 738 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); 739 EXPORT_SYMBOL_GPL(amd_erratum_383); 740 741 bool cpu_has_amd_erratum(const int *erratum) 742 { 743 struct cpuinfo_x86 *cpu = __this_cpu_ptr(&cpu_info); 744 int osvw_id = *erratum++; 745 u32 range; 746 u32 ms; 747 748 /* 749 * If called early enough that current_cpu_data hasn't been initialized 750 * yet, fall back to boot_cpu_data. 751 */ 752 if (cpu->x86 == 0) 753 cpu = &boot_cpu_data; 754 755 if (cpu->x86_vendor != X86_VENDOR_AMD) 756 return false; 757 758 if (osvw_id >= 0 && osvw_id < 65536 && 759 cpu_has(cpu, X86_FEATURE_OSVW)) { 760 u64 osvw_len; 761 762 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); 763 if (osvw_id < osvw_len) { 764 u64 osvw_bits; 765 766 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), 767 osvw_bits); 768 return osvw_bits & (1ULL << (osvw_id & 0x3f)); 769 } 770 } 771 772 /* OSVW unavailable or ID unknown, match family-model-stepping range */ 773 ms = (cpu->x86_model << 4) | cpu->x86_mask; 774 while ((range = *erratum++)) 775 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && 776 (ms >= AMD_MODEL_RANGE_START(range)) && 777 (ms <= AMD_MODEL_RANGE_END(range))) 778 return true; 779 780 return false; 781 } 782 783 EXPORT_SYMBOL_GPL(cpu_has_amd_erratum); 784