1 // SPDX-License-Identifier: GPL-2.0-only 2 #include <linux/export.h> 3 #include <linux/bitops.h> 4 #include <linux/elf.h> 5 #include <linux/mm.h> 6 7 #include <linux/io.h> 8 #include <linux/sched.h> 9 #include <linux/sched/clock.h> 10 #include <linux/random.h> 11 #include <linux/topology.h> 12 #include <asm/processor.h> 13 #include <asm/apic.h> 14 #include <asm/cacheinfo.h> 15 #include <asm/cpu.h> 16 #include <asm/cpu_device_id.h> 17 #include <asm/spec-ctrl.h> 18 #include <asm/smp.h> 19 #include <asm/numa.h> 20 #include <asm/pci-direct.h> 21 #include <asm/delay.h> 22 #include <asm/debugreg.h> 23 #include <asm/resctrl.h> 24 #include <asm/sev.h> 25 26 #ifdef CONFIG_X86_64 27 # include <asm/mmconfig.h> 28 #endif 29 30 #include "cpu.h" 31 32 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) 33 { 34 u32 gprs[8] = { 0 }; 35 int err; 36 37 WARN_ONCE((boot_cpu_data.x86 != 0xf), 38 "%s should only be used on K8!\n", __func__); 39 40 gprs[1] = msr; 41 gprs[7] = 0x9c5a203a; 42 43 err = rdmsr_safe_regs(gprs); 44 45 *p = gprs[0] | ((u64)gprs[2] << 32); 46 47 return err; 48 } 49 50 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) 51 { 52 u32 gprs[8] = { 0 }; 53 54 WARN_ONCE((boot_cpu_data.x86 != 0xf), 55 "%s should only be used on K8!\n", __func__); 56 57 gprs[0] = (u32)val; 58 gprs[1] = msr; 59 gprs[2] = val >> 32; 60 gprs[7] = 0x9c5a203a; 61 62 return wrmsr_safe_regs(gprs); 63 } 64 65 /* 66 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 67 * misexecution of code under Linux. Owners of such processors should 68 * contact AMD for precise details and a CPU swap. 69 * 70 * See http://www.multimania.com/poulot/k6bug.html 71 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" 72 * (Publication # 21266 Issue Date: August 1998) 73 * 74 * The following test is erm.. interesting. AMD neglected to up 75 * the chip setting when fixing the bug but they also tweaked some 76 * performance at the same time.. 77 */ 78 79 #ifdef CONFIG_X86_32 80 extern __visible void vide(void); 81 __asm__(".text\n" 82 ".globl vide\n" 83 ".type vide, @function\n" 84 ".align 4\n" 85 "vide: ret\n"); 86 #endif 87 88 static void init_amd_k5(struct cpuinfo_x86 *c) 89 { 90 #ifdef CONFIG_X86_32 91 /* 92 * General Systems BIOSen alias the cpu frequency registers 93 * of the Elan at 0x000df000. Unfortunately, one of the Linux 94 * drivers subsequently pokes it, and changes the CPU speed. 95 * Workaround : Remove the unneeded alias. 96 */ 97 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 98 #define CBAR_ENB (0x80000000) 99 #define CBAR_KEY (0X000000CB) 100 if (c->x86_model == 9 || c->x86_model == 10) { 101 if (inl(CBAR) & CBAR_ENB) 102 outl(0 | CBAR_KEY, CBAR); 103 } 104 #endif 105 } 106 107 static void init_amd_k6(struct cpuinfo_x86 *c) 108 { 109 #ifdef CONFIG_X86_32 110 u32 l, h; 111 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); 112 113 if (c->x86_model < 6) { 114 /* Based on AMD doc 20734R - June 2000 */ 115 if (c->x86_model == 0) { 116 clear_cpu_cap(c, X86_FEATURE_APIC); 117 set_cpu_cap(c, X86_FEATURE_PGE); 118 } 119 return; 120 } 121 122 if (c->x86_model == 6 && c->x86_stepping == 1) { 123 const int K6_BUG_LOOP = 1000000; 124 int n; 125 void (*f_vide)(void); 126 u64 d, d2; 127 128 pr_info("AMD K6 stepping B detected - "); 129 130 /* 131 * It looks like AMD fixed the 2.6.2 bug and improved indirect 132 * calls at the same time. 133 */ 134 135 n = K6_BUG_LOOP; 136 f_vide = vide; 137 OPTIMIZER_HIDE_VAR(f_vide); 138 d = rdtsc(); 139 while (n--) 140 f_vide(); 141 d2 = rdtsc(); 142 d = d2-d; 143 144 if (d > 20*K6_BUG_LOOP) 145 pr_cont("system stability may be impaired when more than 32 MB are used.\n"); 146 else 147 pr_cont("probably OK (after B9730xxxx).\n"); 148 } 149 150 /* K6 with old style WHCR */ 151 if (c->x86_model < 8 || 152 (c->x86_model == 8 && c->x86_stepping < 8)) { 153 /* We can only write allocate on the low 508Mb */ 154 if (mbytes > 508) 155 mbytes = 508; 156 157 rdmsr(MSR_K6_WHCR, l, h); 158 if ((l&0x0000FFFF) == 0) { 159 unsigned long flags; 160 l = (1<<0)|((mbytes/4)<<1); 161 local_irq_save(flags); 162 wbinvd(); 163 wrmsr(MSR_K6_WHCR, l, h); 164 local_irq_restore(flags); 165 pr_info("Enabling old style K6 write allocation for %d Mb\n", 166 mbytes); 167 } 168 return; 169 } 170 171 if ((c->x86_model == 8 && c->x86_stepping > 7) || 172 c->x86_model == 9 || c->x86_model == 13) { 173 /* The more serious chips .. */ 174 175 if (mbytes > 4092) 176 mbytes = 4092; 177 178 rdmsr(MSR_K6_WHCR, l, h); 179 if ((l&0xFFFF0000) == 0) { 180 unsigned long flags; 181 l = ((mbytes>>2)<<22)|(1<<16); 182 local_irq_save(flags); 183 wbinvd(); 184 wrmsr(MSR_K6_WHCR, l, h); 185 local_irq_restore(flags); 186 pr_info("Enabling new style K6 write allocation for %d Mb\n", 187 mbytes); 188 } 189 190 return; 191 } 192 193 if (c->x86_model == 10) { 194 /* AMD Geode LX is model 10 */ 195 /* placeholder for any needed mods */ 196 return; 197 } 198 #endif 199 } 200 201 static void init_amd_k7(struct cpuinfo_x86 *c) 202 { 203 #ifdef CONFIG_X86_32 204 u32 l, h; 205 206 /* 207 * Bit 15 of Athlon specific MSR 15, needs to be 0 208 * to enable SSE on Palomino/Morgan/Barton CPU's. 209 * If the BIOS didn't enable it already, enable it here. 210 */ 211 if (c->x86_model >= 6 && c->x86_model <= 10) { 212 if (!cpu_has(c, X86_FEATURE_XMM)) { 213 pr_info("Enabling disabled K7/SSE Support.\n"); 214 msr_clear_bit(MSR_K7_HWCR, 15); 215 set_cpu_cap(c, X86_FEATURE_XMM); 216 } 217 } 218 219 /* 220 * It's been determined by AMD that Athlons since model 8 stepping 1 221 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 222 * As per AMD technical note 27212 0.2 223 */ 224 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) { 225 rdmsr(MSR_K7_CLK_CTL, l, h); 226 if ((l & 0xfff00000) != 0x20000000) { 227 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", 228 l, ((l & 0x000fffff)|0x20000000)); 229 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 230 } 231 } 232 233 /* calling is from identify_secondary_cpu() ? */ 234 if (!c->cpu_index) 235 return; 236 237 /* 238 * Certain Athlons might work (for various values of 'work') in SMP 239 * but they are not certified as MP capable. 240 */ 241 /* Athlon 660/661 is valid. */ 242 if ((c->x86_model == 6) && ((c->x86_stepping == 0) || 243 (c->x86_stepping == 1))) 244 return; 245 246 /* Duron 670 is valid */ 247 if ((c->x86_model == 7) && (c->x86_stepping == 0)) 248 return; 249 250 /* 251 * Athlon 662, Duron 671, and Athlon >model 7 have capability 252 * bit. It's worth noting that the A5 stepping (662) of some 253 * Athlon XP's have the MP bit set. 254 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for 255 * more. 256 */ 257 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) || 258 ((c->x86_model == 7) && (c->x86_stepping >= 1)) || 259 (c->x86_model > 7)) 260 if (cpu_has(c, X86_FEATURE_MP)) 261 return; 262 263 /* If we get here, not a certified SMP capable AMD system. */ 264 265 /* 266 * Don't taint if we are running SMP kernel on a single non-MP 267 * approved Athlon 268 */ 269 WARN_ONCE(1, "WARNING: This combination of AMD" 270 " processors is not suitable for SMP.\n"); 271 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 272 #endif 273 } 274 275 #ifdef CONFIG_NUMA 276 /* 277 * To workaround broken NUMA config. Read the comment in 278 * srat_detect_node(). 279 */ 280 static int nearby_node(int apicid) 281 { 282 int i, node; 283 284 for (i = apicid - 1; i >= 0; i--) { 285 node = __apicid_to_node[i]; 286 if (node != NUMA_NO_NODE && node_online(node)) 287 return node; 288 } 289 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 290 node = __apicid_to_node[i]; 291 if (node != NUMA_NO_NODE && node_online(node)) 292 return node; 293 } 294 return first_node(node_online_map); /* Shouldn't happen */ 295 } 296 #endif 297 298 static void srat_detect_node(struct cpuinfo_x86 *c) 299 { 300 #ifdef CONFIG_NUMA 301 int cpu = smp_processor_id(); 302 int node; 303 unsigned apicid = c->topo.apicid; 304 305 node = numa_cpu_node(cpu); 306 if (node == NUMA_NO_NODE) 307 node = per_cpu_llc_id(cpu); 308 309 /* 310 * On multi-fabric platform (e.g. Numascale NumaChip) a 311 * platform-specific handler needs to be called to fixup some 312 * IDs of the CPU. 313 */ 314 if (x86_cpuinit.fixup_cpu_id) 315 x86_cpuinit.fixup_cpu_id(c, node); 316 317 if (!node_online(node)) { 318 /* 319 * Two possibilities here: 320 * 321 * - The CPU is missing memory and no node was created. In 322 * that case try picking one from a nearby CPU. 323 * 324 * - The APIC IDs differ from the HyperTransport node IDs 325 * which the K8 northbridge parsing fills in. Assume 326 * they are all increased by a constant offset, but in 327 * the same order as the HT nodeids. If that doesn't 328 * result in a usable node fall back to the path for the 329 * previous case. 330 * 331 * This workaround operates directly on the mapping between 332 * APIC ID and NUMA node, assuming certain relationship 333 * between APIC ID, HT node ID and NUMA topology. As going 334 * through CPU mapping may alter the outcome, directly 335 * access __apicid_to_node[]. 336 */ 337 int ht_nodeid = c->topo.initial_apicid; 338 339 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 340 node = __apicid_to_node[ht_nodeid]; 341 /* Pick a nearby node */ 342 if (!node_online(node)) 343 node = nearby_node(apicid); 344 } 345 numa_set_node(cpu, node); 346 #endif 347 } 348 349 static void bsp_determine_snp(struct cpuinfo_x86 *c) 350 { 351 #ifdef CONFIG_ARCH_HAS_CC_PLATFORM 352 cc_vendor = CC_VENDOR_AMD; 353 354 if (cpu_has(c, X86_FEATURE_SEV_SNP)) { 355 /* 356 * RMP table entry format is not architectural and is defined by the 357 * per-processor PPR. Restrict SNP support on the known CPU models 358 * for which the RMP table entry format is currently defined or for 359 * processors which support the architecturally defined RMPREAD 360 * instruction. 361 */ 362 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && 363 (cpu_feature_enabled(X86_FEATURE_ZEN3) || 364 cpu_feature_enabled(X86_FEATURE_ZEN4) || 365 cpu_feature_enabled(X86_FEATURE_RMPREAD)) && 366 snp_probe_rmptable_info()) { 367 cc_platform_set(CC_ATTR_HOST_SEV_SNP); 368 } else { 369 setup_clear_cpu_cap(X86_FEATURE_SEV_SNP); 370 cc_platform_clear(CC_ATTR_HOST_SEV_SNP); 371 } 372 } 373 #endif 374 } 375 376 static void bsp_init_amd(struct cpuinfo_x86 *c) 377 { 378 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 379 380 if (c->x86 > 0x10 || 381 (c->x86 == 0x10 && c->x86_model >= 0x2)) { 382 u64 val; 383 384 rdmsrl(MSR_K7_HWCR, val); 385 if (!(val & BIT(24))) 386 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); 387 } 388 } 389 390 if (c->x86 == 0x15) { 391 unsigned long upperbit; 392 u32 cpuid, assoc; 393 394 cpuid = cpuid_edx(0x80000005); 395 assoc = cpuid >> 16 & 0xff; 396 upperbit = ((cpuid >> 24) << 10) / assoc; 397 398 va_align.mask = (upperbit - 1) & PAGE_MASK; 399 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; 400 401 /* A random value per boot for bit slice [12:upper_bit) */ 402 va_align.bits = get_random_u32() & va_align.mask; 403 } 404 405 if (cpu_has(c, X86_FEATURE_MWAITX)) 406 use_mwaitx_delay(); 407 408 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) && 409 !boot_cpu_has(X86_FEATURE_VIRT_SSBD) && 410 c->x86 >= 0x15 && c->x86 <= 0x17) { 411 unsigned int bit; 412 413 switch (c->x86) { 414 case 0x15: bit = 54; break; 415 case 0x16: bit = 33; break; 416 case 0x17: bit = 10; break; 417 default: return; 418 } 419 /* 420 * Try to cache the base value so further operations can 421 * avoid RMW. If that faults, do not enable SSBD. 422 */ 423 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) { 424 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD); 425 setup_force_cpu_cap(X86_FEATURE_SSBD); 426 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit; 427 } 428 } 429 430 resctrl_cpu_detect(c); 431 432 /* Figure out Zen generations: */ 433 switch (c->x86) { 434 case 0x17: 435 switch (c->x86_model) { 436 case 0x00 ... 0x2f: 437 case 0x50 ... 0x5f: 438 setup_force_cpu_cap(X86_FEATURE_ZEN1); 439 break; 440 case 0x30 ... 0x4f: 441 case 0x60 ... 0x7f: 442 case 0x90 ... 0x91: 443 case 0xa0 ... 0xaf: 444 setup_force_cpu_cap(X86_FEATURE_ZEN2); 445 break; 446 default: 447 goto warn; 448 } 449 break; 450 451 case 0x19: 452 switch (c->x86_model) { 453 case 0x00 ... 0x0f: 454 case 0x20 ... 0x5f: 455 setup_force_cpu_cap(X86_FEATURE_ZEN3); 456 break; 457 case 0x10 ... 0x1f: 458 case 0x60 ... 0xaf: 459 setup_force_cpu_cap(X86_FEATURE_ZEN4); 460 break; 461 default: 462 goto warn; 463 } 464 break; 465 466 case 0x1a: 467 switch (c->x86_model) { 468 case 0x00 ... 0x2f: 469 case 0x40 ... 0x4f: 470 case 0x60 ... 0x7f: 471 setup_force_cpu_cap(X86_FEATURE_ZEN5); 472 break; 473 default: 474 goto warn; 475 } 476 break; 477 478 default: 479 break; 480 } 481 482 bsp_determine_snp(c); 483 return; 484 485 warn: 486 WARN_ONCE(1, "Family 0x%x, model: 0x%x??\n", c->x86, c->x86_model); 487 } 488 489 static void early_detect_mem_encrypt(struct cpuinfo_x86 *c) 490 { 491 u64 msr; 492 493 /* 494 * BIOS support is required for SME and SEV. 495 * For SME: If BIOS has enabled SME then adjust x86_phys_bits by 496 * the SME physical address space reduction value. 497 * If BIOS has not enabled SME then don't advertise the 498 * SME feature (set in scattered.c). 499 * If the kernel has not enabled SME via any means then 500 * don't advertise the SME feature. 501 * For SEV: If BIOS has not enabled SEV then don't advertise SEV and 502 * any additional functionality based on it. 503 * 504 * In all cases, since support for SME and SEV requires long mode, 505 * don't advertise the feature under CONFIG_X86_32. 506 */ 507 if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) { 508 /* Check if memory encryption is enabled */ 509 rdmsrl(MSR_AMD64_SYSCFG, msr); 510 if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT)) 511 goto clear_all; 512 513 /* 514 * Always adjust physical address bits. Even though this 515 * will be a value above 32-bits this is still done for 516 * CONFIG_X86_32 so that accurate values are reported. 517 */ 518 c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f; 519 520 if (IS_ENABLED(CONFIG_X86_32)) 521 goto clear_all; 522 523 if (!sme_me_mask) 524 setup_clear_cpu_cap(X86_FEATURE_SME); 525 526 rdmsrl(MSR_K7_HWCR, msr); 527 if (!(msr & MSR_K7_HWCR_SMMLOCK)) 528 goto clear_sev; 529 530 return; 531 532 clear_all: 533 setup_clear_cpu_cap(X86_FEATURE_SME); 534 clear_sev: 535 setup_clear_cpu_cap(X86_FEATURE_SEV); 536 setup_clear_cpu_cap(X86_FEATURE_SEV_ES); 537 setup_clear_cpu_cap(X86_FEATURE_SEV_SNP); 538 } 539 } 540 541 static void early_init_amd(struct cpuinfo_x86 *c) 542 { 543 u32 dummy; 544 545 if (c->x86 >= 0xf) 546 set_cpu_cap(c, X86_FEATURE_K8); 547 548 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); 549 550 /* 551 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 552 * with P/T states and does not stop in deep C-states 553 */ 554 if (c->x86_power & (1 << 8)) { 555 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 556 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 557 } 558 559 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ 560 if (c->x86_power & BIT(12)) 561 set_cpu_cap(c, X86_FEATURE_ACC_POWER); 562 563 /* Bit 14 indicates the Runtime Average Power Limit interface. */ 564 if (c->x86_power & BIT(14)) 565 set_cpu_cap(c, X86_FEATURE_RAPL); 566 567 #ifdef CONFIG_X86_64 568 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 569 #else 570 /* Set MTRR capability flag if appropriate */ 571 if (c->x86 == 5) 572 if (c->x86_model == 13 || c->x86_model == 9 || 573 (c->x86_model == 8 && c->x86_stepping >= 8)) 574 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 575 #endif 576 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 577 /* 578 * ApicID can always be treated as an 8-bit value for AMD APIC versions 579 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we 580 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families 581 * after 16h. 582 */ 583 if (boot_cpu_has(X86_FEATURE_APIC)) { 584 if (c->x86 > 0x16) 585 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 586 else if (c->x86 >= 0xf) { 587 /* check CPU config space for extended APIC ID */ 588 unsigned int val; 589 590 val = read_pci_config(0, 24, 0, 0x68); 591 if ((val >> 17 & 0x3) == 0x3) 592 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 593 } 594 } 595 #endif 596 597 /* 598 * This is only needed to tell the kernel whether to use VMCALL 599 * and VMMCALL. VMMCALL is never executed except under virt, so 600 * we can set it unconditionally. 601 */ 602 set_cpu_cap(c, X86_FEATURE_VMMCALL); 603 604 /* F16h erratum 793, CVE-2013-6885 */ 605 if (c->x86 == 0x16 && c->x86_model <= 0xf) 606 msr_set_bit(MSR_AMD64_LS_CFG, 15); 607 608 early_detect_mem_encrypt(c); 609 610 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && !cpu_has(c, X86_FEATURE_IBPB_BRTYPE)) { 611 if (c->x86 == 0x17 && boot_cpu_has(X86_FEATURE_AMD_IBPB)) 612 setup_force_cpu_cap(X86_FEATURE_IBPB_BRTYPE); 613 else if (c->x86 >= 0x19 && !wrmsrl_safe(MSR_IA32_PRED_CMD, PRED_CMD_SBPB)) { 614 setup_force_cpu_cap(X86_FEATURE_IBPB_BRTYPE); 615 setup_force_cpu_cap(X86_FEATURE_SBPB); 616 } 617 } 618 } 619 620 static void init_amd_k8(struct cpuinfo_x86 *c) 621 { 622 u32 level; 623 u64 value; 624 625 /* On C+ stepping K8 rep microcode works well for copy/memset */ 626 level = cpuid_eax(1); 627 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) 628 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 629 630 /* 631 * Some BIOSes incorrectly force this feature, but only K8 revision D 632 * (model = 0x14) and later actually support it. 633 * (AMD Erratum #110, docId: 25759). 634 */ 635 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { 636 clear_cpu_cap(c, X86_FEATURE_LAHF_LM); 637 if (!rdmsrl_amd_safe(0xc001100d, &value)) { 638 value &= ~BIT_64(32); 639 wrmsrl_amd_safe(0xc001100d, value); 640 } 641 } 642 643 if (!c->x86_model_id[0]) 644 strcpy(c->x86_model_id, "Hammer"); 645 646 #ifdef CONFIG_SMP 647 /* 648 * Disable TLB flush filter by setting HWCR.FFDIS on K8 649 * bit 6 of msr C001_0015 650 * 651 * Errata 63 for SH-B3 steppings 652 * Errata 122 for all steppings (F+ have it disabled by default) 653 */ 654 msr_set_bit(MSR_K7_HWCR, 6); 655 #endif 656 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE); 657 658 /* 659 * Check models and steppings affected by erratum 400. This is 660 * used to select the proper idle routine and to enable the 661 * check whether the machine is affected in arch_post_acpi_subsys_init() 662 * which sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check. 663 */ 664 if (c->x86_model > 0x41 || 665 (c->x86_model == 0x41 && c->x86_stepping >= 0x2)) 666 setup_force_cpu_bug(X86_BUG_AMD_E400); 667 } 668 669 static void init_amd_gh(struct cpuinfo_x86 *c) 670 { 671 #ifdef CONFIG_MMCONF_FAM10H 672 /* do this for boot cpu */ 673 if (c == &boot_cpu_data) 674 check_enable_amd_mmconf_dmi(); 675 676 fam10h_check_enable_mmcfg(); 677 #endif 678 679 /* 680 * Disable GART TLB Walk Errors on Fam10h. We do this here because this 681 * is always needed when GART is enabled, even in a kernel which has no 682 * MCE support built in. BIOS should disable GartTlbWlk Errors already. 683 * If it doesn't, we do it here as suggested by the BKDG. 684 * 685 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 686 */ 687 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10); 688 689 /* 690 * On family 10h BIOS may not have properly enabled WC+ support, causing 691 * it to be converted to CD memtype. This may result in performance 692 * degradation for certain nested-paging guests. Prevent this conversion 693 * by clearing bit 24 in MSR_AMD64_BU_CFG2. 694 * 695 * NOTE: we want to use the _safe accessors so as not to #GP kvm 696 * guests on older kvm hosts. 697 */ 698 msr_clear_bit(MSR_AMD64_BU_CFG2, 24); 699 700 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH); 701 702 /* 703 * Check models and steppings affected by erratum 400. This is 704 * used to select the proper idle routine and to enable the 705 * check whether the machine is affected in arch_post_acpi_subsys_init() 706 * which sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check. 707 */ 708 if (c->x86_model > 0x2 || 709 (c->x86_model == 0x2 && c->x86_stepping >= 0x1)) 710 setup_force_cpu_bug(X86_BUG_AMD_E400); 711 } 712 713 static void init_amd_ln(struct cpuinfo_x86 *c) 714 { 715 /* 716 * Apply erratum 665 fix unconditionally so machines without a BIOS 717 * fix work. 718 */ 719 msr_set_bit(MSR_AMD64_DE_CFG, 31); 720 } 721 722 static bool rdrand_force; 723 724 static int __init rdrand_cmdline(char *str) 725 { 726 if (!str) 727 return -EINVAL; 728 729 if (!strcmp(str, "force")) 730 rdrand_force = true; 731 else 732 return -EINVAL; 733 734 return 0; 735 } 736 early_param("rdrand", rdrand_cmdline); 737 738 static void clear_rdrand_cpuid_bit(struct cpuinfo_x86 *c) 739 { 740 /* 741 * Saving of the MSR used to hide the RDRAND support during 742 * suspend/resume is done by arch/x86/power/cpu.c, which is 743 * dependent on CONFIG_PM_SLEEP. 744 */ 745 if (!IS_ENABLED(CONFIG_PM_SLEEP)) 746 return; 747 748 /* 749 * The self-test can clear X86_FEATURE_RDRAND, so check for 750 * RDRAND support using the CPUID function directly. 751 */ 752 if (!(cpuid_ecx(1) & BIT(30)) || rdrand_force) 753 return; 754 755 msr_clear_bit(MSR_AMD64_CPUID_FN_1, 62); 756 757 /* 758 * Verify that the CPUID change has occurred in case the kernel is 759 * running virtualized and the hypervisor doesn't support the MSR. 760 */ 761 if (cpuid_ecx(1) & BIT(30)) { 762 pr_info_once("BIOS may not properly restore RDRAND after suspend, but hypervisor does not support hiding RDRAND via CPUID.\n"); 763 return; 764 } 765 766 clear_cpu_cap(c, X86_FEATURE_RDRAND); 767 pr_info_once("BIOS may not properly restore RDRAND after suspend, hiding RDRAND via CPUID. Use rdrand=force to reenable.\n"); 768 } 769 770 static void init_amd_jg(struct cpuinfo_x86 *c) 771 { 772 /* 773 * Some BIOS implementations do not restore proper RDRAND support 774 * across suspend and resume. Check on whether to hide the RDRAND 775 * instruction support via CPUID. 776 */ 777 clear_rdrand_cpuid_bit(c); 778 } 779 780 static void init_amd_bd(struct cpuinfo_x86 *c) 781 { 782 u64 value; 783 784 /* 785 * The way access filter has a performance penalty on some workloads. 786 * Disable it on the affected CPUs. 787 */ 788 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) { 789 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) { 790 value |= 0x1E; 791 wrmsrl_safe(MSR_F15H_IC_CFG, value); 792 } 793 } 794 795 /* 796 * Some BIOS implementations do not restore proper RDRAND support 797 * across suspend and resume. Check on whether to hide the RDRAND 798 * instruction support via CPUID. 799 */ 800 clear_rdrand_cpuid_bit(c); 801 } 802 803 static const struct x86_cpu_id erratum_1386_microcode[] = { 804 X86_MATCH_VFM_STEPS(VFM_MAKE(X86_VENDOR_AMD, 0x17, 0x01), 0x2, 0x2, 0x0800126e), 805 X86_MATCH_VFM_STEPS(VFM_MAKE(X86_VENDOR_AMD, 0x17, 0x31), 0x0, 0x0, 0x08301052), 806 }; 807 808 static void fix_erratum_1386(struct cpuinfo_x86 *c) 809 { 810 /* 811 * Work around Erratum 1386. The XSAVES instruction malfunctions in 812 * certain circumstances on Zen1/2 uarch, and not all parts have had 813 * updated microcode at the time of writing (March 2023). 814 * 815 * Affected parts all have no supervisor XSAVE states, meaning that 816 * the XSAVEC instruction (which works fine) is equivalent. 817 * 818 * Clear the feature flag only on microcode revisions which 819 * don't have the fix. 820 */ 821 if (x86_match_min_microcode_rev(erratum_1386_microcode)) 822 return; 823 824 clear_cpu_cap(c, X86_FEATURE_XSAVES); 825 } 826 827 void init_spectral_chicken(struct cpuinfo_x86 *c) 828 { 829 #ifdef CONFIG_MITIGATION_UNRET_ENTRY 830 u64 value; 831 832 /* 833 * On Zen2 we offer this chicken (bit) on the altar of Speculation. 834 * 835 * This suppresses speculation from the middle of a basic block, i.e. it 836 * suppresses non-branch predictions. 837 */ 838 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) { 839 if (!rdmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, &value)) { 840 value |= MSR_ZEN2_SPECTRAL_CHICKEN_BIT; 841 wrmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, value); 842 } 843 } 844 #endif 845 } 846 847 static void init_amd_zen_common(void) 848 { 849 setup_force_cpu_cap(X86_FEATURE_ZEN); 850 #ifdef CONFIG_NUMA 851 node_reclaim_distance = 32; 852 #endif 853 } 854 855 static void init_amd_zen1(struct cpuinfo_x86 *c) 856 { 857 fix_erratum_1386(c); 858 859 /* Fix up CPUID bits, but only if not virtualised. */ 860 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) { 861 862 /* Erratum 1076: CPB feature bit not being set in CPUID. */ 863 if (!cpu_has(c, X86_FEATURE_CPB)) 864 set_cpu_cap(c, X86_FEATURE_CPB); 865 } 866 867 pr_notice_once("AMD Zen1 DIV0 bug detected. Disable SMT for full protection.\n"); 868 setup_force_cpu_bug(X86_BUG_DIV0); 869 } 870 871 static bool cpu_has_zenbleed_microcode(void) 872 { 873 u32 good_rev = 0; 874 875 switch (boot_cpu_data.x86_model) { 876 case 0x30 ... 0x3f: good_rev = 0x0830107b; break; 877 case 0x60 ... 0x67: good_rev = 0x0860010c; break; 878 case 0x68 ... 0x6f: good_rev = 0x08608107; break; 879 case 0x70 ... 0x7f: good_rev = 0x08701033; break; 880 case 0xa0 ... 0xaf: good_rev = 0x08a00009; break; 881 882 default: 883 return false; 884 } 885 886 if (boot_cpu_data.microcode < good_rev) 887 return false; 888 889 return true; 890 } 891 892 static void zen2_zenbleed_check(struct cpuinfo_x86 *c) 893 { 894 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) 895 return; 896 897 if (!cpu_has(c, X86_FEATURE_AVX)) 898 return; 899 900 if (!cpu_has_zenbleed_microcode()) { 901 pr_notice_once("Zenbleed: please update your microcode for the most optimal fix\n"); 902 msr_set_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT); 903 } else { 904 msr_clear_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT); 905 } 906 } 907 908 static void init_amd_zen2(struct cpuinfo_x86 *c) 909 { 910 init_spectral_chicken(c); 911 fix_erratum_1386(c); 912 zen2_zenbleed_check(c); 913 } 914 915 static void init_amd_zen3(struct cpuinfo_x86 *c) 916 { 917 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) { 918 /* 919 * Zen3 (Fam19 model < 0x10) parts are not susceptible to 920 * Branch Type Confusion, but predate the allocation of the 921 * BTC_NO bit. 922 */ 923 if (!cpu_has(c, X86_FEATURE_BTC_NO)) 924 set_cpu_cap(c, X86_FEATURE_BTC_NO); 925 } 926 } 927 928 static void init_amd_zen4(struct cpuinfo_x86 *c) 929 { 930 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) 931 msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT); 932 933 /* 934 * These Zen4 SoCs advertise support for virtualized VMLOAD/VMSAVE 935 * in some BIOS versions but they can lead to random host reboots. 936 */ 937 switch (c->x86_model) { 938 case 0x18 ... 0x1f: 939 case 0x60 ... 0x7f: 940 clear_cpu_cap(c, X86_FEATURE_V_VMSAVE_VMLOAD); 941 break; 942 } 943 } 944 945 static void init_amd_zen5(struct cpuinfo_x86 *c) 946 { 947 } 948 949 static void init_amd(struct cpuinfo_x86 *c) 950 { 951 u64 vm_cr; 952 953 early_init_amd(c); 954 955 /* 956 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 957 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 958 */ 959 clear_cpu_cap(c, 0*32+31); 960 961 if (c->x86 >= 0x10) 962 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 963 964 /* AMD FSRM also implies FSRS */ 965 if (cpu_has(c, X86_FEATURE_FSRM)) 966 set_cpu_cap(c, X86_FEATURE_FSRS); 967 968 /* K6s reports MCEs but don't actually have all the MSRs */ 969 if (c->x86 < 6) 970 clear_cpu_cap(c, X86_FEATURE_MCE); 971 972 switch (c->x86) { 973 case 4: init_amd_k5(c); break; 974 case 5: init_amd_k6(c); break; 975 case 6: init_amd_k7(c); break; 976 case 0xf: init_amd_k8(c); break; 977 case 0x10: init_amd_gh(c); break; 978 case 0x12: init_amd_ln(c); break; 979 case 0x15: init_amd_bd(c); break; 980 case 0x16: init_amd_jg(c); break; 981 } 982 983 /* 984 * Save up on some future enablement work and do common Zen 985 * settings. 986 */ 987 if (c->x86 >= 0x17) 988 init_amd_zen_common(); 989 990 if (boot_cpu_has(X86_FEATURE_ZEN1)) 991 init_amd_zen1(c); 992 else if (boot_cpu_has(X86_FEATURE_ZEN2)) 993 init_amd_zen2(c); 994 else if (boot_cpu_has(X86_FEATURE_ZEN3)) 995 init_amd_zen3(c); 996 else if (boot_cpu_has(X86_FEATURE_ZEN4)) 997 init_amd_zen4(c); 998 else if (boot_cpu_has(X86_FEATURE_ZEN5)) 999 init_amd_zen5(c); 1000 1001 /* 1002 * Enable workaround for FXSAVE leak on CPUs 1003 * without a XSaveErPtr feature 1004 */ 1005 if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR))) 1006 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK); 1007 1008 cpu_detect_cache_sizes(c); 1009 1010 srat_detect_node(c); 1011 1012 init_amd_cacheinfo(c); 1013 1014 if (cpu_has(c, X86_FEATURE_SVM)) { 1015 rdmsrl(MSR_VM_CR, vm_cr); 1016 if (vm_cr & SVM_VM_CR_SVM_DIS_MASK) { 1017 pr_notice_once("SVM disabled (by BIOS) in MSR_VM_CR\n"); 1018 clear_cpu_cap(c, X86_FEATURE_SVM); 1019 } 1020 } 1021 1022 if (!cpu_has(c, X86_FEATURE_LFENCE_RDTSC) && cpu_has(c, X86_FEATURE_XMM2)) { 1023 /* 1024 * Use LFENCE for execution serialization. On families which 1025 * don't have that MSR, LFENCE is already serializing. 1026 * msr_set_bit() uses the safe accessors, too, even if the MSR 1027 * is not present. 1028 */ 1029 msr_set_bit(MSR_AMD64_DE_CFG, 1030 MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT); 1031 1032 /* A serializing LFENCE stops RDTSC speculation */ 1033 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 1034 } 1035 1036 /* 1037 * Family 0x12 and above processors have APIC timer 1038 * running in deep C states. 1039 */ 1040 if (c->x86 > 0x11) 1041 set_cpu_cap(c, X86_FEATURE_ARAT); 1042 1043 /* 3DNow or LM implies PREFETCHW */ 1044 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH)) 1045 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM)) 1046 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH); 1047 1048 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */ 1049 if (!cpu_feature_enabled(X86_FEATURE_XENPV)) 1050 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); 1051 1052 /* 1053 * Turn on the Instructions Retired free counter on machines not 1054 * susceptible to erratum #1054 "Instructions Retired Performance 1055 * Counter May Be Inaccurate". 1056 */ 1057 if (cpu_has(c, X86_FEATURE_IRPERF) && 1058 (boot_cpu_has(X86_FEATURE_ZEN1) && c->x86_model > 0x2f)) 1059 msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT); 1060 1061 check_null_seg_clears_base(c); 1062 1063 /* 1064 * Make sure EFER[AIBRSE - Automatic IBRS Enable] is set. The APs are brought up 1065 * using the trampoline code and as part of it, MSR_EFER gets prepared there in 1066 * order to be replicated onto them. Regardless, set it here again, if not set, 1067 * to protect against any future refactoring/code reorganization which might 1068 * miss setting this important bit. 1069 */ 1070 if (spectre_v2_in_eibrs_mode(spectre_v2_enabled) && 1071 cpu_has(c, X86_FEATURE_AUTOIBRS)) 1072 WARN_ON_ONCE(msr_set_bit(MSR_EFER, _EFER_AUTOIBRS) < 0); 1073 1074 /* AMD CPUs don't need fencing after x2APIC/TSC_DEADLINE MSR writes. */ 1075 clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE); 1076 } 1077 1078 #ifdef CONFIG_X86_32 1079 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) 1080 { 1081 /* AMD errata T13 (order #21922) */ 1082 if (c->x86 == 6) { 1083 /* Duron Rev A0 */ 1084 if (c->x86_model == 3 && c->x86_stepping == 0) 1085 size = 64; 1086 /* Tbird rev A1/A2 */ 1087 if (c->x86_model == 4 && 1088 (c->x86_stepping == 0 || c->x86_stepping == 1)) 1089 size = 256; 1090 } 1091 return size; 1092 } 1093 #endif 1094 1095 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) 1096 { 1097 u32 ebx, eax, ecx, edx; 1098 u16 mask = 0xfff; 1099 1100 if (c->x86 < 0xf) 1101 return; 1102 1103 if (c->extended_cpuid_level < 0x80000006) 1104 return; 1105 1106 cpuid(0x80000006, &eax, &ebx, &ecx, &edx); 1107 1108 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask; 1109 tlb_lli_4k[ENTRIES] = ebx & mask; 1110 1111 /* 1112 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB 1113 * characteristics from the CPUID function 0x80000005 instead. 1114 */ 1115 if (c->x86 == 0xf) { 1116 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 1117 mask = 0xff; 1118 } 1119 1120 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 1121 if (!((eax >> 16) & mask)) 1122 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff; 1123 else 1124 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask; 1125 1126 /* a 4M entry uses two 2M entries */ 1127 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1; 1128 1129 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 1130 if (!(eax & mask)) { 1131 /* Erratum 658 */ 1132 if (c->x86 == 0x15 && c->x86_model <= 0x1f) { 1133 tlb_lli_2m[ENTRIES] = 1024; 1134 } else { 1135 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 1136 tlb_lli_2m[ENTRIES] = eax & 0xff; 1137 } 1138 } else 1139 tlb_lli_2m[ENTRIES] = eax & mask; 1140 1141 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; 1142 } 1143 1144 static const struct cpu_dev amd_cpu_dev = { 1145 .c_vendor = "AMD", 1146 .c_ident = { "AuthenticAMD" }, 1147 #ifdef CONFIG_X86_32 1148 .legacy_models = { 1149 { .family = 4, .model_names = 1150 { 1151 [3] = "486 DX/2", 1152 [7] = "486 DX/2-WB", 1153 [8] = "486 DX/4", 1154 [9] = "486 DX/4-WB", 1155 [14] = "Am5x86-WT", 1156 [15] = "Am5x86-WB" 1157 } 1158 }, 1159 }, 1160 .legacy_cache_size = amd_size_cache, 1161 #endif 1162 .c_early_init = early_init_amd, 1163 .c_detect_tlb = cpu_detect_tlb_amd, 1164 .c_bsp_init = bsp_init_amd, 1165 .c_init = init_amd, 1166 .c_x86_vendor = X86_VENDOR_AMD, 1167 }; 1168 1169 cpu_dev_register(amd_cpu_dev); 1170 1171 static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[4], amd_dr_addr_mask); 1172 1173 static unsigned int amd_msr_dr_addr_masks[] = { 1174 MSR_F16H_DR0_ADDR_MASK, 1175 MSR_F16H_DR1_ADDR_MASK, 1176 MSR_F16H_DR1_ADDR_MASK + 1, 1177 MSR_F16H_DR1_ADDR_MASK + 2 1178 }; 1179 1180 void amd_set_dr_addr_mask(unsigned long mask, unsigned int dr) 1181 { 1182 int cpu = smp_processor_id(); 1183 1184 if (!cpu_feature_enabled(X86_FEATURE_BPEXT)) 1185 return; 1186 1187 if (WARN_ON_ONCE(dr >= ARRAY_SIZE(amd_msr_dr_addr_masks))) 1188 return; 1189 1190 if (per_cpu(amd_dr_addr_mask, cpu)[dr] == mask) 1191 return; 1192 1193 wrmsr(amd_msr_dr_addr_masks[dr], mask, 0); 1194 per_cpu(amd_dr_addr_mask, cpu)[dr] = mask; 1195 } 1196 1197 unsigned long amd_get_dr_addr_mask(unsigned int dr) 1198 { 1199 if (!cpu_feature_enabled(X86_FEATURE_BPEXT)) 1200 return 0; 1201 1202 if (WARN_ON_ONCE(dr >= ARRAY_SIZE(amd_msr_dr_addr_masks))) 1203 return 0; 1204 1205 return per_cpu(amd_dr_addr_mask[dr], smp_processor_id()); 1206 } 1207 EXPORT_SYMBOL_GPL(amd_get_dr_addr_mask); 1208 1209 static void zenbleed_check_cpu(void *unused) 1210 { 1211 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 1212 1213 zen2_zenbleed_check(c); 1214 } 1215 1216 void amd_check_microcode(void) 1217 { 1218 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) 1219 return; 1220 1221 if (cpu_feature_enabled(X86_FEATURE_ZEN2)) 1222 on_each_cpu(zenbleed_check_cpu, NULL, 1); 1223 } 1224