1 // SPDX-License-Identifier: GPL-2.0-only 2 #include <linux/export.h> 3 #include <linux/bitops.h> 4 #include <linux/elf.h> 5 #include <linux/mm.h> 6 7 #include <linux/io.h> 8 #include <linux/sched.h> 9 #include <linux/sched/clock.h> 10 #include <linux/random.h> 11 #include <linux/topology.h> 12 #include <asm/processor.h> 13 #include <asm/apic.h> 14 #include <asm/cacheinfo.h> 15 #include <asm/cpu.h> 16 #include <asm/cpu_device_id.h> 17 #include <asm/spec-ctrl.h> 18 #include <asm/smp.h> 19 #include <asm/numa.h> 20 #include <asm/pci-direct.h> 21 #include <asm/delay.h> 22 #include <asm/debugreg.h> 23 #include <asm/resctrl.h> 24 #include <asm/sev.h> 25 26 #ifdef CONFIG_X86_64 27 # include <asm/mmconfig.h> 28 #endif 29 30 #include "cpu.h" 31 32 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) 33 { 34 u32 gprs[8] = { 0 }; 35 int err; 36 37 WARN_ONCE((boot_cpu_data.x86 != 0xf), 38 "%s should only be used on K8!\n", __func__); 39 40 gprs[1] = msr; 41 gprs[7] = 0x9c5a203a; 42 43 err = rdmsr_safe_regs(gprs); 44 45 *p = gprs[0] | ((u64)gprs[2] << 32); 46 47 return err; 48 } 49 50 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) 51 { 52 u32 gprs[8] = { 0 }; 53 54 WARN_ONCE((boot_cpu_data.x86 != 0xf), 55 "%s should only be used on K8!\n", __func__); 56 57 gprs[0] = (u32)val; 58 gprs[1] = msr; 59 gprs[2] = val >> 32; 60 gprs[7] = 0x9c5a203a; 61 62 return wrmsr_safe_regs(gprs); 63 } 64 65 /* 66 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 67 * misexecution of code under Linux. Owners of such processors should 68 * contact AMD for precise details and a CPU swap. 69 * 70 * See http://www.multimania.com/poulot/k6bug.html 71 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" 72 * (Publication # 21266 Issue Date: August 1998) 73 * 74 * The following test is erm.. interesting. AMD neglected to up 75 * the chip setting when fixing the bug but they also tweaked some 76 * performance at the same time.. 77 */ 78 79 #ifdef CONFIG_X86_32 80 extern __visible void vide(void); 81 __asm__(".text\n" 82 ".globl vide\n" 83 ".type vide, @function\n" 84 ".align 4\n" 85 "vide: ret\n"); 86 #endif 87 88 static void init_amd_k5(struct cpuinfo_x86 *c) 89 { 90 #ifdef CONFIG_X86_32 91 /* 92 * General Systems BIOSen alias the cpu frequency registers 93 * of the Elan at 0x000df000. Unfortunately, one of the Linux 94 * drivers subsequently pokes it, and changes the CPU speed. 95 * Workaround : Remove the unneeded alias. 96 */ 97 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 98 #define CBAR_ENB (0x80000000) 99 #define CBAR_KEY (0X000000CB) 100 if (c->x86_model == 9 || c->x86_model == 10) { 101 if (inl(CBAR) & CBAR_ENB) 102 outl(0 | CBAR_KEY, CBAR); 103 } 104 #endif 105 } 106 107 static void init_amd_k6(struct cpuinfo_x86 *c) 108 { 109 #ifdef CONFIG_X86_32 110 u32 l, h; 111 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); 112 113 if (c->x86_model < 6) { 114 /* Based on AMD doc 20734R - June 2000 */ 115 if (c->x86_model == 0) { 116 clear_cpu_cap(c, X86_FEATURE_APIC); 117 set_cpu_cap(c, X86_FEATURE_PGE); 118 } 119 return; 120 } 121 122 if (c->x86_model == 6 && c->x86_stepping == 1) { 123 const int K6_BUG_LOOP = 1000000; 124 int n; 125 void (*f_vide)(void); 126 u64 d, d2; 127 128 pr_info("AMD K6 stepping B detected - "); 129 130 /* 131 * It looks like AMD fixed the 2.6.2 bug and improved indirect 132 * calls at the same time. 133 */ 134 135 n = K6_BUG_LOOP; 136 f_vide = vide; 137 OPTIMIZER_HIDE_VAR(f_vide); 138 d = rdtsc(); 139 while (n--) 140 f_vide(); 141 d2 = rdtsc(); 142 d = d2-d; 143 144 if (d > 20*K6_BUG_LOOP) 145 pr_cont("system stability may be impaired when more than 32 MB are used.\n"); 146 else 147 pr_cont("probably OK (after B9730xxxx).\n"); 148 } 149 150 /* K6 with old style WHCR */ 151 if (c->x86_model < 8 || 152 (c->x86_model == 8 && c->x86_stepping < 8)) { 153 /* We can only write allocate on the low 508Mb */ 154 if (mbytes > 508) 155 mbytes = 508; 156 157 rdmsr(MSR_K6_WHCR, l, h); 158 if ((l&0x0000FFFF) == 0) { 159 unsigned long flags; 160 l = (1<<0)|((mbytes/4)<<1); 161 local_irq_save(flags); 162 wbinvd(); 163 wrmsr(MSR_K6_WHCR, l, h); 164 local_irq_restore(flags); 165 pr_info("Enabling old style K6 write allocation for %d Mb\n", 166 mbytes); 167 } 168 return; 169 } 170 171 if ((c->x86_model == 8 && c->x86_stepping > 7) || 172 c->x86_model == 9 || c->x86_model == 13) { 173 /* The more serious chips .. */ 174 175 if (mbytes > 4092) 176 mbytes = 4092; 177 178 rdmsr(MSR_K6_WHCR, l, h); 179 if ((l&0xFFFF0000) == 0) { 180 unsigned long flags; 181 l = ((mbytes>>2)<<22)|(1<<16); 182 local_irq_save(flags); 183 wbinvd(); 184 wrmsr(MSR_K6_WHCR, l, h); 185 local_irq_restore(flags); 186 pr_info("Enabling new style K6 write allocation for %d Mb\n", 187 mbytes); 188 } 189 190 return; 191 } 192 193 if (c->x86_model == 10) { 194 /* AMD Geode LX is model 10 */ 195 /* placeholder for any needed mods */ 196 return; 197 } 198 #endif 199 } 200 201 static void init_amd_k7(struct cpuinfo_x86 *c) 202 { 203 #ifdef CONFIG_X86_32 204 u32 l, h; 205 206 /* 207 * Bit 15 of Athlon specific MSR 15, needs to be 0 208 * to enable SSE on Palomino/Morgan/Barton CPU's. 209 * If the BIOS didn't enable it already, enable it here. 210 */ 211 if (c->x86_model >= 6 && c->x86_model <= 10) { 212 if (!cpu_has(c, X86_FEATURE_XMM)) { 213 pr_info("Enabling disabled K7/SSE Support.\n"); 214 msr_clear_bit(MSR_K7_HWCR, 15); 215 set_cpu_cap(c, X86_FEATURE_XMM); 216 } 217 } 218 219 /* 220 * It's been determined by AMD that Athlons since model 8 stepping 1 221 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 222 * As per AMD technical note 27212 0.2 223 */ 224 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) { 225 rdmsr(MSR_K7_CLK_CTL, l, h); 226 if ((l & 0xfff00000) != 0x20000000) { 227 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", 228 l, ((l & 0x000fffff)|0x20000000)); 229 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 230 } 231 } 232 233 /* calling is from identify_secondary_cpu() ? */ 234 if (!c->cpu_index) 235 return; 236 237 /* 238 * Certain Athlons might work (for various values of 'work') in SMP 239 * but they are not certified as MP capable. 240 */ 241 /* Athlon 660/661 is valid. */ 242 if ((c->x86_model == 6) && ((c->x86_stepping == 0) || 243 (c->x86_stepping == 1))) 244 return; 245 246 /* Duron 670 is valid */ 247 if ((c->x86_model == 7) && (c->x86_stepping == 0)) 248 return; 249 250 /* 251 * Athlon 662, Duron 671, and Athlon >model 7 have capability 252 * bit. It's worth noting that the A5 stepping (662) of some 253 * Athlon XP's have the MP bit set. 254 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for 255 * more. 256 */ 257 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) || 258 ((c->x86_model == 7) && (c->x86_stepping >= 1)) || 259 (c->x86_model > 7)) 260 if (cpu_has(c, X86_FEATURE_MP)) 261 return; 262 263 /* If we get here, not a certified SMP capable AMD system. */ 264 265 /* 266 * Don't taint if we are running SMP kernel on a single non-MP 267 * approved Athlon 268 */ 269 WARN_ONCE(1, "WARNING: This combination of AMD" 270 " processors is not suitable for SMP.\n"); 271 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 272 #endif 273 } 274 275 #ifdef CONFIG_NUMA 276 /* 277 * To workaround broken NUMA config. Read the comment in 278 * srat_detect_node(). 279 */ 280 static int nearby_node(int apicid) 281 { 282 int i, node; 283 284 for (i = apicid - 1; i >= 0; i--) { 285 node = __apicid_to_node[i]; 286 if (node != NUMA_NO_NODE && node_online(node)) 287 return node; 288 } 289 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 290 node = __apicid_to_node[i]; 291 if (node != NUMA_NO_NODE && node_online(node)) 292 return node; 293 } 294 return first_node(node_online_map); /* Shouldn't happen */ 295 } 296 #endif 297 298 static void srat_detect_node(struct cpuinfo_x86 *c) 299 { 300 #ifdef CONFIG_NUMA 301 int cpu = smp_processor_id(); 302 int node; 303 unsigned apicid = c->topo.apicid; 304 305 node = numa_cpu_node(cpu); 306 if (node == NUMA_NO_NODE) 307 node = per_cpu_llc_id(cpu); 308 309 /* 310 * On multi-fabric platform (e.g. Numascale NumaChip) a 311 * platform-specific handler needs to be called to fixup some 312 * IDs of the CPU. 313 */ 314 if (x86_cpuinit.fixup_cpu_id) 315 x86_cpuinit.fixup_cpu_id(c, node); 316 317 if (!node_online(node)) { 318 /* 319 * Two possibilities here: 320 * 321 * - The CPU is missing memory and no node was created. In 322 * that case try picking one from a nearby CPU. 323 * 324 * - The APIC IDs differ from the HyperTransport node IDs 325 * which the K8 northbridge parsing fills in. Assume 326 * they are all increased by a constant offset, but in 327 * the same order as the HT nodeids. If that doesn't 328 * result in a usable node fall back to the path for the 329 * previous case. 330 * 331 * This workaround operates directly on the mapping between 332 * APIC ID and NUMA node, assuming certain relationship 333 * between APIC ID, HT node ID and NUMA topology. As going 334 * through CPU mapping may alter the outcome, directly 335 * access __apicid_to_node[]. 336 */ 337 int ht_nodeid = c->topo.initial_apicid; 338 339 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 340 node = __apicid_to_node[ht_nodeid]; 341 /* Pick a nearby node */ 342 if (!node_online(node)) 343 node = nearby_node(apicid); 344 } 345 numa_set_node(cpu, node); 346 #endif 347 } 348 349 static void bsp_determine_snp(struct cpuinfo_x86 *c) 350 { 351 #ifdef CONFIG_ARCH_HAS_CC_PLATFORM 352 cc_vendor = CC_VENDOR_AMD; 353 354 if (cpu_has(c, X86_FEATURE_SEV_SNP)) { 355 /* 356 * RMP table entry format is not architectural and is defined by the 357 * per-processor PPR. Restrict SNP support on the known CPU models 358 * for which the RMP table entry format is currently defined for. 359 */ 360 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && 361 c->x86 >= 0x19 && snp_probe_rmptable_info()) { 362 cc_platform_set(CC_ATTR_HOST_SEV_SNP); 363 } else { 364 setup_clear_cpu_cap(X86_FEATURE_SEV_SNP); 365 cc_platform_clear(CC_ATTR_HOST_SEV_SNP); 366 } 367 } 368 #endif 369 } 370 371 static void bsp_init_amd(struct cpuinfo_x86 *c) 372 { 373 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 374 375 if (c->x86 > 0x10 || 376 (c->x86 == 0x10 && c->x86_model >= 0x2)) { 377 u64 val; 378 379 rdmsrl(MSR_K7_HWCR, val); 380 if (!(val & BIT(24))) 381 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); 382 } 383 } 384 385 if (c->x86 == 0x15) { 386 unsigned long upperbit; 387 u32 cpuid, assoc; 388 389 cpuid = cpuid_edx(0x80000005); 390 assoc = cpuid >> 16 & 0xff; 391 upperbit = ((cpuid >> 24) << 10) / assoc; 392 393 va_align.mask = (upperbit - 1) & PAGE_MASK; 394 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; 395 396 /* A random value per boot for bit slice [12:upper_bit) */ 397 va_align.bits = get_random_u32() & va_align.mask; 398 } 399 400 if (cpu_has(c, X86_FEATURE_MWAITX)) 401 use_mwaitx_delay(); 402 403 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) && 404 !boot_cpu_has(X86_FEATURE_VIRT_SSBD) && 405 c->x86 >= 0x15 && c->x86 <= 0x17) { 406 unsigned int bit; 407 408 switch (c->x86) { 409 case 0x15: bit = 54; break; 410 case 0x16: bit = 33; break; 411 case 0x17: bit = 10; break; 412 default: return; 413 } 414 /* 415 * Try to cache the base value so further operations can 416 * avoid RMW. If that faults, do not enable SSBD. 417 */ 418 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) { 419 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD); 420 setup_force_cpu_cap(X86_FEATURE_SSBD); 421 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit; 422 } 423 } 424 425 resctrl_cpu_detect(c); 426 427 /* Figure out Zen generations: */ 428 switch (c->x86) { 429 case 0x17: 430 switch (c->x86_model) { 431 case 0x00 ... 0x2f: 432 case 0x50 ... 0x5f: 433 setup_force_cpu_cap(X86_FEATURE_ZEN1); 434 break; 435 case 0x30 ... 0x4f: 436 case 0x60 ... 0x7f: 437 case 0x90 ... 0x91: 438 case 0xa0 ... 0xaf: 439 setup_force_cpu_cap(X86_FEATURE_ZEN2); 440 break; 441 default: 442 goto warn; 443 } 444 break; 445 446 case 0x19: 447 switch (c->x86_model) { 448 case 0x00 ... 0x0f: 449 case 0x20 ... 0x5f: 450 setup_force_cpu_cap(X86_FEATURE_ZEN3); 451 break; 452 case 0x10 ... 0x1f: 453 case 0x60 ... 0xaf: 454 setup_force_cpu_cap(X86_FEATURE_ZEN4); 455 break; 456 default: 457 goto warn; 458 } 459 break; 460 461 case 0x1a: 462 switch (c->x86_model) { 463 case 0x00 ... 0x2f: 464 case 0x40 ... 0x4f: 465 case 0x60 ... 0x7f: 466 setup_force_cpu_cap(X86_FEATURE_ZEN5); 467 break; 468 default: 469 goto warn; 470 } 471 break; 472 473 default: 474 break; 475 } 476 477 bsp_determine_snp(c); 478 return; 479 480 warn: 481 WARN_ONCE(1, "Family 0x%x, model: 0x%x??\n", c->x86, c->x86_model); 482 } 483 484 static void early_detect_mem_encrypt(struct cpuinfo_x86 *c) 485 { 486 u64 msr; 487 488 /* 489 * BIOS support is required for SME and SEV. 490 * For SME: If BIOS has enabled SME then adjust x86_phys_bits by 491 * the SME physical address space reduction value. 492 * If BIOS has not enabled SME then don't advertise the 493 * SME feature (set in scattered.c). 494 * If the kernel has not enabled SME via any means then 495 * don't advertise the SME feature. 496 * For SEV: If BIOS has not enabled SEV then don't advertise SEV and 497 * any additional functionality based on it. 498 * 499 * In all cases, since support for SME and SEV requires long mode, 500 * don't advertise the feature under CONFIG_X86_32. 501 */ 502 if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) { 503 /* Check if memory encryption is enabled */ 504 rdmsrl(MSR_AMD64_SYSCFG, msr); 505 if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT)) 506 goto clear_all; 507 508 /* 509 * Always adjust physical address bits. Even though this 510 * will be a value above 32-bits this is still done for 511 * CONFIG_X86_32 so that accurate values are reported. 512 */ 513 c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f; 514 515 if (IS_ENABLED(CONFIG_X86_32)) 516 goto clear_all; 517 518 if (!sme_me_mask) 519 setup_clear_cpu_cap(X86_FEATURE_SME); 520 521 rdmsrl(MSR_K7_HWCR, msr); 522 if (!(msr & MSR_K7_HWCR_SMMLOCK)) 523 goto clear_sev; 524 525 return; 526 527 clear_all: 528 setup_clear_cpu_cap(X86_FEATURE_SME); 529 clear_sev: 530 setup_clear_cpu_cap(X86_FEATURE_SEV); 531 setup_clear_cpu_cap(X86_FEATURE_SEV_ES); 532 setup_clear_cpu_cap(X86_FEATURE_SEV_SNP); 533 } 534 } 535 536 static void early_init_amd(struct cpuinfo_x86 *c) 537 { 538 u32 dummy; 539 540 if (c->x86 >= 0xf) 541 set_cpu_cap(c, X86_FEATURE_K8); 542 543 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); 544 545 /* 546 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 547 * with P/T states and does not stop in deep C-states 548 */ 549 if (c->x86_power & (1 << 8)) { 550 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 551 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 552 } 553 554 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ 555 if (c->x86_power & BIT(12)) 556 set_cpu_cap(c, X86_FEATURE_ACC_POWER); 557 558 /* Bit 14 indicates the Runtime Average Power Limit interface. */ 559 if (c->x86_power & BIT(14)) 560 set_cpu_cap(c, X86_FEATURE_RAPL); 561 562 #ifdef CONFIG_X86_64 563 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 564 #else 565 /* Set MTRR capability flag if appropriate */ 566 if (c->x86 == 5) 567 if (c->x86_model == 13 || c->x86_model == 9 || 568 (c->x86_model == 8 && c->x86_stepping >= 8)) 569 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 570 #endif 571 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 572 /* 573 * ApicID can always be treated as an 8-bit value for AMD APIC versions 574 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we 575 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families 576 * after 16h. 577 */ 578 if (boot_cpu_has(X86_FEATURE_APIC)) { 579 if (c->x86 > 0x16) 580 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 581 else if (c->x86 >= 0xf) { 582 /* check CPU config space for extended APIC ID */ 583 unsigned int val; 584 585 val = read_pci_config(0, 24, 0, 0x68); 586 if ((val >> 17 & 0x3) == 0x3) 587 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 588 } 589 } 590 #endif 591 592 /* 593 * This is only needed to tell the kernel whether to use VMCALL 594 * and VMMCALL. VMMCALL is never executed except under virt, so 595 * we can set it unconditionally. 596 */ 597 set_cpu_cap(c, X86_FEATURE_VMMCALL); 598 599 /* F16h erratum 793, CVE-2013-6885 */ 600 if (c->x86 == 0x16 && c->x86_model <= 0xf) 601 msr_set_bit(MSR_AMD64_LS_CFG, 15); 602 603 early_detect_mem_encrypt(c); 604 605 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && !cpu_has(c, X86_FEATURE_IBPB_BRTYPE)) { 606 if (c->x86 == 0x17 && boot_cpu_has(X86_FEATURE_AMD_IBPB)) 607 setup_force_cpu_cap(X86_FEATURE_IBPB_BRTYPE); 608 else if (c->x86 >= 0x19 && !wrmsrl_safe(MSR_IA32_PRED_CMD, PRED_CMD_SBPB)) { 609 setup_force_cpu_cap(X86_FEATURE_IBPB_BRTYPE); 610 setup_force_cpu_cap(X86_FEATURE_SBPB); 611 } 612 } 613 } 614 615 static void init_amd_k8(struct cpuinfo_x86 *c) 616 { 617 u32 level; 618 u64 value; 619 620 /* On C+ stepping K8 rep microcode works well for copy/memset */ 621 level = cpuid_eax(1); 622 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) 623 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 624 625 /* 626 * Some BIOSes incorrectly force this feature, but only K8 revision D 627 * (model = 0x14) and later actually support it. 628 * (AMD Erratum #110, docId: 25759). 629 */ 630 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { 631 clear_cpu_cap(c, X86_FEATURE_LAHF_LM); 632 if (!rdmsrl_amd_safe(0xc001100d, &value)) { 633 value &= ~BIT_64(32); 634 wrmsrl_amd_safe(0xc001100d, value); 635 } 636 } 637 638 if (!c->x86_model_id[0]) 639 strcpy(c->x86_model_id, "Hammer"); 640 641 #ifdef CONFIG_SMP 642 /* 643 * Disable TLB flush filter by setting HWCR.FFDIS on K8 644 * bit 6 of msr C001_0015 645 * 646 * Errata 63 for SH-B3 steppings 647 * Errata 122 for all steppings (F+ have it disabled by default) 648 */ 649 msr_set_bit(MSR_K7_HWCR, 6); 650 #endif 651 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE); 652 653 /* 654 * Check models and steppings affected by erratum 400. This is 655 * used to select the proper idle routine and to enable the 656 * check whether the machine is affected in arch_post_acpi_subsys_init() 657 * which sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check. 658 */ 659 if (c->x86_model > 0x41 || 660 (c->x86_model == 0x41 && c->x86_stepping >= 0x2)) 661 setup_force_cpu_bug(X86_BUG_AMD_E400); 662 } 663 664 static void init_amd_gh(struct cpuinfo_x86 *c) 665 { 666 #ifdef CONFIG_MMCONF_FAM10H 667 /* do this for boot cpu */ 668 if (c == &boot_cpu_data) 669 check_enable_amd_mmconf_dmi(); 670 671 fam10h_check_enable_mmcfg(); 672 #endif 673 674 /* 675 * Disable GART TLB Walk Errors on Fam10h. We do this here because this 676 * is always needed when GART is enabled, even in a kernel which has no 677 * MCE support built in. BIOS should disable GartTlbWlk Errors already. 678 * If it doesn't, we do it here as suggested by the BKDG. 679 * 680 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 681 */ 682 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10); 683 684 /* 685 * On family 10h BIOS may not have properly enabled WC+ support, causing 686 * it to be converted to CD memtype. This may result in performance 687 * degradation for certain nested-paging guests. Prevent this conversion 688 * by clearing bit 24 in MSR_AMD64_BU_CFG2. 689 * 690 * NOTE: we want to use the _safe accessors so as not to #GP kvm 691 * guests on older kvm hosts. 692 */ 693 msr_clear_bit(MSR_AMD64_BU_CFG2, 24); 694 695 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH); 696 697 /* 698 * Check models and steppings affected by erratum 400. This is 699 * used to select the proper idle routine and to enable the 700 * check whether the machine is affected in arch_post_acpi_subsys_init() 701 * which sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check. 702 */ 703 if (c->x86_model > 0x2 || 704 (c->x86_model == 0x2 && c->x86_stepping >= 0x1)) 705 setup_force_cpu_bug(X86_BUG_AMD_E400); 706 } 707 708 static void init_amd_ln(struct cpuinfo_x86 *c) 709 { 710 /* 711 * Apply erratum 665 fix unconditionally so machines without a BIOS 712 * fix work. 713 */ 714 msr_set_bit(MSR_AMD64_DE_CFG, 31); 715 } 716 717 static bool rdrand_force; 718 719 static int __init rdrand_cmdline(char *str) 720 { 721 if (!str) 722 return -EINVAL; 723 724 if (!strcmp(str, "force")) 725 rdrand_force = true; 726 else 727 return -EINVAL; 728 729 return 0; 730 } 731 early_param("rdrand", rdrand_cmdline); 732 733 static void clear_rdrand_cpuid_bit(struct cpuinfo_x86 *c) 734 { 735 /* 736 * Saving of the MSR used to hide the RDRAND support during 737 * suspend/resume is done by arch/x86/power/cpu.c, which is 738 * dependent on CONFIG_PM_SLEEP. 739 */ 740 if (!IS_ENABLED(CONFIG_PM_SLEEP)) 741 return; 742 743 /* 744 * The self-test can clear X86_FEATURE_RDRAND, so check for 745 * RDRAND support using the CPUID function directly. 746 */ 747 if (!(cpuid_ecx(1) & BIT(30)) || rdrand_force) 748 return; 749 750 msr_clear_bit(MSR_AMD64_CPUID_FN_1, 62); 751 752 /* 753 * Verify that the CPUID change has occurred in case the kernel is 754 * running virtualized and the hypervisor doesn't support the MSR. 755 */ 756 if (cpuid_ecx(1) & BIT(30)) { 757 pr_info_once("BIOS may not properly restore RDRAND after suspend, but hypervisor does not support hiding RDRAND via CPUID.\n"); 758 return; 759 } 760 761 clear_cpu_cap(c, X86_FEATURE_RDRAND); 762 pr_info_once("BIOS may not properly restore RDRAND after suspend, hiding RDRAND via CPUID. Use rdrand=force to reenable.\n"); 763 } 764 765 static void init_amd_jg(struct cpuinfo_x86 *c) 766 { 767 /* 768 * Some BIOS implementations do not restore proper RDRAND support 769 * across suspend and resume. Check on whether to hide the RDRAND 770 * instruction support via CPUID. 771 */ 772 clear_rdrand_cpuid_bit(c); 773 } 774 775 static void init_amd_bd(struct cpuinfo_x86 *c) 776 { 777 u64 value; 778 779 /* 780 * The way access filter has a performance penalty on some workloads. 781 * Disable it on the affected CPUs. 782 */ 783 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) { 784 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) { 785 value |= 0x1E; 786 wrmsrl_safe(MSR_F15H_IC_CFG, value); 787 } 788 } 789 790 /* 791 * Some BIOS implementations do not restore proper RDRAND support 792 * across suspend and resume. Check on whether to hide the RDRAND 793 * instruction support via CPUID. 794 */ 795 clear_rdrand_cpuid_bit(c); 796 } 797 798 static const struct x86_cpu_desc erratum_1386_microcode[] = { 799 AMD_CPU_DESC(0x17, 0x1, 0x2, 0x0800126e), 800 AMD_CPU_DESC(0x17, 0x31, 0x0, 0x08301052), 801 {}, 802 }; 803 804 static void fix_erratum_1386(struct cpuinfo_x86 *c) 805 { 806 /* 807 * Work around Erratum 1386. The XSAVES instruction malfunctions in 808 * certain circumstances on Zen1/2 uarch, and not all parts have had 809 * updated microcode at the time of writing (March 2023). 810 * 811 * Affected parts all have no supervisor XSAVE states, meaning that 812 * the XSAVEC instruction (which works fine) is equivalent. 813 * 814 * Clear the feature flag only on microcode revisions which 815 * don't have the fix. 816 */ 817 if (x86_cpu_has_min_microcode_rev(erratum_1386_microcode)) 818 return; 819 820 clear_cpu_cap(c, X86_FEATURE_XSAVES); 821 } 822 823 void init_spectral_chicken(struct cpuinfo_x86 *c) 824 { 825 #ifdef CONFIG_MITIGATION_UNRET_ENTRY 826 u64 value; 827 828 /* 829 * On Zen2 we offer this chicken (bit) on the altar of Speculation. 830 * 831 * This suppresses speculation from the middle of a basic block, i.e. it 832 * suppresses non-branch predictions. 833 */ 834 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) { 835 if (!rdmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, &value)) { 836 value |= MSR_ZEN2_SPECTRAL_CHICKEN_BIT; 837 wrmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, value); 838 } 839 } 840 #endif 841 } 842 843 static void init_amd_zen_common(void) 844 { 845 setup_force_cpu_cap(X86_FEATURE_ZEN); 846 #ifdef CONFIG_NUMA 847 node_reclaim_distance = 32; 848 #endif 849 } 850 851 static void init_amd_zen1(struct cpuinfo_x86 *c) 852 { 853 fix_erratum_1386(c); 854 855 /* Fix up CPUID bits, but only if not virtualised. */ 856 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) { 857 858 /* Erratum 1076: CPB feature bit not being set in CPUID. */ 859 if (!cpu_has(c, X86_FEATURE_CPB)) 860 set_cpu_cap(c, X86_FEATURE_CPB); 861 } 862 863 pr_notice_once("AMD Zen1 DIV0 bug detected. Disable SMT for full protection.\n"); 864 setup_force_cpu_bug(X86_BUG_DIV0); 865 } 866 867 static bool cpu_has_zenbleed_microcode(void) 868 { 869 u32 good_rev = 0; 870 871 switch (boot_cpu_data.x86_model) { 872 case 0x30 ... 0x3f: good_rev = 0x0830107b; break; 873 case 0x60 ... 0x67: good_rev = 0x0860010c; break; 874 case 0x68 ... 0x6f: good_rev = 0x08608107; break; 875 case 0x70 ... 0x7f: good_rev = 0x08701033; break; 876 case 0xa0 ... 0xaf: good_rev = 0x08a00009; break; 877 878 default: 879 return false; 880 } 881 882 if (boot_cpu_data.microcode < good_rev) 883 return false; 884 885 return true; 886 } 887 888 static void zen2_zenbleed_check(struct cpuinfo_x86 *c) 889 { 890 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) 891 return; 892 893 if (!cpu_has(c, X86_FEATURE_AVX)) 894 return; 895 896 if (!cpu_has_zenbleed_microcode()) { 897 pr_notice_once("Zenbleed: please update your microcode for the most optimal fix\n"); 898 msr_set_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT); 899 } else { 900 msr_clear_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT); 901 } 902 } 903 904 static void init_amd_zen2(struct cpuinfo_x86 *c) 905 { 906 init_spectral_chicken(c); 907 fix_erratum_1386(c); 908 zen2_zenbleed_check(c); 909 } 910 911 static void init_amd_zen3(struct cpuinfo_x86 *c) 912 { 913 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) { 914 /* 915 * Zen3 (Fam19 model < 0x10) parts are not susceptible to 916 * Branch Type Confusion, but predate the allocation of the 917 * BTC_NO bit. 918 */ 919 if (!cpu_has(c, X86_FEATURE_BTC_NO)) 920 set_cpu_cap(c, X86_FEATURE_BTC_NO); 921 } 922 } 923 924 static void init_amd_zen4(struct cpuinfo_x86 *c) 925 { 926 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) 927 msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT); 928 929 /* 930 * These Zen4 SoCs advertise support for virtualized VMLOAD/VMSAVE 931 * in some BIOS versions but they can lead to random host reboots. 932 */ 933 switch (c->x86_model) { 934 case 0x18 ... 0x1f: 935 case 0x60 ... 0x7f: 936 clear_cpu_cap(c, X86_FEATURE_V_VMSAVE_VMLOAD); 937 break; 938 } 939 } 940 941 static void init_amd_zen5(struct cpuinfo_x86 *c) 942 { 943 } 944 945 static void init_amd(struct cpuinfo_x86 *c) 946 { 947 u64 vm_cr; 948 949 early_init_amd(c); 950 951 /* 952 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 953 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 954 */ 955 clear_cpu_cap(c, 0*32+31); 956 957 if (c->x86 >= 0x10) 958 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 959 960 /* AMD FSRM also implies FSRS */ 961 if (cpu_has(c, X86_FEATURE_FSRM)) 962 set_cpu_cap(c, X86_FEATURE_FSRS); 963 964 /* K6s reports MCEs but don't actually have all the MSRs */ 965 if (c->x86 < 6) 966 clear_cpu_cap(c, X86_FEATURE_MCE); 967 968 switch (c->x86) { 969 case 4: init_amd_k5(c); break; 970 case 5: init_amd_k6(c); break; 971 case 6: init_amd_k7(c); break; 972 case 0xf: init_amd_k8(c); break; 973 case 0x10: init_amd_gh(c); break; 974 case 0x12: init_amd_ln(c); break; 975 case 0x15: init_amd_bd(c); break; 976 case 0x16: init_amd_jg(c); break; 977 } 978 979 /* 980 * Save up on some future enablement work and do common Zen 981 * settings. 982 */ 983 if (c->x86 >= 0x17) 984 init_amd_zen_common(); 985 986 if (boot_cpu_has(X86_FEATURE_ZEN1)) 987 init_amd_zen1(c); 988 else if (boot_cpu_has(X86_FEATURE_ZEN2)) 989 init_amd_zen2(c); 990 else if (boot_cpu_has(X86_FEATURE_ZEN3)) 991 init_amd_zen3(c); 992 else if (boot_cpu_has(X86_FEATURE_ZEN4)) 993 init_amd_zen4(c); 994 else if (boot_cpu_has(X86_FEATURE_ZEN5)) 995 init_amd_zen5(c); 996 997 /* 998 * Enable workaround for FXSAVE leak on CPUs 999 * without a XSaveErPtr feature 1000 */ 1001 if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR))) 1002 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK); 1003 1004 cpu_detect_cache_sizes(c); 1005 1006 srat_detect_node(c); 1007 1008 init_amd_cacheinfo(c); 1009 1010 if (cpu_has(c, X86_FEATURE_SVM)) { 1011 rdmsrl(MSR_VM_CR, vm_cr); 1012 if (vm_cr & SVM_VM_CR_SVM_DIS_MASK) { 1013 pr_notice_once("SVM disabled (by BIOS) in MSR_VM_CR\n"); 1014 clear_cpu_cap(c, X86_FEATURE_SVM); 1015 } 1016 } 1017 1018 if (!cpu_has(c, X86_FEATURE_LFENCE_RDTSC) && cpu_has(c, X86_FEATURE_XMM2)) { 1019 /* 1020 * Use LFENCE for execution serialization. On families which 1021 * don't have that MSR, LFENCE is already serializing. 1022 * msr_set_bit() uses the safe accessors, too, even if the MSR 1023 * is not present. 1024 */ 1025 msr_set_bit(MSR_AMD64_DE_CFG, 1026 MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT); 1027 1028 /* A serializing LFENCE stops RDTSC speculation */ 1029 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 1030 } 1031 1032 /* 1033 * Family 0x12 and above processors have APIC timer 1034 * running in deep C states. 1035 */ 1036 if (c->x86 > 0x11) 1037 set_cpu_cap(c, X86_FEATURE_ARAT); 1038 1039 /* 3DNow or LM implies PREFETCHW */ 1040 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH)) 1041 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM)) 1042 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH); 1043 1044 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */ 1045 if (!cpu_feature_enabled(X86_FEATURE_XENPV)) 1046 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); 1047 1048 /* 1049 * Turn on the Instructions Retired free counter on machines not 1050 * susceptible to erratum #1054 "Instructions Retired Performance 1051 * Counter May Be Inaccurate". 1052 */ 1053 if (cpu_has(c, X86_FEATURE_IRPERF) && 1054 (boot_cpu_has(X86_FEATURE_ZEN1) && c->x86_model > 0x2f)) 1055 msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT); 1056 1057 check_null_seg_clears_base(c); 1058 1059 /* 1060 * Make sure EFER[AIBRSE - Automatic IBRS Enable] is set. The APs are brought up 1061 * using the trampoline code and as part of it, MSR_EFER gets prepared there in 1062 * order to be replicated onto them. Regardless, set it here again, if not set, 1063 * to protect against any future refactoring/code reorganization which might 1064 * miss setting this important bit. 1065 */ 1066 if (spectre_v2_in_eibrs_mode(spectre_v2_enabled) && 1067 cpu_has(c, X86_FEATURE_AUTOIBRS)) 1068 WARN_ON_ONCE(msr_set_bit(MSR_EFER, _EFER_AUTOIBRS)); 1069 1070 /* AMD CPUs don't need fencing after x2APIC/TSC_DEADLINE MSR writes. */ 1071 clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE); 1072 } 1073 1074 #ifdef CONFIG_X86_32 1075 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) 1076 { 1077 /* AMD errata T13 (order #21922) */ 1078 if (c->x86 == 6) { 1079 /* Duron Rev A0 */ 1080 if (c->x86_model == 3 && c->x86_stepping == 0) 1081 size = 64; 1082 /* Tbird rev A1/A2 */ 1083 if (c->x86_model == 4 && 1084 (c->x86_stepping == 0 || c->x86_stepping == 1)) 1085 size = 256; 1086 } 1087 return size; 1088 } 1089 #endif 1090 1091 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) 1092 { 1093 u32 ebx, eax, ecx, edx; 1094 u16 mask = 0xfff; 1095 1096 if (c->x86 < 0xf) 1097 return; 1098 1099 if (c->extended_cpuid_level < 0x80000006) 1100 return; 1101 1102 cpuid(0x80000006, &eax, &ebx, &ecx, &edx); 1103 1104 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask; 1105 tlb_lli_4k[ENTRIES] = ebx & mask; 1106 1107 /* 1108 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB 1109 * characteristics from the CPUID function 0x80000005 instead. 1110 */ 1111 if (c->x86 == 0xf) { 1112 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 1113 mask = 0xff; 1114 } 1115 1116 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 1117 if (!((eax >> 16) & mask)) 1118 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff; 1119 else 1120 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask; 1121 1122 /* a 4M entry uses two 2M entries */ 1123 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1; 1124 1125 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 1126 if (!(eax & mask)) { 1127 /* Erratum 658 */ 1128 if (c->x86 == 0x15 && c->x86_model <= 0x1f) { 1129 tlb_lli_2m[ENTRIES] = 1024; 1130 } else { 1131 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 1132 tlb_lli_2m[ENTRIES] = eax & 0xff; 1133 } 1134 } else 1135 tlb_lli_2m[ENTRIES] = eax & mask; 1136 1137 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; 1138 } 1139 1140 static const struct cpu_dev amd_cpu_dev = { 1141 .c_vendor = "AMD", 1142 .c_ident = { "AuthenticAMD" }, 1143 #ifdef CONFIG_X86_32 1144 .legacy_models = { 1145 { .family = 4, .model_names = 1146 { 1147 [3] = "486 DX/2", 1148 [7] = "486 DX/2-WB", 1149 [8] = "486 DX/4", 1150 [9] = "486 DX/4-WB", 1151 [14] = "Am5x86-WT", 1152 [15] = "Am5x86-WB" 1153 } 1154 }, 1155 }, 1156 .legacy_cache_size = amd_size_cache, 1157 #endif 1158 .c_early_init = early_init_amd, 1159 .c_detect_tlb = cpu_detect_tlb_amd, 1160 .c_bsp_init = bsp_init_amd, 1161 .c_init = init_amd, 1162 .c_x86_vendor = X86_VENDOR_AMD, 1163 }; 1164 1165 cpu_dev_register(amd_cpu_dev); 1166 1167 static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[4], amd_dr_addr_mask); 1168 1169 static unsigned int amd_msr_dr_addr_masks[] = { 1170 MSR_F16H_DR0_ADDR_MASK, 1171 MSR_F16H_DR1_ADDR_MASK, 1172 MSR_F16H_DR1_ADDR_MASK + 1, 1173 MSR_F16H_DR1_ADDR_MASK + 2 1174 }; 1175 1176 void amd_set_dr_addr_mask(unsigned long mask, unsigned int dr) 1177 { 1178 int cpu = smp_processor_id(); 1179 1180 if (!cpu_feature_enabled(X86_FEATURE_BPEXT)) 1181 return; 1182 1183 if (WARN_ON_ONCE(dr >= ARRAY_SIZE(amd_msr_dr_addr_masks))) 1184 return; 1185 1186 if (per_cpu(amd_dr_addr_mask, cpu)[dr] == mask) 1187 return; 1188 1189 wrmsr(amd_msr_dr_addr_masks[dr], mask, 0); 1190 per_cpu(amd_dr_addr_mask, cpu)[dr] = mask; 1191 } 1192 1193 unsigned long amd_get_dr_addr_mask(unsigned int dr) 1194 { 1195 if (!cpu_feature_enabled(X86_FEATURE_BPEXT)) 1196 return 0; 1197 1198 if (WARN_ON_ONCE(dr >= ARRAY_SIZE(amd_msr_dr_addr_masks))) 1199 return 0; 1200 1201 return per_cpu(amd_dr_addr_mask[dr], smp_processor_id()); 1202 } 1203 EXPORT_SYMBOL_GPL(amd_get_dr_addr_mask); 1204 1205 static void zenbleed_check_cpu(void *unused) 1206 { 1207 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 1208 1209 zen2_zenbleed_check(c); 1210 } 1211 1212 void amd_check_microcode(void) 1213 { 1214 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) 1215 return; 1216 1217 if (cpu_feature_enabled(X86_FEATURE_ZEN2)) 1218 on_each_cpu(zenbleed_check_cpu, NULL, 1); 1219 } 1220