xref: /linux/arch/x86/kernel/cpu/amd.c (revision 79de4d9ade7411ffdddf0b69c87020311731d155)
1 // SPDX-License-Identifier: GPL-2.0-only
2 #include <linux/export.h>
3 #include <linux/bitops.h>
4 #include <linux/elf.h>
5 #include <linux/mm.h>
6 
7 #include <linux/io.h>
8 #include <linux/sched.h>
9 #include <linux/sched/clock.h>
10 #include <linux/random.h>
11 #include <linux/topology.h>
12 #include <asm/processor.h>
13 #include <asm/apic.h>
14 #include <asm/cacheinfo.h>
15 #include <asm/cpu.h>
16 #include <asm/spec-ctrl.h>
17 #include <asm/smp.h>
18 #include <asm/numa.h>
19 #include <asm/pci-direct.h>
20 #include <asm/delay.h>
21 #include <asm/debugreg.h>
22 #include <asm/resctrl.h>
23 
24 #ifdef CONFIG_X86_64
25 # include <asm/mmconfig.h>
26 #endif
27 
28 #include "cpu.h"
29 
30 /*
31  * nodes_per_socket: Stores the number of nodes per socket.
32  * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
33  * Node Identifiers[10:8]
34  */
35 static u32 nodes_per_socket = 1;
36 
37 /*
38  * AMD errata checking
39  *
40  * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
41  * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
42  * have an OSVW id assigned, which it takes as first argument. Both take a
43  * variable number of family-specific model-stepping ranges created by
44  * AMD_MODEL_RANGE().
45  *
46  * Example:
47  *
48  * const int amd_erratum_319[] =
49  *	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
50  *			   AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
51  *			   AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
52  */
53 
54 #define AMD_LEGACY_ERRATUM(...)		{ -1, __VA_ARGS__, 0 }
55 #define AMD_OSVW_ERRATUM(osvw_id, ...)	{ osvw_id, __VA_ARGS__, 0 }
56 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
57 	((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
58 #define AMD_MODEL_RANGE_FAMILY(range)	(((range) >> 24) & 0xff)
59 #define AMD_MODEL_RANGE_START(range)	(((range) >> 12) & 0xfff)
60 #define AMD_MODEL_RANGE_END(range)	((range) & 0xfff)
61 
62 static const int amd_erratum_400[] =
63 	AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
64 			    AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
65 
66 static const int amd_erratum_383[] =
67 	AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
68 
69 /* #1054: Instructions Retired Performance Counter May Be Inaccurate */
70 static const int amd_erratum_1054[] =
71 	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
72 
73 static const int amd_zenbleed[] =
74 	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x30, 0x0, 0x4f, 0xf),
75 			   AMD_MODEL_RANGE(0x17, 0x60, 0x0, 0x7f, 0xf),
76 			   AMD_MODEL_RANGE(0x17, 0x90, 0x0, 0x91, 0xf),
77 			   AMD_MODEL_RANGE(0x17, 0xa0, 0x0, 0xaf, 0xf));
78 
79 static const int amd_div0[] =
80 	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x00, 0x0, 0x2f, 0xf),
81 			   AMD_MODEL_RANGE(0x17, 0x50, 0x0, 0x5f, 0xf));
82 
83 static const int amd_erratum_1485[] =
84 	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x19, 0x10, 0x0, 0x1f, 0xf),
85 			   AMD_MODEL_RANGE(0x19, 0x60, 0x0, 0xaf, 0xf));
86 
87 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
88 {
89 	int osvw_id = *erratum++;
90 	u32 range;
91 	u32 ms;
92 
93 	if (osvw_id >= 0 && osvw_id < 65536 &&
94 	    cpu_has(cpu, X86_FEATURE_OSVW)) {
95 		u64 osvw_len;
96 
97 		rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
98 		if (osvw_id < osvw_len) {
99 			u64 osvw_bits;
100 
101 			rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
102 			    osvw_bits);
103 			return osvw_bits & (1ULL << (osvw_id & 0x3f));
104 		}
105 	}
106 
107 	/* OSVW unavailable or ID unknown, match family-model-stepping range */
108 	ms = (cpu->x86_model << 4) | cpu->x86_stepping;
109 	while ((range = *erratum++))
110 		if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
111 		    (ms >= AMD_MODEL_RANGE_START(range)) &&
112 		    (ms <= AMD_MODEL_RANGE_END(range)))
113 			return true;
114 
115 	return false;
116 }
117 
118 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
119 {
120 	u32 gprs[8] = { 0 };
121 	int err;
122 
123 	WARN_ONCE((boot_cpu_data.x86 != 0xf),
124 		  "%s should only be used on K8!\n", __func__);
125 
126 	gprs[1] = msr;
127 	gprs[7] = 0x9c5a203a;
128 
129 	err = rdmsr_safe_regs(gprs);
130 
131 	*p = gprs[0] | ((u64)gprs[2] << 32);
132 
133 	return err;
134 }
135 
136 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
137 {
138 	u32 gprs[8] = { 0 };
139 
140 	WARN_ONCE((boot_cpu_data.x86 != 0xf),
141 		  "%s should only be used on K8!\n", __func__);
142 
143 	gprs[0] = (u32)val;
144 	gprs[1] = msr;
145 	gprs[2] = val >> 32;
146 	gprs[7] = 0x9c5a203a;
147 
148 	return wrmsr_safe_regs(gprs);
149 }
150 
151 /*
152  *	B step AMD K6 before B 9730xxxx have hardware bugs that can cause
153  *	misexecution of code under Linux. Owners of such processors should
154  *	contact AMD for precise details and a CPU swap.
155  *
156  *	See	http://www.multimania.com/poulot/k6bug.html
157  *	and	section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
158  *		(Publication # 21266  Issue Date: August 1998)
159  *
160  *	The following test is erm.. interesting. AMD neglected to up
161  *	the chip setting when fixing the bug but they also tweaked some
162  *	performance at the same time..
163  */
164 
165 #ifdef CONFIG_X86_32
166 extern __visible void vide(void);
167 __asm__(".text\n"
168 	".globl vide\n"
169 	".type vide, @function\n"
170 	".align 4\n"
171 	"vide: ret\n");
172 #endif
173 
174 static void init_amd_k5(struct cpuinfo_x86 *c)
175 {
176 #ifdef CONFIG_X86_32
177 /*
178  * General Systems BIOSen alias the cpu frequency registers
179  * of the Elan at 0x000df000. Unfortunately, one of the Linux
180  * drivers subsequently pokes it, and changes the CPU speed.
181  * Workaround : Remove the unneeded alias.
182  */
183 #define CBAR		(0xfffc) /* Configuration Base Address  (32-bit) */
184 #define CBAR_ENB	(0x80000000)
185 #define CBAR_KEY	(0X000000CB)
186 	if (c->x86_model == 9 || c->x86_model == 10) {
187 		if (inl(CBAR) & CBAR_ENB)
188 			outl(0 | CBAR_KEY, CBAR);
189 	}
190 #endif
191 }
192 
193 static void init_amd_k6(struct cpuinfo_x86 *c)
194 {
195 #ifdef CONFIG_X86_32
196 	u32 l, h;
197 	int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);
198 
199 	if (c->x86_model < 6) {
200 		/* Based on AMD doc 20734R - June 2000 */
201 		if (c->x86_model == 0) {
202 			clear_cpu_cap(c, X86_FEATURE_APIC);
203 			set_cpu_cap(c, X86_FEATURE_PGE);
204 		}
205 		return;
206 	}
207 
208 	if (c->x86_model == 6 && c->x86_stepping == 1) {
209 		const int K6_BUG_LOOP = 1000000;
210 		int n;
211 		void (*f_vide)(void);
212 		u64 d, d2;
213 
214 		pr_info("AMD K6 stepping B detected - ");
215 
216 		/*
217 		 * It looks like AMD fixed the 2.6.2 bug and improved indirect
218 		 * calls at the same time.
219 		 */
220 
221 		n = K6_BUG_LOOP;
222 		f_vide = vide;
223 		OPTIMIZER_HIDE_VAR(f_vide);
224 		d = rdtsc();
225 		while (n--)
226 			f_vide();
227 		d2 = rdtsc();
228 		d = d2-d;
229 
230 		if (d > 20*K6_BUG_LOOP)
231 			pr_cont("system stability may be impaired when more than 32 MB are used.\n");
232 		else
233 			pr_cont("probably OK (after B9730xxxx).\n");
234 	}
235 
236 	/* K6 with old style WHCR */
237 	if (c->x86_model < 8 ||
238 	   (c->x86_model == 8 && c->x86_stepping < 8)) {
239 		/* We can only write allocate on the low 508Mb */
240 		if (mbytes > 508)
241 			mbytes = 508;
242 
243 		rdmsr(MSR_K6_WHCR, l, h);
244 		if ((l&0x0000FFFF) == 0) {
245 			unsigned long flags;
246 			l = (1<<0)|((mbytes/4)<<1);
247 			local_irq_save(flags);
248 			wbinvd();
249 			wrmsr(MSR_K6_WHCR, l, h);
250 			local_irq_restore(flags);
251 			pr_info("Enabling old style K6 write allocation for %d Mb\n",
252 				mbytes);
253 		}
254 		return;
255 	}
256 
257 	if ((c->x86_model == 8 && c->x86_stepping > 7) ||
258 	     c->x86_model == 9 || c->x86_model == 13) {
259 		/* The more serious chips .. */
260 
261 		if (mbytes > 4092)
262 			mbytes = 4092;
263 
264 		rdmsr(MSR_K6_WHCR, l, h);
265 		if ((l&0xFFFF0000) == 0) {
266 			unsigned long flags;
267 			l = ((mbytes>>2)<<22)|(1<<16);
268 			local_irq_save(flags);
269 			wbinvd();
270 			wrmsr(MSR_K6_WHCR, l, h);
271 			local_irq_restore(flags);
272 			pr_info("Enabling new style K6 write allocation for %d Mb\n",
273 				mbytes);
274 		}
275 
276 		return;
277 	}
278 
279 	if (c->x86_model == 10) {
280 		/* AMD Geode LX is model 10 */
281 		/* placeholder for any needed mods */
282 		return;
283 	}
284 #endif
285 }
286 
287 static void init_amd_k7(struct cpuinfo_x86 *c)
288 {
289 #ifdef CONFIG_X86_32
290 	u32 l, h;
291 
292 	/*
293 	 * Bit 15 of Athlon specific MSR 15, needs to be 0
294 	 * to enable SSE on Palomino/Morgan/Barton CPU's.
295 	 * If the BIOS didn't enable it already, enable it here.
296 	 */
297 	if (c->x86_model >= 6 && c->x86_model <= 10) {
298 		if (!cpu_has(c, X86_FEATURE_XMM)) {
299 			pr_info("Enabling disabled K7/SSE Support.\n");
300 			msr_clear_bit(MSR_K7_HWCR, 15);
301 			set_cpu_cap(c, X86_FEATURE_XMM);
302 		}
303 	}
304 
305 	/*
306 	 * It's been determined by AMD that Athlons since model 8 stepping 1
307 	 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
308 	 * As per AMD technical note 27212 0.2
309 	 */
310 	if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) {
311 		rdmsr(MSR_K7_CLK_CTL, l, h);
312 		if ((l & 0xfff00000) != 0x20000000) {
313 			pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
314 				l, ((l & 0x000fffff)|0x20000000));
315 			wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
316 		}
317 	}
318 
319 	/* calling is from identify_secondary_cpu() ? */
320 	if (!c->cpu_index)
321 		return;
322 
323 	/*
324 	 * Certain Athlons might work (for various values of 'work') in SMP
325 	 * but they are not certified as MP capable.
326 	 */
327 	/* Athlon 660/661 is valid. */
328 	if ((c->x86_model == 6) && ((c->x86_stepping == 0) ||
329 	    (c->x86_stepping == 1)))
330 		return;
331 
332 	/* Duron 670 is valid */
333 	if ((c->x86_model == 7) && (c->x86_stepping == 0))
334 		return;
335 
336 	/*
337 	 * Athlon 662, Duron 671, and Athlon >model 7 have capability
338 	 * bit. It's worth noting that the A5 stepping (662) of some
339 	 * Athlon XP's have the MP bit set.
340 	 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
341 	 * more.
342 	 */
343 	if (((c->x86_model == 6) && (c->x86_stepping >= 2)) ||
344 	    ((c->x86_model == 7) && (c->x86_stepping >= 1)) ||
345 	     (c->x86_model > 7))
346 		if (cpu_has(c, X86_FEATURE_MP))
347 			return;
348 
349 	/* If we get here, not a certified SMP capable AMD system. */
350 
351 	/*
352 	 * Don't taint if we are running SMP kernel on a single non-MP
353 	 * approved Athlon
354 	 */
355 	WARN_ONCE(1, "WARNING: This combination of AMD"
356 		" processors is not suitable for SMP.\n");
357 	add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
358 #endif
359 }
360 
361 #ifdef CONFIG_NUMA
362 /*
363  * To workaround broken NUMA config.  Read the comment in
364  * srat_detect_node().
365  */
366 static int nearby_node(int apicid)
367 {
368 	int i, node;
369 
370 	for (i = apicid - 1; i >= 0; i--) {
371 		node = __apicid_to_node[i];
372 		if (node != NUMA_NO_NODE && node_online(node))
373 			return node;
374 	}
375 	for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
376 		node = __apicid_to_node[i];
377 		if (node != NUMA_NO_NODE && node_online(node))
378 			return node;
379 	}
380 	return first_node(node_online_map); /* Shouldn't happen */
381 }
382 #endif
383 
384 /*
385  * Fix up cpu_core_id for pre-F17h systems to be in the
386  * [0 .. cores_per_node - 1] range. Not really needed but
387  * kept so as not to break existing setups.
388  */
389 static void legacy_fixup_core_id(struct cpuinfo_x86 *c)
390 {
391 	u32 cus_per_node;
392 
393 	if (c->x86 >= 0x17)
394 		return;
395 
396 	cus_per_node = c->x86_max_cores / nodes_per_socket;
397 	c->cpu_core_id %= cus_per_node;
398 }
399 
400 /*
401  * Fixup core topology information for
402  * (1) AMD multi-node processors
403  *     Assumption: Number of cores in each internal node is the same.
404  * (2) AMD processors supporting compute units
405  */
406 static void amd_get_topology(struct cpuinfo_x86 *c)
407 {
408 	int cpu = smp_processor_id();
409 
410 	/* get information required for multi-node processors */
411 	if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
412 		int err;
413 		u32 eax, ebx, ecx, edx;
414 
415 		cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
416 
417 		c->cpu_die_id  = ecx & 0xff;
418 
419 		if (c->x86 == 0x15)
420 			c->cu_id = ebx & 0xff;
421 
422 		if (c->x86 >= 0x17) {
423 			c->cpu_core_id = ebx & 0xff;
424 
425 			if (smp_num_siblings > 1)
426 				c->x86_max_cores /= smp_num_siblings;
427 		}
428 
429 		/*
430 		 * In case leaf B is available, use it to derive
431 		 * topology information.
432 		 */
433 		err = detect_extended_topology(c);
434 		if (!err)
435 			c->x86_coreid_bits = get_count_order(c->x86_max_cores);
436 
437 		cacheinfo_amd_init_llc_id(c, cpu);
438 
439 	} else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
440 		u64 value;
441 
442 		rdmsrl(MSR_FAM10H_NODE_ID, value);
443 		c->cpu_die_id = value & 7;
444 
445 		per_cpu(cpu_llc_id, cpu) = c->cpu_die_id;
446 	} else
447 		return;
448 
449 	if (nodes_per_socket > 1) {
450 		set_cpu_cap(c, X86_FEATURE_AMD_DCM);
451 		legacy_fixup_core_id(c);
452 	}
453 }
454 
455 /*
456  * On a AMD dual core setup the lower bits of the APIC id distinguish the cores.
457  * Assumes number of cores is a power of two.
458  */
459 static void amd_detect_cmp(struct cpuinfo_x86 *c)
460 {
461 	unsigned bits;
462 	int cpu = smp_processor_id();
463 
464 	bits = c->x86_coreid_bits;
465 	/* Low order bits define the core id (index of core in socket) */
466 	c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
467 	/* Convert the initial APIC ID into the socket ID */
468 	c->phys_proc_id = c->initial_apicid >> bits;
469 	/* use socket ID also for last level cache */
470 	per_cpu(cpu_llc_id, cpu) = c->cpu_die_id = c->phys_proc_id;
471 }
472 
473 u32 amd_get_nodes_per_socket(void)
474 {
475 	return nodes_per_socket;
476 }
477 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket);
478 
479 static void srat_detect_node(struct cpuinfo_x86 *c)
480 {
481 #ifdef CONFIG_NUMA
482 	int cpu = smp_processor_id();
483 	int node;
484 	unsigned apicid = c->apicid;
485 
486 	node = numa_cpu_node(cpu);
487 	if (node == NUMA_NO_NODE)
488 		node = get_llc_id(cpu);
489 
490 	/*
491 	 * On multi-fabric platform (e.g. Numascale NumaChip) a
492 	 * platform-specific handler needs to be called to fixup some
493 	 * IDs of the CPU.
494 	 */
495 	if (x86_cpuinit.fixup_cpu_id)
496 		x86_cpuinit.fixup_cpu_id(c, node);
497 
498 	if (!node_online(node)) {
499 		/*
500 		 * Two possibilities here:
501 		 *
502 		 * - The CPU is missing memory and no node was created.  In
503 		 *   that case try picking one from a nearby CPU.
504 		 *
505 		 * - The APIC IDs differ from the HyperTransport node IDs
506 		 *   which the K8 northbridge parsing fills in.  Assume
507 		 *   they are all increased by a constant offset, but in
508 		 *   the same order as the HT nodeids.  If that doesn't
509 		 *   result in a usable node fall back to the path for the
510 		 *   previous case.
511 		 *
512 		 * This workaround operates directly on the mapping between
513 		 * APIC ID and NUMA node, assuming certain relationship
514 		 * between APIC ID, HT node ID and NUMA topology.  As going
515 		 * through CPU mapping may alter the outcome, directly
516 		 * access __apicid_to_node[].
517 		 */
518 		int ht_nodeid = c->initial_apicid;
519 
520 		if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
521 			node = __apicid_to_node[ht_nodeid];
522 		/* Pick a nearby node */
523 		if (!node_online(node))
524 			node = nearby_node(apicid);
525 	}
526 	numa_set_node(cpu, node);
527 #endif
528 }
529 
530 static void early_init_amd_mc(struct cpuinfo_x86 *c)
531 {
532 #ifdef CONFIG_SMP
533 	unsigned bits, ecx;
534 
535 	/* Multi core CPU? */
536 	if (c->extended_cpuid_level < 0x80000008)
537 		return;
538 
539 	ecx = cpuid_ecx(0x80000008);
540 
541 	c->x86_max_cores = (ecx & 0xff) + 1;
542 
543 	/* CPU telling us the core id bits shift? */
544 	bits = (ecx >> 12) & 0xF;
545 
546 	/* Otherwise recompute */
547 	if (bits == 0) {
548 		while ((1 << bits) < c->x86_max_cores)
549 			bits++;
550 	}
551 
552 	c->x86_coreid_bits = bits;
553 #endif
554 }
555 
556 static void bsp_init_amd(struct cpuinfo_x86 *c)
557 {
558 	if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
559 
560 		if (c->x86 > 0x10 ||
561 		    (c->x86 == 0x10 && c->x86_model >= 0x2)) {
562 			u64 val;
563 
564 			rdmsrl(MSR_K7_HWCR, val);
565 			if (!(val & BIT(24)))
566 				pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
567 		}
568 	}
569 
570 	if (c->x86 == 0x15) {
571 		unsigned long upperbit;
572 		u32 cpuid, assoc;
573 
574 		cpuid	 = cpuid_edx(0x80000005);
575 		assoc	 = cpuid >> 16 & 0xff;
576 		upperbit = ((cpuid >> 24) << 10) / assoc;
577 
578 		va_align.mask	  = (upperbit - 1) & PAGE_MASK;
579 		va_align.flags    = ALIGN_VA_32 | ALIGN_VA_64;
580 
581 		/* A random value per boot for bit slice [12:upper_bit) */
582 		va_align.bits = get_random_u32() & va_align.mask;
583 	}
584 
585 	if (cpu_has(c, X86_FEATURE_MWAITX))
586 		use_mwaitx_delay();
587 
588 	if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
589 		u32 ecx;
590 
591 		ecx = cpuid_ecx(0x8000001e);
592 		__max_die_per_package = nodes_per_socket = ((ecx >> 8) & 7) + 1;
593 	} else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
594 		u64 value;
595 
596 		rdmsrl(MSR_FAM10H_NODE_ID, value);
597 		__max_die_per_package = nodes_per_socket = ((value >> 3) & 7) + 1;
598 	}
599 
600 	if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) &&
601 	    !boot_cpu_has(X86_FEATURE_VIRT_SSBD) &&
602 	    c->x86 >= 0x15 && c->x86 <= 0x17) {
603 		unsigned int bit;
604 
605 		switch (c->x86) {
606 		case 0x15: bit = 54; break;
607 		case 0x16: bit = 33; break;
608 		case 0x17: bit = 10; break;
609 		default: return;
610 		}
611 		/*
612 		 * Try to cache the base value so further operations can
613 		 * avoid RMW. If that faults, do not enable SSBD.
614 		 */
615 		if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {
616 			setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD);
617 			setup_force_cpu_cap(X86_FEATURE_SSBD);
618 			x86_amd_ls_cfg_ssbd_mask = 1ULL << bit;
619 		}
620 	}
621 
622 	resctrl_cpu_detect(c);
623 }
624 
625 static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
626 {
627 	u64 msr;
628 
629 	/*
630 	 * BIOS support is required for SME and SEV.
631 	 *   For SME: If BIOS has enabled SME then adjust x86_phys_bits by
632 	 *	      the SME physical address space reduction value.
633 	 *	      If BIOS has not enabled SME then don't advertise the
634 	 *	      SME feature (set in scattered.c).
635 	 *	      If the kernel has not enabled SME via any means then
636 	 *	      don't advertise the SME feature.
637 	 *   For SEV: If BIOS has not enabled SEV then don't advertise the
638 	 *            SEV and SEV_ES feature (set in scattered.c).
639 	 *
640 	 *   In all cases, since support for SME and SEV requires long mode,
641 	 *   don't advertise the feature under CONFIG_X86_32.
642 	 */
643 	if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) {
644 		/* Check if memory encryption is enabled */
645 		rdmsrl(MSR_AMD64_SYSCFG, msr);
646 		if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
647 			goto clear_all;
648 
649 		/*
650 		 * Always adjust physical address bits. Even though this
651 		 * will be a value above 32-bits this is still done for
652 		 * CONFIG_X86_32 so that accurate values are reported.
653 		 */
654 		c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f;
655 
656 		if (IS_ENABLED(CONFIG_X86_32))
657 			goto clear_all;
658 
659 		if (!sme_me_mask)
660 			setup_clear_cpu_cap(X86_FEATURE_SME);
661 
662 		rdmsrl(MSR_K7_HWCR, msr);
663 		if (!(msr & MSR_K7_HWCR_SMMLOCK))
664 			goto clear_sev;
665 
666 		return;
667 
668 clear_all:
669 		setup_clear_cpu_cap(X86_FEATURE_SME);
670 clear_sev:
671 		setup_clear_cpu_cap(X86_FEATURE_SEV);
672 		setup_clear_cpu_cap(X86_FEATURE_SEV_ES);
673 	}
674 }
675 
676 static void early_init_amd(struct cpuinfo_x86 *c)
677 {
678 	u64 value;
679 	u32 dummy;
680 
681 	early_init_amd_mc(c);
682 
683 	if (c->x86 >= 0xf)
684 		set_cpu_cap(c, X86_FEATURE_K8);
685 
686 	rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
687 
688 	/*
689 	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
690 	 * with P/T states and does not stop in deep C-states
691 	 */
692 	if (c->x86_power & (1 << 8)) {
693 		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
694 		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
695 	}
696 
697 	/* Bit 12 of 8000_0007 edx is accumulated power mechanism. */
698 	if (c->x86_power & BIT(12))
699 		set_cpu_cap(c, X86_FEATURE_ACC_POWER);
700 
701 	/* Bit 14 indicates the Runtime Average Power Limit interface. */
702 	if (c->x86_power & BIT(14))
703 		set_cpu_cap(c, X86_FEATURE_RAPL);
704 
705 #ifdef CONFIG_X86_64
706 	set_cpu_cap(c, X86_FEATURE_SYSCALL32);
707 #else
708 	/*  Set MTRR capability flag if appropriate */
709 	if (c->x86 == 5)
710 		if (c->x86_model == 13 || c->x86_model == 9 ||
711 		    (c->x86_model == 8 && c->x86_stepping >= 8))
712 			set_cpu_cap(c, X86_FEATURE_K6_MTRR);
713 #endif
714 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
715 	/*
716 	 * ApicID can always be treated as an 8-bit value for AMD APIC versions
717 	 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we
718 	 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families
719 	 * after 16h.
720 	 */
721 	if (boot_cpu_has(X86_FEATURE_APIC)) {
722 		if (c->x86 > 0x16)
723 			set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
724 		else if (c->x86 >= 0xf) {
725 			/* check CPU config space for extended APIC ID */
726 			unsigned int val;
727 
728 			val = read_pci_config(0, 24, 0, 0x68);
729 			if ((val >> 17 & 0x3) == 0x3)
730 				set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
731 		}
732 	}
733 #endif
734 
735 	/*
736 	 * This is only needed to tell the kernel whether to use VMCALL
737 	 * and VMMCALL.  VMMCALL is never executed except under virt, so
738 	 * we can set it unconditionally.
739 	 */
740 	set_cpu_cap(c, X86_FEATURE_VMMCALL);
741 
742 	/* F16h erratum 793, CVE-2013-6885 */
743 	if (c->x86 == 0x16 && c->x86_model <= 0xf)
744 		msr_set_bit(MSR_AMD64_LS_CFG, 15);
745 
746 	/*
747 	 * Check whether the machine is affected by erratum 400. This is
748 	 * used to select the proper idle routine and to enable the check
749 	 * whether the machine is affected in arch_post_acpi_init(), which
750 	 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check.
751 	 */
752 	if (cpu_has_amd_erratum(c, amd_erratum_400))
753 		set_cpu_bug(c, X86_BUG_AMD_E400);
754 
755 	early_detect_mem_encrypt(c);
756 
757 	/* Re-enable TopologyExtensions if switched off by BIOS */
758 	if (c->x86 == 0x15 &&
759 	    (c->x86_model >= 0x10 && c->x86_model <= 0x6f) &&
760 	    !cpu_has(c, X86_FEATURE_TOPOEXT)) {
761 
762 		if (msr_set_bit(0xc0011005, 54) > 0) {
763 			rdmsrl(0xc0011005, value);
764 			if (value & BIT_64(54)) {
765 				set_cpu_cap(c, X86_FEATURE_TOPOEXT);
766 				pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
767 			}
768 		}
769 	}
770 
771 	if (cpu_has(c, X86_FEATURE_TOPOEXT))
772 		smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1;
773 
774 	if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && !cpu_has(c, X86_FEATURE_IBPB_BRTYPE)) {
775 		if (c->x86 == 0x17 && boot_cpu_has(X86_FEATURE_AMD_IBPB))
776 			setup_force_cpu_cap(X86_FEATURE_IBPB_BRTYPE);
777 		else if (c->x86 >= 0x19 && !wrmsrl_safe(MSR_IA32_PRED_CMD, PRED_CMD_SBPB)) {
778 			setup_force_cpu_cap(X86_FEATURE_IBPB_BRTYPE);
779 			setup_force_cpu_cap(X86_FEATURE_SBPB);
780 		}
781 	}
782 }
783 
784 static void init_amd_k8(struct cpuinfo_x86 *c)
785 {
786 	u32 level;
787 	u64 value;
788 
789 	/* On C+ stepping K8 rep microcode works well for copy/memset */
790 	level = cpuid_eax(1);
791 	if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
792 		set_cpu_cap(c, X86_FEATURE_REP_GOOD);
793 
794 	/*
795 	 * Some BIOSes incorrectly force this feature, but only K8 revision D
796 	 * (model = 0x14) and later actually support it.
797 	 * (AMD Erratum #110, docId: 25759).
798 	 */
799 	if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
800 		clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
801 		if (!rdmsrl_amd_safe(0xc001100d, &value)) {
802 			value &= ~BIT_64(32);
803 			wrmsrl_amd_safe(0xc001100d, value);
804 		}
805 	}
806 
807 	if (!c->x86_model_id[0])
808 		strcpy(c->x86_model_id, "Hammer");
809 
810 #ifdef CONFIG_SMP
811 	/*
812 	 * Disable TLB flush filter by setting HWCR.FFDIS on K8
813 	 * bit 6 of msr C001_0015
814 	 *
815 	 * Errata 63 for SH-B3 steppings
816 	 * Errata 122 for all steppings (F+ have it disabled by default)
817 	 */
818 	msr_set_bit(MSR_K7_HWCR, 6);
819 #endif
820 	set_cpu_bug(c, X86_BUG_SWAPGS_FENCE);
821 }
822 
823 static void init_amd_gh(struct cpuinfo_x86 *c)
824 {
825 #ifdef CONFIG_MMCONF_FAM10H
826 	/* do this for boot cpu */
827 	if (c == &boot_cpu_data)
828 		check_enable_amd_mmconf_dmi();
829 
830 	fam10h_check_enable_mmcfg();
831 #endif
832 
833 	/*
834 	 * Disable GART TLB Walk Errors on Fam10h. We do this here because this
835 	 * is always needed when GART is enabled, even in a kernel which has no
836 	 * MCE support built in. BIOS should disable GartTlbWlk Errors already.
837 	 * If it doesn't, we do it here as suggested by the BKDG.
838 	 *
839 	 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
840 	 */
841 	msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);
842 
843 	/*
844 	 * On family 10h BIOS may not have properly enabled WC+ support, causing
845 	 * it to be converted to CD memtype. This may result in performance
846 	 * degradation for certain nested-paging guests. Prevent this conversion
847 	 * by clearing bit 24 in MSR_AMD64_BU_CFG2.
848 	 *
849 	 * NOTE: we want to use the _safe accessors so as not to #GP kvm
850 	 * guests on older kvm hosts.
851 	 */
852 	msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
853 
854 	if (cpu_has_amd_erratum(c, amd_erratum_383))
855 		set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
856 }
857 
858 static void init_amd_ln(struct cpuinfo_x86 *c)
859 {
860 	/*
861 	 * Apply erratum 665 fix unconditionally so machines without a BIOS
862 	 * fix work.
863 	 */
864 	msr_set_bit(MSR_AMD64_DE_CFG, 31);
865 }
866 
867 static bool rdrand_force;
868 
869 static int __init rdrand_cmdline(char *str)
870 {
871 	if (!str)
872 		return -EINVAL;
873 
874 	if (!strcmp(str, "force"))
875 		rdrand_force = true;
876 	else
877 		return -EINVAL;
878 
879 	return 0;
880 }
881 early_param("rdrand", rdrand_cmdline);
882 
883 static void clear_rdrand_cpuid_bit(struct cpuinfo_x86 *c)
884 {
885 	/*
886 	 * Saving of the MSR used to hide the RDRAND support during
887 	 * suspend/resume is done by arch/x86/power/cpu.c, which is
888 	 * dependent on CONFIG_PM_SLEEP.
889 	 */
890 	if (!IS_ENABLED(CONFIG_PM_SLEEP))
891 		return;
892 
893 	/*
894 	 * The self-test can clear X86_FEATURE_RDRAND, so check for
895 	 * RDRAND support using the CPUID function directly.
896 	 */
897 	if (!(cpuid_ecx(1) & BIT(30)) || rdrand_force)
898 		return;
899 
900 	msr_clear_bit(MSR_AMD64_CPUID_FN_1, 62);
901 
902 	/*
903 	 * Verify that the CPUID change has occurred in case the kernel is
904 	 * running virtualized and the hypervisor doesn't support the MSR.
905 	 */
906 	if (cpuid_ecx(1) & BIT(30)) {
907 		pr_info_once("BIOS may not properly restore RDRAND after suspend, but hypervisor does not support hiding RDRAND via CPUID.\n");
908 		return;
909 	}
910 
911 	clear_cpu_cap(c, X86_FEATURE_RDRAND);
912 	pr_info_once("BIOS may not properly restore RDRAND after suspend, hiding RDRAND via CPUID. Use rdrand=force to reenable.\n");
913 }
914 
915 static void init_amd_jg(struct cpuinfo_x86 *c)
916 {
917 	/*
918 	 * Some BIOS implementations do not restore proper RDRAND support
919 	 * across suspend and resume. Check on whether to hide the RDRAND
920 	 * instruction support via CPUID.
921 	 */
922 	clear_rdrand_cpuid_bit(c);
923 }
924 
925 static void init_amd_bd(struct cpuinfo_x86 *c)
926 {
927 	u64 value;
928 
929 	/*
930 	 * The way access filter has a performance penalty on some workloads.
931 	 * Disable it on the affected CPUs.
932 	 */
933 	if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
934 		if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) {
935 			value |= 0x1E;
936 			wrmsrl_safe(MSR_F15H_IC_CFG, value);
937 		}
938 	}
939 
940 	/*
941 	 * Some BIOS implementations do not restore proper RDRAND support
942 	 * across suspend and resume. Check on whether to hide the RDRAND
943 	 * instruction support via CPUID.
944 	 */
945 	clear_rdrand_cpuid_bit(c);
946 }
947 
948 void init_spectral_chicken(struct cpuinfo_x86 *c)
949 {
950 #ifdef CONFIG_CPU_UNRET_ENTRY
951 	u64 value;
952 
953 	/*
954 	 * On Zen2 we offer this chicken (bit) on the altar of Speculation.
955 	 *
956 	 * This suppresses speculation from the middle of a basic block, i.e. it
957 	 * suppresses non-branch predictions.
958 	 *
959 	 * We use STIBP as a heuristic to filter out Zen2 from the rest of F17H
960 	 */
961 	if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && cpu_has(c, X86_FEATURE_AMD_STIBP)) {
962 		if (!rdmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, &value)) {
963 			value |= MSR_ZEN2_SPECTRAL_CHICKEN_BIT;
964 			wrmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, value);
965 		}
966 	}
967 #endif
968 	/*
969 	 * Work around Erratum 1386.  The XSAVES instruction malfunctions in
970 	 * certain circumstances on Zen1/2 uarch, and not all parts have had
971 	 * updated microcode at the time of writing (March 2023).
972 	 *
973 	 * Affected parts all have no supervisor XSAVE states, meaning that
974 	 * the XSAVEC instruction (which works fine) is equivalent.
975 	 */
976 	clear_cpu_cap(c, X86_FEATURE_XSAVES);
977 }
978 
979 static void init_amd_zn(struct cpuinfo_x86 *c)
980 {
981 	set_cpu_cap(c, X86_FEATURE_ZEN);
982 
983 #ifdef CONFIG_NUMA
984 	node_reclaim_distance = 32;
985 #endif
986 
987 	/* Fix up CPUID bits, but only if not virtualised. */
988 	if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) {
989 
990 		/* Erratum 1076: CPB feature bit not being set in CPUID. */
991 		if (!cpu_has(c, X86_FEATURE_CPB))
992 			set_cpu_cap(c, X86_FEATURE_CPB);
993 
994 		/*
995 		 * Zen3 (Fam19 model < 0x10) parts are not susceptible to
996 		 * Branch Type Confusion, but predate the allocation of the
997 		 * BTC_NO bit.
998 		 */
999 		if (c->x86 == 0x19 && !cpu_has(c, X86_FEATURE_BTC_NO))
1000 			set_cpu_cap(c, X86_FEATURE_BTC_NO);
1001 	}
1002 }
1003 
1004 static bool cpu_has_zenbleed_microcode(void)
1005 {
1006 	u32 good_rev = 0;
1007 
1008 	switch (boot_cpu_data.x86_model) {
1009 	case 0x30 ... 0x3f: good_rev = 0x0830107a; break;
1010 	case 0x60 ... 0x67: good_rev = 0x0860010b; break;
1011 	case 0x68 ... 0x6f: good_rev = 0x08608105; break;
1012 	case 0x70 ... 0x7f: good_rev = 0x08701032; break;
1013 	case 0xa0 ... 0xaf: good_rev = 0x08a00008; break;
1014 
1015 	default:
1016 		return false;
1017 		break;
1018 	}
1019 
1020 	if (boot_cpu_data.microcode < good_rev)
1021 		return false;
1022 
1023 	return true;
1024 }
1025 
1026 static void zenbleed_check(struct cpuinfo_x86 *c)
1027 {
1028 	if (!cpu_has_amd_erratum(c, amd_zenbleed))
1029 		return;
1030 
1031 	if (cpu_has(c, X86_FEATURE_HYPERVISOR))
1032 		return;
1033 
1034 	if (!cpu_has(c, X86_FEATURE_AVX))
1035 		return;
1036 
1037 	if (!cpu_has_zenbleed_microcode()) {
1038 		pr_notice_once("Zenbleed: please update your microcode for the most optimal fix\n");
1039 		msr_set_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
1040 	} else {
1041 		msr_clear_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
1042 	}
1043 }
1044 
1045 static void init_amd(struct cpuinfo_x86 *c)
1046 {
1047 	early_init_amd(c);
1048 
1049 	/*
1050 	 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
1051 	 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
1052 	 */
1053 	clear_cpu_cap(c, 0*32+31);
1054 
1055 	if (c->x86 >= 0x10)
1056 		set_cpu_cap(c, X86_FEATURE_REP_GOOD);
1057 
1058 	/* AMD FSRM also implies FSRS */
1059 	if (cpu_has(c, X86_FEATURE_FSRM))
1060 		set_cpu_cap(c, X86_FEATURE_FSRS);
1061 
1062 	/* get apicid instead of initial apic id from cpuid */
1063 	c->apicid = read_apic_id();
1064 
1065 	/* K6s reports MCEs but don't actually have all the MSRs */
1066 	if (c->x86 < 6)
1067 		clear_cpu_cap(c, X86_FEATURE_MCE);
1068 
1069 	switch (c->x86) {
1070 	case 4:    init_amd_k5(c); break;
1071 	case 5:    init_amd_k6(c); break;
1072 	case 6:	   init_amd_k7(c); break;
1073 	case 0xf:  init_amd_k8(c); break;
1074 	case 0x10: init_amd_gh(c); break;
1075 	case 0x12: init_amd_ln(c); break;
1076 	case 0x15: init_amd_bd(c); break;
1077 	case 0x16: init_amd_jg(c); break;
1078 	case 0x17: init_spectral_chicken(c);
1079 		   fallthrough;
1080 	case 0x19: init_amd_zn(c); break;
1081 	}
1082 
1083 	/*
1084 	 * Enable workaround for FXSAVE leak on CPUs
1085 	 * without a XSaveErPtr feature
1086 	 */
1087 	if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR)))
1088 		set_cpu_bug(c, X86_BUG_FXSAVE_LEAK);
1089 
1090 	cpu_detect_cache_sizes(c);
1091 
1092 	amd_detect_cmp(c);
1093 	amd_get_topology(c);
1094 	srat_detect_node(c);
1095 
1096 	init_amd_cacheinfo(c);
1097 
1098 	if (!cpu_has(c, X86_FEATURE_LFENCE_RDTSC) && cpu_has(c, X86_FEATURE_XMM2)) {
1099 		/*
1100 		 * Use LFENCE for execution serialization.  On families which
1101 		 * don't have that MSR, LFENCE is already serializing.
1102 		 * msr_set_bit() uses the safe accessors, too, even if the MSR
1103 		 * is not present.
1104 		 */
1105 		msr_set_bit(MSR_AMD64_DE_CFG,
1106 			    MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT);
1107 
1108 		/* A serializing LFENCE stops RDTSC speculation */
1109 		set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
1110 	}
1111 
1112 	/*
1113 	 * Family 0x12 and above processors have APIC timer
1114 	 * running in deep C states.
1115 	 */
1116 	if (c->x86 > 0x11)
1117 		set_cpu_cap(c, X86_FEATURE_ARAT);
1118 
1119 	/* 3DNow or LM implies PREFETCHW */
1120 	if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH))
1121 		if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM))
1122 			set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH);
1123 
1124 	/* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */
1125 	if (!cpu_feature_enabled(X86_FEATURE_XENPV))
1126 		set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
1127 
1128 	/*
1129 	 * Turn on the Instructions Retired free counter on machines not
1130 	 * susceptible to erratum #1054 "Instructions Retired Performance
1131 	 * Counter May Be Inaccurate".
1132 	 */
1133 	if (cpu_has(c, X86_FEATURE_IRPERF) &&
1134 	    !cpu_has_amd_erratum(c, amd_erratum_1054))
1135 		msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT);
1136 
1137 	check_null_seg_clears_base(c);
1138 
1139 	/*
1140 	 * Make sure EFER[AIBRSE - Automatic IBRS Enable] is set. The APs are brought up
1141 	 * using the trampoline code and as part of it, MSR_EFER gets prepared there in
1142 	 * order to be replicated onto them. Regardless, set it here again, if not set,
1143 	 * to protect against any future refactoring/code reorganization which might
1144 	 * miss setting this important bit.
1145 	 */
1146 	if (spectre_v2_in_eibrs_mode(spectre_v2_enabled) &&
1147 	    cpu_has(c, X86_FEATURE_AUTOIBRS))
1148 		WARN_ON_ONCE(msr_set_bit(MSR_EFER, _EFER_AUTOIBRS));
1149 
1150 	zenbleed_check(c);
1151 
1152 	if (cpu_has_amd_erratum(c, amd_div0)) {
1153 		pr_notice_once("AMD Zen1 DIV0 bug detected. Disable SMT for full protection.\n");
1154 		setup_force_cpu_bug(X86_BUG_DIV0);
1155 	}
1156 
1157 	if (!cpu_has(c, X86_FEATURE_HYPERVISOR) &&
1158 	     cpu_has_amd_erratum(c, amd_erratum_1485))
1159 		msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT);
1160 }
1161 
1162 #ifdef CONFIG_X86_32
1163 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
1164 {
1165 	/* AMD errata T13 (order #21922) */
1166 	if (c->x86 == 6) {
1167 		/* Duron Rev A0 */
1168 		if (c->x86_model == 3 && c->x86_stepping == 0)
1169 			size = 64;
1170 		/* Tbird rev A1/A2 */
1171 		if (c->x86_model == 4 &&
1172 			(c->x86_stepping == 0 || c->x86_stepping == 1))
1173 			size = 256;
1174 	}
1175 	return size;
1176 }
1177 #endif
1178 
1179 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
1180 {
1181 	u32 ebx, eax, ecx, edx;
1182 	u16 mask = 0xfff;
1183 
1184 	if (c->x86 < 0xf)
1185 		return;
1186 
1187 	if (c->extended_cpuid_level < 0x80000006)
1188 		return;
1189 
1190 	cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
1191 
1192 	tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
1193 	tlb_lli_4k[ENTRIES] = ebx & mask;
1194 
1195 	/*
1196 	 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
1197 	 * characteristics from the CPUID function 0x80000005 instead.
1198 	 */
1199 	if (c->x86 == 0xf) {
1200 		cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
1201 		mask = 0xff;
1202 	}
1203 
1204 	/* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
1205 	if (!((eax >> 16) & mask))
1206 		tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
1207 	else
1208 		tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
1209 
1210 	/* a 4M entry uses two 2M entries */
1211 	tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
1212 
1213 	/* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
1214 	if (!(eax & mask)) {
1215 		/* Erratum 658 */
1216 		if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
1217 			tlb_lli_2m[ENTRIES] = 1024;
1218 		} else {
1219 			cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
1220 			tlb_lli_2m[ENTRIES] = eax & 0xff;
1221 		}
1222 	} else
1223 		tlb_lli_2m[ENTRIES] = eax & mask;
1224 
1225 	tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
1226 }
1227 
1228 static const struct cpu_dev amd_cpu_dev = {
1229 	.c_vendor	= "AMD",
1230 	.c_ident	= { "AuthenticAMD" },
1231 #ifdef CONFIG_X86_32
1232 	.legacy_models = {
1233 		{ .family = 4, .model_names =
1234 		  {
1235 			  [3] = "486 DX/2",
1236 			  [7] = "486 DX/2-WB",
1237 			  [8] = "486 DX/4",
1238 			  [9] = "486 DX/4-WB",
1239 			  [14] = "Am5x86-WT",
1240 			  [15] = "Am5x86-WB"
1241 		  }
1242 		},
1243 	},
1244 	.legacy_cache_size = amd_size_cache,
1245 #endif
1246 	.c_early_init   = early_init_amd,
1247 	.c_detect_tlb	= cpu_detect_tlb_amd,
1248 	.c_bsp_init	= bsp_init_amd,
1249 	.c_init		= init_amd,
1250 	.c_x86_vendor	= X86_VENDOR_AMD,
1251 };
1252 
1253 cpu_dev_register(amd_cpu_dev);
1254 
1255 static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[4], amd_dr_addr_mask);
1256 
1257 static unsigned int amd_msr_dr_addr_masks[] = {
1258 	MSR_F16H_DR0_ADDR_MASK,
1259 	MSR_F16H_DR1_ADDR_MASK,
1260 	MSR_F16H_DR1_ADDR_MASK + 1,
1261 	MSR_F16H_DR1_ADDR_MASK + 2
1262 };
1263 
1264 void amd_set_dr_addr_mask(unsigned long mask, unsigned int dr)
1265 {
1266 	int cpu = smp_processor_id();
1267 
1268 	if (!cpu_feature_enabled(X86_FEATURE_BPEXT))
1269 		return;
1270 
1271 	if (WARN_ON_ONCE(dr >= ARRAY_SIZE(amd_msr_dr_addr_masks)))
1272 		return;
1273 
1274 	if (per_cpu(amd_dr_addr_mask, cpu)[dr] == mask)
1275 		return;
1276 
1277 	wrmsr(amd_msr_dr_addr_masks[dr], mask, 0);
1278 	per_cpu(amd_dr_addr_mask, cpu)[dr] = mask;
1279 }
1280 
1281 unsigned long amd_get_dr_addr_mask(unsigned int dr)
1282 {
1283 	if (!cpu_feature_enabled(X86_FEATURE_BPEXT))
1284 		return 0;
1285 
1286 	if (WARN_ON_ONCE(dr >= ARRAY_SIZE(amd_msr_dr_addr_masks)))
1287 		return 0;
1288 
1289 	return per_cpu(amd_dr_addr_mask[dr], smp_processor_id());
1290 }
1291 EXPORT_SYMBOL_GPL(amd_get_dr_addr_mask);
1292 
1293 u32 amd_get_highest_perf(void)
1294 {
1295 	struct cpuinfo_x86 *c = &boot_cpu_data;
1296 
1297 	if (c->x86 == 0x17 && ((c->x86_model >= 0x30 && c->x86_model < 0x40) ||
1298 			       (c->x86_model >= 0x70 && c->x86_model < 0x80)))
1299 		return 166;
1300 
1301 	if (c->x86 == 0x19 && ((c->x86_model >= 0x20 && c->x86_model < 0x30) ||
1302 			       (c->x86_model >= 0x40 && c->x86_model < 0x70)))
1303 		return 166;
1304 
1305 	return 255;
1306 }
1307 EXPORT_SYMBOL_GPL(amd_get_highest_perf);
1308 
1309 static void zenbleed_check_cpu(void *unused)
1310 {
1311 	struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
1312 
1313 	zenbleed_check(c);
1314 }
1315 
1316 void amd_check_microcode(void)
1317 {
1318 	on_each_cpu(zenbleed_check_cpu, NULL, 1);
1319 }
1320 
1321 /*
1322  * Issue a DIV 0/1 insn to clear any division data from previous DIV
1323  * operations.
1324  */
1325 void noinstr amd_clear_divider(void)
1326 {
1327 	asm volatile(ALTERNATIVE("", "div %2\n\t", X86_BUG_DIV0)
1328 		     :: "a" (0), "d" (0), "r" (1));
1329 }
1330 EXPORT_SYMBOL_GPL(amd_clear_divider);
1331