1 #include <linux/init.h> 2 #include <linux/bitops.h> 3 #include <linux/mm.h> 4 #include <asm/io.h> 5 #include <asm/processor.h> 6 #include <asm/apic.h> 7 #include <asm/mach_apic.h> 8 9 #include "cpu.h" 10 11 /* 12 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 13 * misexecution of code under Linux. Owners of such processors should 14 * contact AMD for precise details and a CPU swap. 15 * 16 * See http://www.multimania.com/poulot/k6bug.html 17 * http://www.amd.com/K6/k6docs/revgd.html 18 * 19 * The following test is erm.. interesting. AMD neglected to up 20 * the chip setting when fixing the bug but they also tweaked some 21 * performance at the same time.. 22 */ 23 24 extern void vide(void); 25 __asm__(".align 4\nvide: ret"); 26 27 #ifdef CONFIG_X86_LOCAL_APIC 28 #define ENABLE_C1E_MASK 0x18000000 29 #define CPUID_PROCESSOR_SIGNATURE 1 30 #define CPUID_XFAM 0x0ff00000 31 #define CPUID_XFAM_K8 0x00000000 32 #define CPUID_XFAM_10H 0x00100000 33 #define CPUID_XFAM_11H 0x00200000 34 #define CPUID_XMOD 0x000f0000 35 #define CPUID_XMOD_REV_F 0x00040000 36 37 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */ 38 static __cpuinit int amd_apic_timer_broken(void) 39 { 40 u32 lo, hi; 41 u32 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE); 42 switch (eax & CPUID_XFAM) { 43 case CPUID_XFAM_K8: 44 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F) 45 break; 46 case CPUID_XFAM_10H: 47 case CPUID_XFAM_11H: 48 rdmsr(MSR_K8_ENABLE_C1E, lo, hi); 49 if (lo & ENABLE_C1E_MASK) { 50 if (smp_processor_id() != boot_cpu_physical_apicid) 51 printk(KERN_INFO "AMD C1E detected late. " 52 " Force timer broadcast.\n"); 53 return 1; 54 } 55 break; 56 default: 57 /* err on the side of caution */ 58 return 1; 59 } 60 return 0; 61 } 62 #endif 63 64 int force_mwait __cpuinitdata; 65 66 static void __cpuinit init_amd(struct cpuinfo_x86 *c) 67 { 68 u32 l, h; 69 int mbytes = num_physpages >> (20-PAGE_SHIFT); 70 int r; 71 72 #ifdef CONFIG_SMP 73 unsigned long long value; 74 75 /* Disable TLB flush filter by setting HWCR.FFDIS on K8 76 * bit 6 of msr C001_0015 77 * 78 * Errata 63 for SH-B3 steppings 79 * Errata 122 for all steppings (F+ have it disabled by default) 80 */ 81 if (c->x86 == 15) { 82 rdmsrl(MSR_K7_HWCR, value); 83 value |= 1 << 6; 84 wrmsrl(MSR_K7_HWCR, value); 85 } 86 #endif 87 88 /* 89 * FIXME: We should handle the K5 here. Set up the write 90 * range and also turn on MSR 83 bits 4 and 31 (write alloc, 91 * no bus pipeline) 92 */ 93 94 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID; 95 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */ 96 clear_bit(0*32+31, c->x86_capability); 97 98 r = get_model_name(c); 99 100 switch(c->x86) 101 { 102 case 4: 103 /* 104 * General Systems BIOSen alias the cpu frequency registers 105 * of the Elan at 0x000df000. Unfortuantly, one of the Linux 106 * drivers subsequently pokes it, and changes the CPU speed. 107 * Workaround : Remove the unneeded alias. 108 */ 109 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 110 #define CBAR_ENB (0x80000000) 111 #define CBAR_KEY (0X000000CB) 112 if (c->x86_model==9 || c->x86_model == 10) { 113 if (inl (CBAR) & CBAR_ENB) 114 outl (0 | CBAR_KEY, CBAR); 115 } 116 break; 117 case 5: 118 if( c->x86_model < 6 ) 119 { 120 /* Based on AMD doc 20734R - June 2000 */ 121 if ( c->x86_model == 0 ) { 122 clear_bit(X86_FEATURE_APIC, c->x86_capability); 123 set_bit(X86_FEATURE_PGE, c->x86_capability); 124 } 125 break; 126 } 127 128 if ( c->x86_model == 6 && c->x86_mask == 1 ) { 129 const int K6_BUG_LOOP = 1000000; 130 int n; 131 void (*f_vide)(void); 132 unsigned long d, d2; 133 134 printk(KERN_INFO "AMD K6 stepping B detected - "); 135 136 /* 137 * It looks like AMD fixed the 2.6.2 bug and improved indirect 138 * calls at the same time. 139 */ 140 141 n = K6_BUG_LOOP; 142 f_vide = vide; 143 rdtscl(d); 144 while (n--) 145 f_vide(); 146 rdtscl(d2); 147 d = d2-d; 148 149 if (d > 20*K6_BUG_LOOP) 150 printk("system stability may be impaired when more than 32 MB are used.\n"); 151 else 152 printk("probably OK (after B9730xxxx).\n"); 153 printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n"); 154 } 155 156 /* K6 with old style WHCR */ 157 if (c->x86_model < 8 || 158 (c->x86_model== 8 && c->x86_mask < 8)) { 159 /* We can only write allocate on the low 508Mb */ 160 if(mbytes>508) 161 mbytes=508; 162 163 rdmsr(MSR_K6_WHCR, l, h); 164 if ((l&0x0000FFFF)==0) { 165 unsigned long flags; 166 l=(1<<0)|((mbytes/4)<<1); 167 local_irq_save(flags); 168 wbinvd(); 169 wrmsr(MSR_K6_WHCR, l, h); 170 local_irq_restore(flags); 171 printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n", 172 mbytes); 173 } 174 break; 175 } 176 177 if ((c->x86_model == 8 && c->x86_mask >7) || 178 c->x86_model == 9 || c->x86_model == 13) { 179 /* The more serious chips .. */ 180 181 if(mbytes>4092) 182 mbytes=4092; 183 184 rdmsr(MSR_K6_WHCR, l, h); 185 if ((l&0xFFFF0000)==0) { 186 unsigned long flags; 187 l=((mbytes>>2)<<22)|(1<<16); 188 local_irq_save(flags); 189 wbinvd(); 190 wrmsr(MSR_K6_WHCR, l, h); 191 local_irq_restore(flags); 192 printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n", 193 mbytes); 194 } 195 196 /* Set MTRR capability flag if appropriate */ 197 if (c->x86_model == 13 || c->x86_model == 9 || 198 (c->x86_model == 8 && c->x86_mask >= 8)) 199 set_bit(X86_FEATURE_K6_MTRR, c->x86_capability); 200 break; 201 } 202 203 if (c->x86_model == 10) { 204 /* AMD Geode LX is model 10 */ 205 /* placeholder for any needed mods */ 206 break; 207 } 208 break; 209 case 6: /* An Athlon/Duron */ 210 211 /* Bit 15 of Athlon specific MSR 15, needs to be 0 212 * to enable SSE on Palomino/Morgan/Barton CPU's. 213 * If the BIOS didn't enable it already, enable it here. 214 */ 215 if (c->x86_model >= 6 && c->x86_model <= 10) { 216 if (!cpu_has(c, X86_FEATURE_XMM)) { 217 printk(KERN_INFO "Enabling disabled K7/SSE Support.\n"); 218 rdmsr(MSR_K7_HWCR, l, h); 219 l &= ~0x00008000; 220 wrmsr(MSR_K7_HWCR, l, h); 221 set_bit(X86_FEATURE_XMM, c->x86_capability); 222 } 223 } 224 225 /* It's been determined by AMD that Athlons since model 8 stepping 1 226 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 227 * As per AMD technical note 27212 0.2 228 */ 229 if ((c->x86_model == 8 && c->x86_mask>=1) || (c->x86_model > 8)) { 230 rdmsr(MSR_K7_CLK_CTL, l, h); 231 if ((l & 0xfff00000) != 0x20000000) { 232 printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l, 233 ((l & 0x000fffff)|0x20000000)); 234 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 235 } 236 } 237 break; 238 } 239 240 switch (c->x86) { 241 case 15: 242 /* Use K8 tuning for Fam10h and Fam11h */ 243 case 0x10: 244 case 0x11: 245 set_bit(X86_FEATURE_K8, c->x86_capability); 246 break; 247 case 6: 248 set_bit(X86_FEATURE_K7, c->x86_capability); 249 break; 250 } 251 if (c->x86 >= 6) 252 set_bit(X86_FEATURE_FXSAVE_LEAK, c->x86_capability); 253 254 display_cacheinfo(c); 255 256 if (cpuid_eax(0x80000000) >= 0x80000008) { 257 c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1; 258 } 259 260 if (cpuid_eax(0x80000000) >= 0x80000007) { 261 c->x86_power = cpuid_edx(0x80000007); 262 if (c->x86_power & (1<<8)) 263 set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability); 264 } 265 266 #ifdef CONFIG_X86_HT 267 /* 268 * On a AMD multi core setup the lower bits of the APIC id 269 * distinguish the cores. 270 */ 271 if (c->x86_max_cores > 1) { 272 int cpu = smp_processor_id(); 273 unsigned bits = (cpuid_ecx(0x80000008) >> 12) & 0xf; 274 275 if (bits == 0) { 276 while ((1 << bits) < c->x86_max_cores) 277 bits++; 278 } 279 c->cpu_core_id = c->phys_proc_id & ((1<<bits)-1); 280 c->phys_proc_id >>= bits; 281 printk(KERN_INFO "CPU %d(%d) -> Core %d\n", 282 cpu, c->x86_max_cores, c->cpu_core_id); 283 } 284 #endif 285 286 if (cpuid_eax(0x80000000) >= 0x80000006) { 287 if ((c->x86 == 0x10) && (cpuid_edx(0x80000006) & 0xf000)) 288 num_cache_leaves = 4; 289 else 290 num_cache_leaves = 3; 291 } 292 293 #ifdef CONFIG_X86_LOCAL_APIC 294 if (amd_apic_timer_broken()) 295 local_apic_timer_disabled = 1; 296 #endif 297 298 if (c->x86 == 0x10 && !force_mwait) 299 clear_bit(X86_FEATURE_MWAIT, c->x86_capability); 300 301 /* K6s reports MCEs but don't actually have all the MSRs */ 302 if (c->x86 < 6) 303 clear_bit(X86_FEATURE_MCE, c->x86_capability); 304 } 305 306 static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 * c, unsigned int size) 307 { 308 /* AMD errata T13 (order #21922) */ 309 if ((c->x86 == 6)) { 310 if (c->x86_model == 3 && c->x86_mask == 0) /* Duron Rev A0 */ 311 size = 64; 312 if (c->x86_model == 4 && 313 (c->x86_mask==0 || c->x86_mask==1)) /* Tbird rev A1/A2 */ 314 size = 256; 315 } 316 return size; 317 } 318 319 static struct cpu_dev amd_cpu_dev __cpuinitdata = { 320 .c_vendor = "AMD", 321 .c_ident = { "AuthenticAMD" }, 322 .c_models = { 323 { .vendor = X86_VENDOR_AMD, .family = 4, .model_names = 324 { 325 [3] = "486 DX/2", 326 [7] = "486 DX/2-WB", 327 [8] = "486 DX/4", 328 [9] = "486 DX/4-WB", 329 [14] = "Am5x86-WT", 330 [15] = "Am5x86-WB" 331 } 332 }, 333 }, 334 .c_init = init_amd, 335 .c_size_cache = amd_size_cache, 336 }; 337 338 int __init amd_init_cpu(void) 339 { 340 cpu_devs[X86_VENDOR_AMD] = &amd_cpu_dev; 341 return 0; 342 } 343