1 #include <linux/export.h> 2 #include <linux/bitops.h> 3 #include <linux/elf.h> 4 #include <linux/mm.h> 5 6 #include <linux/io.h> 7 #include <linux/sched.h> 8 #include <linux/sched/clock.h> 9 #include <linux/random.h> 10 #include <asm/processor.h> 11 #include <asm/apic.h> 12 #include <asm/cacheinfo.h> 13 #include <asm/cpu.h> 14 #include <asm/spec-ctrl.h> 15 #include <asm/smp.h> 16 #include <asm/pci-direct.h> 17 #include <asm/delay.h> 18 19 #ifdef CONFIG_X86_64 20 # include <asm/mmconfig.h> 21 # include <asm/set_memory.h> 22 #endif 23 24 #include "cpu.h" 25 26 static const int amd_erratum_383[]; 27 static const int amd_erratum_400[]; 28 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); 29 30 /* 31 * nodes_per_socket: Stores the number of nodes per socket. 32 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX 33 * Node Identifiers[10:8] 34 */ 35 static u32 nodes_per_socket = 1; 36 37 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) 38 { 39 u32 gprs[8] = { 0 }; 40 int err; 41 42 WARN_ONCE((boot_cpu_data.x86 != 0xf), 43 "%s should only be used on K8!\n", __func__); 44 45 gprs[1] = msr; 46 gprs[7] = 0x9c5a203a; 47 48 err = rdmsr_safe_regs(gprs); 49 50 *p = gprs[0] | ((u64)gprs[2] << 32); 51 52 return err; 53 } 54 55 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) 56 { 57 u32 gprs[8] = { 0 }; 58 59 WARN_ONCE((boot_cpu_data.x86 != 0xf), 60 "%s should only be used on K8!\n", __func__); 61 62 gprs[0] = (u32)val; 63 gprs[1] = msr; 64 gprs[2] = val >> 32; 65 gprs[7] = 0x9c5a203a; 66 67 return wrmsr_safe_regs(gprs); 68 } 69 70 /* 71 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 72 * misexecution of code under Linux. Owners of such processors should 73 * contact AMD for precise details and a CPU swap. 74 * 75 * See http://www.multimania.com/poulot/k6bug.html 76 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" 77 * (Publication # 21266 Issue Date: August 1998) 78 * 79 * The following test is erm.. interesting. AMD neglected to up 80 * the chip setting when fixing the bug but they also tweaked some 81 * performance at the same time.. 82 */ 83 84 extern __visible void vide(void); 85 __asm__(".globl vide\n" 86 ".type vide, @function\n" 87 ".align 4\n" 88 "vide: ret\n"); 89 90 static void init_amd_k5(struct cpuinfo_x86 *c) 91 { 92 #ifdef CONFIG_X86_32 93 /* 94 * General Systems BIOSen alias the cpu frequency registers 95 * of the Elan at 0x000df000. Unfortunately, one of the Linux 96 * drivers subsequently pokes it, and changes the CPU speed. 97 * Workaround : Remove the unneeded alias. 98 */ 99 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 100 #define CBAR_ENB (0x80000000) 101 #define CBAR_KEY (0X000000CB) 102 if (c->x86_model == 9 || c->x86_model == 10) { 103 if (inl(CBAR) & CBAR_ENB) 104 outl(0 | CBAR_KEY, CBAR); 105 } 106 #endif 107 } 108 109 static void init_amd_k6(struct cpuinfo_x86 *c) 110 { 111 #ifdef CONFIG_X86_32 112 u32 l, h; 113 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); 114 115 if (c->x86_model < 6) { 116 /* Based on AMD doc 20734R - June 2000 */ 117 if (c->x86_model == 0) { 118 clear_cpu_cap(c, X86_FEATURE_APIC); 119 set_cpu_cap(c, X86_FEATURE_PGE); 120 } 121 return; 122 } 123 124 if (c->x86_model == 6 && c->x86_stepping == 1) { 125 const int K6_BUG_LOOP = 1000000; 126 int n; 127 void (*f_vide)(void); 128 u64 d, d2; 129 130 pr_info("AMD K6 stepping B detected - "); 131 132 /* 133 * It looks like AMD fixed the 2.6.2 bug and improved indirect 134 * calls at the same time. 135 */ 136 137 n = K6_BUG_LOOP; 138 f_vide = vide; 139 OPTIMIZER_HIDE_VAR(f_vide); 140 d = rdtsc(); 141 while (n--) 142 f_vide(); 143 d2 = rdtsc(); 144 d = d2-d; 145 146 if (d > 20*K6_BUG_LOOP) 147 pr_cont("system stability may be impaired when more than 32 MB are used.\n"); 148 else 149 pr_cont("probably OK (after B9730xxxx).\n"); 150 } 151 152 /* K6 with old style WHCR */ 153 if (c->x86_model < 8 || 154 (c->x86_model == 8 && c->x86_stepping < 8)) { 155 /* We can only write allocate on the low 508Mb */ 156 if (mbytes > 508) 157 mbytes = 508; 158 159 rdmsr(MSR_K6_WHCR, l, h); 160 if ((l&0x0000FFFF) == 0) { 161 unsigned long flags; 162 l = (1<<0)|((mbytes/4)<<1); 163 local_irq_save(flags); 164 wbinvd(); 165 wrmsr(MSR_K6_WHCR, l, h); 166 local_irq_restore(flags); 167 pr_info("Enabling old style K6 write allocation for %d Mb\n", 168 mbytes); 169 } 170 return; 171 } 172 173 if ((c->x86_model == 8 && c->x86_stepping > 7) || 174 c->x86_model == 9 || c->x86_model == 13) { 175 /* The more serious chips .. */ 176 177 if (mbytes > 4092) 178 mbytes = 4092; 179 180 rdmsr(MSR_K6_WHCR, l, h); 181 if ((l&0xFFFF0000) == 0) { 182 unsigned long flags; 183 l = ((mbytes>>2)<<22)|(1<<16); 184 local_irq_save(flags); 185 wbinvd(); 186 wrmsr(MSR_K6_WHCR, l, h); 187 local_irq_restore(flags); 188 pr_info("Enabling new style K6 write allocation for %d Mb\n", 189 mbytes); 190 } 191 192 return; 193 } 194 195 if (c->x86_model == 10) { 196 /* AMD Geode LX is model 10 */ 197 /* placeholder for any needed mods */ 198 return; 199 } 200 #endif 201 } 202 203 static void init_amd_k7(struct cpuinfo_x86 *c) 204 { 205 #ifdef CONFIG_X86_32 206 u32 l, h; 207 208 /* 209 * Bit 15 of Athlon specific MSR 15, needs to be 0 210 * to enable SSE on Palomino/Morgan/Barton CPU's. 211 * If the BIOS didn't enable it already, enable it here. 212 */ 213 if (c->x86_model >= 6 && c->x86_model <= 10) { 214 if (!cpu_has(c, X86_FEATURE_XMM)) { 215 pr_info("Enabling disabled K7/SSE Support.\n"); 216 msr_clear_bit(MSR_K7_HWCR, 15); 217 set_cpu_cap(c, X86_FEATURE_XMM); 218 } 219 } 220 221 /* 222 * It's been determined by AMD that Athlons since model 8 stepping 1 223 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 224 * As per AMD technical note 27212 0.2 225 */ 226 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) { 227 rdmsr(MSR_K7_CLK_CTL, l, h); 228 if ((l & 0xfff00000) != 0x20000000) { 229 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", 230 l, ((l & 0x000fffff)|0x20000000)); 231 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 232 } 233 } 234 235 /* calling is from identify_secondary_cpu() ? */ 236 if (!c->cpu_index) 237 return; 238 239 /* 240 * Certain Athlons might work (for various values of 'work') in SMP 241 * but they are not certified as MP capable. 242 */ 243 /* Athlon 660/661 is valid. */ 244 if ((c->x86_model == 6) && ((c->x86_stepping == 0) || 245 (c->x86_stepping == 1))) 246 return; 247 248 /* Duron 670 is valid */ 249 if ((c->x86_model == 7) && (c->x86_stepping == 0)) 250 return; 251 252 /* 253 * Athlon 662, Duron 671, and Athlon >model 7 have capability 254 * bit. It's worth noting that the A5 stepping (662) of some 255 * Athlon XP's have the MP bit set. 256 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for 257 * more. 258 */ 259 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) || 260 ((c->x86_model == 7) && (c->x86_stepping >= 1)) || 261 (c->x86_model > 7)) 262 if (cpu_has(c, X86_FEATURE_MP)) 263 return; 264 265 /* If we get here, not a certified SMP capable AMD system. */ 266 267 /* 268 * Don't taint if we are running SMP kernel on a single non-MP 269 * approved Athlon 270 */ 271 WARN_ONCE(1, "WARNING: This combination of AMD" 272 " processors is not suitable for SMP.\n"); 273 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 274 #endif 275 } 276 277 #ifdef CONFIG_NUMA 278 /* 279 * To workaround broken NUMA config. Read the comment in 280 * srat_detect_node(). 281 */ 282 static int nearby_node(int apicid) 283 { 284 int i, node; 285 286 for (i = apicid - 1; i >= 0; i--) { 287 node = __apicid_to_node[i]; 288 if (node != NUMA_NO_NODE && node_online(node)) 289 return node; 290 } 291 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 292 node = __apicid_to_node[i]; 293 if (node != NUMA_NO_NODE && node_online(node)) 294 return node; 295 } 296 return first_node(node_online_map); /* Shouldn't happen */ 297 } 298 #endif 299 300 /* 301 * Fix up cpu_core_id for pre-F17h systems to be in the 302 * [0 .. cores_per_node - 1] range. Not really needed but 303 * kept so as not to break existing setups. 304 */ 305 static void legacy_fixup_core_id(struct cpuinfo_x86 *c) 306 { 307 u32 cus_per_node; 308 309 if (c->x86 >= 0x17) 310 return; 311 312 cus_per_node = c->x86_max_cores / nodes_per_socket; 313 c->cpu_core_id %= cus_per_node; 314 } 315 316 /* 317 * Fixup core topology information for 318 * (1) AMD multi-node processors 319 * Assumption: Number of cores in each internal node is the same. 320 * (2) AMD processors supporting compute units 321 */ 322 static void amd_get_topology(struct cpuinfo_x86 *c) 323 { 324 u8 node_id; 325 int cpu = smp_processor_id(); 326 327 /* get information required for multi-node processors */ 328 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 329 int err; 330 u32 eax, ebx, ecx, edx; 331 332 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); 333 334 node_id = ecx & 0xff; 335 smp_num_siblings = ((ebx >> 8) & 0xff) + 1; 336 337 if (c->x86 == 0x15) 338 c->cu_id = ebx & 0xff; 339 340 if (c->x86 >= 0x17) { 341 c->cpu_core_id = ebx & 0xff; 342 343 if (smp_num_siblings > 1) 344 c->x86_max_cores /= smp_num_siblings; 345 } 346 347 /* 348 * In case leaf B is available, use it to derive 349 * topology information. 350 */ 351 err = detect_extended_topology(c); 352 if (!err) 353 c->x86_coreid_bits = get_count_order(c->x86_max_cores); 354 355 cacheinfo_amd_init_llc_id(c, cpu, node_id); 356 357 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { 358 u64 value; 359 360 rdmsrl(MSR_FAM10H_NODE_ID, value); 361 node_id = value & 7; 362 363 per_cpu(cpu_llc_id, cpu) = node_id; 364 } else 365 return; 366 367 if (nodes_per_socket > 1) { 368 set_cpu_cap(c, X86_FEATURE_AMD_DCM); 369 legacy_fixup_core_id(c); 370 } 371 } 372 373 /* 374 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores. 375 * Assumes number of cores is a power of two. 376 */ 377 static void amd_detect_cmp(struct cpuinfo_x86 *c) 378 { 379 unsigned bits; 380 int cpu = smp_processor_id(); 381 382 bits = c->x86_coreid_bits; 383 /* Low order bits define the core id (index of core in socket) */ 384 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); 385 /* Convert the initial APIC ID into the socket ID */ 386 c->phys_proc_id = c->initial_apicid >> bits; 387 /* use socket ID also for last level cache */ 388 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; 389 } 390 391 u16 amd_get_nb_id(int cpu) 392 { 393 return per_cpu(cpu_llc_id, cpu); 394 } 395 EXPORT_SYMBOL_GPL(amd_get_nb_id); 396 397 u32 amd_get_nodes_per_socket(void) 398 { 399 return nodes_per_socket; 400 } 401 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket); 402 403 static void srat_detect_node(struct cpuinfo_x86 *c) 404 { 405 #ifdef CONFIG_NUMA 406 int cpu = smp_processor_id(); 407 int node; 408 unsigned apicid = c->apicid; 409 410 node = numa_cpu_node(cpu); 411 if (node == NUMA_NO_NODE) 412 node = per_cpu(cpu_llc_id, cpu); 413 414 /* 415 * On multi-fabric platform (e.g. Numascale NumaChip) a 416 * platform-specific handler needs to be called to fixup some 417 * IDs of the CPU. 418 */ 419 if (x86_cpuinit.fixup_cpu_id) 420 x86_cpuinit.fixup_cpu_id(c, node); 421 422 if (!node_online(node)) { 423 /* 424 * Two possibilities here: 425 * 426 * - The CPU is missing memory and no node was created. In 427 * that case try picking one from a nearby CPU. 428 * 429 * - The APIC IDs differ from the HyperTransport node IDs 430 * which the K8 northbridge parsing fills in. Assume 431 * they are all increased by a constant offset, but in 432 * the same order as the HT nodeids. If that doesn't 433 * result in a usable node fall back to the path for the 434 * previous case. 435 * 436 * This workaround operates directly on the mapping between 437 * APIC ID and NUMA node, assuming certain relationship 438 * between APIC ID, HT node ID and NUMA topology. As going 439 * through CPU mapping may alter the outcome, directly 440 * access __apicid_to_node[]. 441 */ 442 int ht_nodeid = c->initial_apicid; 443 444 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 445 node = __apicid_to_node[ht_nodeid]; 446 /* Pick a nearby node */ 447 if (!node_online(node)) 448 node = nearby_node(apicid); 449 } 450 numa_set_node(cpu, node); 451 #endif 452 } 453 454 static void early_init_amd_mc(struct cpuinfo_x86 *c) 455 { 456 #ifdef CONFIG_SMP 457 unsigned bits, ecx; 458 459 /* Multi core CPU? */ 460 if (c->extended_cpuid_level < 0x80000008) 461 return; 462 463 ecx = cpuid_ecx(0x80000008); 464 465 c->x86_max_cores = (ecx & 0xff) + 1; 466 467 /* CPU telling us the core id bits shift? */ 468 bits = (ecx >> 12) & 0xF; 469 470 /* Otherwise recompute */ 471 if (bits == 0) { 472 while ((1 << bits) < c->x86_max_cores) 473 bits++; 474 } 475 476 c->x86_coreid_bits = bits; 477 #endif 478 } 479 480 static void bsp_init_amd(struct cpuinfo_x86 *c) 481 { 482 483 #ifdef CONFIG_X86_64 484 if (c->x86 >= 0xf) { 485 unsigned long long tseg; 486 487 /* 488 * Split up direct mapping around the TSEG SMM area. 489 * Don't do it for gbpages because there seems very little 490 * benefit in doing so. 491 */ 492 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { 493 unsigned long pfn = tseg >> PAGE_SHIFT; 494 495 pr_debug("tseg: %010llx\n", tseg); 496 if (pfn_range_is_mapped(pfn, pfn + 1)) 497 set_memory_4k((unsigned long)__va(tseg), 1); 498 } 499 } 500 #endif 501 502 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 503 504 if (c->x86 > 0x10 || 505 (c->x86 == 0x10 && c->x86_model >= 0x2)) { 506 u64 val; 507 508 rdmsrl(MSR_K7_HWCR, val); 509 if (!(val & BIT(24))) 510 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); 511 } 512 } 513 514 if (c->x86 == 0x15) { 515 unsigned long upperbit; 516 u32 cpuid, assoc; 517 518 cpuid = cpuid_edx(0x80000005); 519 assoc = cpuid >> 16 & 0xff; 520 upperbit = ((cpuid >> 24) << 10) / assoc; 521 522 va_align.mask = (upperbit - 1) & PAGE_MASK; 523 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; 524 525 /* A random value per boot for bit slice [12:upper_bit) */ 526 va_align.bits = get_random_int() & va_align.mask; 527 } 528 529 if (cpu_has(c, X86_FEATURE_MWAITX)) 530 use_mwaitx_delay(); 531 532 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 533 u32 ecx; 534 535 ecx = cpuid_ecx(0x8000001e); 536 nodes_per_socket = ((ecx >> 8) & 7) + 1; 537 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) { 538 u64 value; 539 540 rdmsrl(MSR_FAM10H_NODE_ID, value); 541 nodes_per_socket = ((value >> 3) & 7) + 1; 542 } 543 544 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) && 545 !boot_cpu_has(X86_FEATURE_VIRT_SSBD) && 546 c->x86 >= 0x15 && c->x86 <= 0x17) { 547 unsigned int bit; 548 549 switch (c->x86) { 550 case 0x15: bit = 54; break; 551 case 0x16: bit = 33; break; 552 case 0x17: bit = 10; break; 553 default: return; 554 } 555 /* 556 * Try to cache the base value so further operations can 557 * avoid RMW. If that faults, do not enable SSBD. 558 */ 559 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) { 560 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD); 561 setup_force_cpu_cap(X86_FEATURE_SSBD); 562 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit; 563 } 564 } 565 } 566 567 static void early_detect_mem_encrypt(struct cpuinfo_x86 *c) 568 { 569 u64 msr; 570 571 /* 572 * BIOS support is required for SME and SEV. 573 * For SME: If BIOS has enabled SME then adjust x86_phys_bits by 574 * the SME physical address space reduction value. 575 * If BIOS has not enabled SME then don't advertise the 576 * SME feature (set in scattered.c). 577 * For SEV: If BIOS has not enabled SEV then don't advertise the 578 * SEV feature (set in scattered.c). 579 * 580 * In all cases, since support for SME and SEV requires long mode, 581 * don't advertise the feature under CONFIG_X86_32. 582 */ 583 if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) { 584 /* Check if memory encryption is enabled */ 585 rdmsrl(MSR_K8_SYSCFG, msr); 586 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT)) 587 goto clear_all; 588 589 /* 590 * Always adjust physical address bits. Even though this 591 * will be a value above 32-bits this is still done for 592 * CONFIG_X86_32 so that accurate values are reported. 593 */ 594 c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f; 595 596 if (IS_ENABLED(CONFIG_X86_32)) 597 goto clear_all; 598 599 rdmsrl(MSR_K7_HWCR, msr); 600 if (!(msr & MSR_K7_HWCR_SMMLOCK)) 601 goto clear_sev; 602 603 return; 604 605 clear_all: 606 clear_cpu_cap(c, X86_FEATURE_SME); 607 clear_sev: 608 clear_cpu_cap(c, X86_FEATURE_SEV); 609 } 610 } 611 612 static void early_init_amd(struct cpuinfo_x86 *c) 613 { 614 u32 dummy; 615 616 early_init_amd_mc(c); 617 618 #ifdef CONFIG_X86_32 619 if (c->x86 == 6) 620 set_cpu_cap(c, X86_FEATURE_K7); 621 #endif 622 623 if (c->x86 >= 0xf) 624 set_cpu_cap(c, X86_FEATURE_K8); 625 626 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); 627 628 /* 629 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 630 * with P/T states and does not stop in deep C-states 631 */ 632 if (c->x86_power & (1 << 8)) { 633 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 634 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 635 } 636 637 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ 638 if (c->x86_power & BIT(12)) 639 set_cpu_cap(c, X86_FEATURE_ACC_POWER); 640 641 #ifdef CONFIG_X86_64 642 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 643 #else 644 /* Set MTRR capability flag if appropriate */ 645 if (c->x86 == 5) 646 if (c->x86_model == 13 || c->x86_model == 9 || 647 (c->x86_model == 8 && c->x86_stepping >= 8)) 648 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 649 #endif 650 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 651 /* 652 * ApicID can always be treated as an 8-bit value for AMD APIC versions 653 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we 654 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families 655 * after 16h. 656 */ 657 if (boot_cpu_has(X86_FEATURE_APIC)) { 658 if (c->x86 > 0x16) 659 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 660 else if (c->x86 >= 0xf) { 661 /* check CPU config space for extended APIC ID */ 662 unsigned int val; 663 664 val = read_pci_config(0, 24, 0, 0x68); 665 if ((val >> 17 & 0x3) == 0x3) 666 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 667 } 668 } 669 #endif 670 671 /* 672 * This is only needed to tell the kernel whether to use VMCALL 673 * and VMMCALL. VMMCALL is never executed except under virt, so 674 * we can set it unconditionally. 675 */ 676 set_cpu_cap(c, X86_FEATURE_VMMCALL); 677 678 /* F16h erratum 793, CVE-2013-6885 */ 679 if (c->x86 == 0x16 && c->x86_model <= 0xf) 680 msr_set_bit(MSR_AMD64_LS_CFG, 15); 681 682 /* 683 * Check whether the machine is affected by erratum 400. This is 684 * used to select the proper idle routine and to enable the check 685 * whether the machine is affected in arch_post_acpi_init(), which 686 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check. 687 */ 688 if (cpu_has_amd_erratum(c, amd_erratum_400)) 689 set_cpu_bug(c, X86_BUG_AMD_E400); 690 691 early_detect_mem_encrypt(c); 692 } 693 694 static void init_amd_k8(struct cpuinfo_x86 *c) 695 { 696 u32 level; 697 u64 value; 698 699 /* On C+ stepping K8 rep microcode works well for copy/memset */ 700 level = cpuid_eax(1); 701 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) 702 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 703 704 /* 705 * Some BIOSes incorrectly force this feature, but only K8 revision D 706 * (model = 0x14) and later actually support it. 707 * (AMD Erratum #110, docId: 25759). 708 */ 709 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { 710 clear_cpu_cap(c, X86_FEATURE_LAHF_LM); 711 if (!rdmsrl_amd_safe(0xc001100d, &value)) { 712 value &= ~BIT_64(32); 713 wrmsrl_amd_safe(0xc001100d, value); 714 } 715 } 716 717 if (!c->x86_model_id[0]) 718 strcpy(c->x86_model_id, "Hammer"); 719 720 #ifdef CONFIG_SMP 721 /* 722 * Disable TLB flush filter by setting HWCR.FFDIS on K8 723 * bit 6 of msr C001_0015 724 * 725 * Errata 63 for SH-B3 steppings 726 * Errata 122 for all steppings (F+ have it disabled by default) 727 */ 728 msr_set_bit(MSR_K7_HWCR, 6); 729 #endif 730 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE); 731 } 732 733 static void init_amd_gh(struct cpuinfo_x86 *c) 734 { 735 #ifdef CONFIG_MMCONF_FAM10H 736 /* do this for boot cpu */ 737 if (c == &boot_cpu_data) 738 check_enable_amd_mmconf_dmi(); 739 740 fam10h_check_enable_mmcfg(); 741 #endif 742 743 /* 744 * Disable GART TLB Walk Errors on Fam10h. We do this here because this 745 * is always needed when GART is enabled, even in a kernel which has no 746 * MCE support built in. BIOS should disable GartTlbWlk Errors already. 747 * If it doesn't, we do it here as suggested by the BKDG. 748 * 749 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 750 */ 751 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10); 752 753 /* 754 * On family 10h BIOS may not have properly enabled WC+ support, causing 755 * it to be converted to CD memtype. This may result in performance 756 * degradation for certain nested-paging guests. Prevent this conversion 757 * by clearing bit 24 in MSR_AMD64_BU_CFG2. 758 * 759 * NOTE: we want to use the _safe accessors so as not to #GP kvm 760 * guests on older kvm hosts. 761 */ 762 msr_clear_bit(MSR_AMD64_BU_CFG2, 24); 763 764 if (cpu_has_amd_erratum(c, amd_erratum_383)) 765 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH); 766 } 767 768 #define MSR_AMD64_DE_CFG 0xC0011029 769 770 static void init_amd_ln(struct cpuinfo_x86 *c) 771 { 772 /* 773 * Apply erratum 665 fix unconditionally so machines without a BIOS 774 * fix work. 775 */ 776 msr_set_bit(MSR_AMD64_DE_CFG, 31); 777 } 778 779 static void init_amd_bd(struct cpuinfo_x86 *c) 780 { 781 u64 value; 782 783 /* re-enable TopologyExtensions if switched off by BIOS */ 784 if ((c->x86_model >= 0x10) && (c->x86_model <= 0x6f) && 785 !cpu_has(c, X86_FEATURE_TOPOEXT)) { 786 787 if (msr_set_bit(0xc0011005, 54) > 0) { 788 rdmsrl(0xc0011005, value); 789 if (value & BIT_64(54)) { 790 set_cpu_cap(c, X86_FEATURE_TOPOEXT); 791 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n"); 792 } 793 } 794 } 795 796 /* 797 * The way access filter has a performance penalty on some workloads. 798 * Disable it on the affected CPUs. 799 */ 800 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) { 801 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) { 802 value |= 0x1E; 803 wrmsrl_safe(MSR_F15H_IC_CFG, value); 804 } 805 } 806 } 807 808 static void init_amd_zn(struct cpuinfo_x86 *c) 809 { 810 set_cpu_cap(c, X86_FEATURE_ZEN); 811 /* 812 * Fix erratum 1076: CPB feature bit not being set in CPUID. It affects 813 * all up to and including B1. 814 */ 815 if (c->x86_model <= 1 && c->x86_stepping <= 1) 816 set_cpu_cap(c, X86_FEATURE_CPB); 817 } 818 819 static void init_amd(struct cpuinfo_x86 *c) 820 { 821 early_init_amd(c); 822 823 /* 824 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 825 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 826 */ 827 clear_cpu_cap(c, 0*32+31); 828 829 if (c->x86 >= 0x10) 830 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 831 832 /* get apicid instead of initial apic id from cpuid */ 833 c->apicid = hard_smp_processor_id(); 834 835 /* K6s reports MCEs but don't actually have all the MSRs */ 836 if (c->x86 < 6) 837 clear_cpu_cap(c, X86_FEATURE_MCE); 838 839 switch (c->x86) { 840 case 4: init_amd_k5(c); break; 841 case 5: init_amd_k6(c); break; 842 case 6: init_amd_k7(c); break; 843 case 0xf: init_amd_k8(c); break; 844 case 0x10: init_amd_gh(c); break; 845 case 0x12: init_amd_ln(c); break; 846 case 0x15: init_amd_bd(c); break; 847 case 0x17: init_amd_zn(c); break; 848 } 849 850 /* 851 * Enable workaround for FXSAVE leak on CPUs 852 * without a XSaveErPtr feature 853 */ 854 if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR))) 855 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK); 856 857 cpu_detect_cache_sizes(c); 858 859 /* Multi core CPU? */ 860 if (c->extended_cpuid_level >= 0x80000008) { 861 amd_detect_cmp(c); 862 amd_get_topology(c); 863 srat_detect_node(c); 864 } 865 866 #ifdef CONFIG_X86_32 867 detect_ht(c); 868 #endif 869 870 init_amd_cacheinfo(c); 871 872 if (cpu_has(c, X86_FEATURE_XMM2)) { 873 unsigned long long val; 874 int ret; 875 876 /* 877 * A serializing LFENCE has less overhead than MFENCE, so 878 * use it for execution serialization. On families which 879 * don't have that MSR, LFENCE is already serializing. 880 * msr_set_bit() uses the safe accessors, too, even if the MSR 881 * is not present. 882 */ 883 msr_set_bit(MSR_F10H_DECFG, 884 MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT); 885 886 /* 887 * Verify that the MSR write was successful (could be running 888 * under a hypervisor) and only then assume that LFENCE is 889 * serializing. 890 */ 891 ret = rdmsrl_safe(MSR_F10H_DECFG, &val); 892 if (!ret && (val & MSR_F10H_DECFG_LFENCE_SERIALIZE)) { 893 /* A serializing LFENCE stops RDTSC speculation */ 894 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 895 } else { 896 /* MFENCE stops RDTSC speculation */ 897 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); 898 } 899 } 900 901 /* 902 * Family 0x12 and above processors have APIC timer 903 * running in deep C states. 904 */ 905 if (c->x86 > 0x11) 906 set_cpu_cap(c, X86_FEATURE_ARAT); 907 908 /* 3DNow or LM implies PREFETCHW */ 909 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH)) 910 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM)) 911 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH); 912 913 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */ 914 if (!cpu_has(c, X86_FEATURE_XENPV)) 915 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); 916 } 917 918 #ifdef CONFIG_X86_32 919 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) 920 { 921 /* AMD errata T13 (order #21922) */ 922 if ((c->x86 == 6)) { 923 /* Duron Rev A0 */ 924 if (c->x86_model == 3 && c->x86_stepping == 0) 925 size = 64; 926 /* Tbird rev A1/A2 */ 927 if (c->x86_model == 4 && 928 (c->x86_stepping == 0 || c->x86_stepping == 1)) 929 size = 256; 930 } 931 return size; 932 } 933 #endif 934 935 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) 936 { 937 u32 ebx, eax, ecx, edx; 938 u16 mask = 0xfff; 939 940 if (c->x86 < 0xf) 941 return; 942 943 if (c->extended_cpuid_level < 0x80000006) 944 return; 945 946 cpuid(0x80000006, &eax, &ebx, &ecx, &edx); 947 948 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask; 949 tlb_lli_4k[ENTRIES] = ebx & mask; 950 951 /* 952 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB 953 * characteristics from the CPUID function 0x80000005 instead. 954 */ 955 if (c->x86 == 0xf) { 956 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 957 mask = 0xff; 958 } 959 960 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 961 if (!((eax >> 16) & mask)) 962 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff; 963 else 964 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask; 965 966 /* a 4M entry uses two 2M entries */ 967 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1; 968 969 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 970 if (!(eax & mask)) { 971 /* Erratum 658 */ 972 if (c->x86 == 0x15 && c->x86_model <= 0x1f) { 973 tlb_lli_2m[ENTRIES] = 1024; 974 } else { 975 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 976 tlb_lli_2m[ENTRIES] = eax & 0xff; 977 } 978 } else 979 tlb_lli_2m[ENTRIES] = eax & mask; 980 981 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; 982 } 983 984 static const struct cpu_dev amd_cpu_dev = { 985 .c_vendor = "AMD", 986 .c_ident = { "AuthenticAMD" }, 987 #ifdef CONFIG_X86_32 988 .legacy_models = { 989 { .family = 4, .model_names = 990 { 991 [3] = "486 DX/2", 992 [7] = "486 DX/2-WB", 993 [8] = "486 DX/4", 994 [9] = "486 DX/4-WB", 995 [14] = "Am5x86-WT", 996 [15] = "Am5x86-WB" 997 } 998 }, 999 }, 1000 .legacy_cache_size = amd_size_cache, 1001 #endif 1002 .c_early_init = early_init_amd, 1003 .c_detect_tlb = cpu_detect_tlb_amd, 1004 .c_bsp_init = bsp_init_amd, 1005 .c_init = init_amd, 1006 .c_x86_vendor = X86_VENDOR_AMD, 1007 }; 1008 1009 cpu_dev_register(amd_cpu_dev); 1010 1011 /* 1012 * AMD errata checking 1013 * 1014 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or 1015 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that 1016 * have an OSVW id assigned, which it takes as first argument. Both take a 1017 * variable number of family-specific model-stepping ranges created by 1018 * AMD_MODEL_RANGE(). 1019 * 1020 * Example: 1021 * 1022 * const int amd_erratum_319[] = 1023 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), 1024 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), 1025 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); 1026 */ 1027 1028 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } 1029 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } 1030 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ 1031 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) 1032 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) 1033 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) 1034 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) 1035 1036 static const int amd_erratum_400[] = 1037 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), 1038 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); 1039 1040 static const int amd_erratum_383[] = 1041 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); 1042 1043 1044 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) 1045 { 1046 int osvw_id = *erratum++; 1047 u32 range; 1048 u32 ms; 1049 1050 if (osvw_id >= 0 && osvw_id < 65536 && 1051 cpu_has(cpu, X86_FEATURE_OSVW)) { 1052 u64 osvw_len; 1053 1054 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); 1055 if (osvw_id < osvw_len) { 1056 u64 osvw_bits; 1057 1058 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), 1059 osvw_bits); 1060 return osvw_bits & (1ULL << (osvw_id & 0x3f)); 1061 } 1062 } 1063 1064 /* OSVW unavailable or ID unknown, match family-model-stepping range */ 1065 ms = (cpu->x86_model << 4) | cpu->x86_stepping; 1066 while ((range = *erratum++)) 1067 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && 1068 (ms >= AMD_MODEL_RANGE_START(range)) && 1069 (ms <= AMD_MODEL_RANGE_END(range))) 1070 return true; 1071 1072 return false; 1073 } 1074 1075 void set_dr_addr_mask(unsigned long mask, int dr) 1076 { 1077 if (!boot_cpu_has(X86_FEATURE_BPEXT)) 1078 return; 1079 1080 switch (dr) { 1081 case 0: 1082 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0); 1083 break; 1084 case 1: 1085 case 2: 1086 case 3: 1087 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0); 1088 break; 1089 default: 1090 break; 1091 } 1092 } 1093