1 // SPDX-License-Identifier: GPL-2.0-only 2 #include <linux/export.h> 3 #include <linux/bitops.h> 4 #include <linux/dmi.h> 5 #include <linux/elf.h> 6 #include <linux/mm.h> 7 #include <linux/kvm_types.h> 8 #include <linux/io.h> 9 #include <linux/sched.h> 10 #include <linux/sched/clock.h> 11 #include <linux/random.h> 12 #include <linux/topology.h> 13 #include <linux/platform_data/x86/amd-fch.h> 14 #include <asm/processor.h> 15 #include <asm/apic.h> 16 #include <asm/cacheinfo.h> 17 #include <asm/cpu.h> 18 #include <asm/cpu_device_id.h> 19 #include <asm/cpuid/api.h> 20 #include <asm/spec-ctrl.h> 21 #include <asm/smp.h> 22 #include <asm/numa.h> 23 #include <asm/pci-direct.h> 24 #include <asm/delay.h> 25 #include <asm/debugreg.h> 26 #include <asm/resctrl.h> 27 #include <asm/msr.h> 28 #include <asm/sev.h> 29 30 #ifdef CONFIG_X86_64 31 # include <asm/mmconfig.h> 32 #endif 33 34 #include "cpu.h" 35 36 u16 invlpgb_count_max __ro_after_init = 1; 37 38 static inline int rdmsrq_amd_safe(unsigned msr, u64 *p) 39 { 40 u32 gprs[8] = { 0 }; 41 int err; 42 43 WARN_ONCE((boot_cpu_data.x86 != 0xf), 44 "%s should only be used on K8!\n", __func__); 45 46 gprs[1] = msr; 47 gprs[7] = 0x9c5a203a; 48 49 err = rdmsr_safe_regs(gprs); 50 51 *p = gprs[0] | ((u64)gprs[2] << 32); 52 53 return err; 54 } 55 56 static inline int wrmsrq_amd_safe(unsigned msr, u64 val) 57 { 58 u32 gprs[8] = { 0 }; 59 60 WARN_ONCE((boot_cpu_data.x86 != 0xf), 61 "%s should only be used on K8!\n", __func__); 62 63 gprs[0] = (u32)val; 64 gprs[1] = msr; 65 gprs[2] = val >> 32; 66 gprs[7] = 0x9c5a203a; 67 68 return wrmsr_safe_regs(gprs); 69 } 70 71 /* 72 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 73 * misexecution of code under Linux. Owners of such processors should 74 * contact AMD for precise details and a CPU swap. 75 * 76 * See http://www.multimania.com/poulot/k6bug.html 77 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" 78 * (Publication # 21266 Issue Date: August 1998) 79 * 80 * The following test is erm.. interesting. AMD neglected to up 81 * the chip setting when fixing the bug but they also tweaked some 82 * performance at the same time.. 83 */ 84 85 #ifdef CONFIG_X86_32 86 extern __visible void vide(void); 87 __asm__(".text\n" 88 ".globl vide\n" 89 ".type vide, @function\n" 90 ".align 4\n" 91 "vide: ret\n"); 92 #endif 93 94 static void init_amd_k5(struct cpuinfo_x86 *c) 95 { 96 #ifdef CONFIG_X86_32 97 /* 98 * General Systems BIOSen alias the cpu frequency registers 99 * of the Elan at 0x000df000. Unfortunately, one of the Linux 100 * drivers subsequently pokes it, and changes the CPU speed. 101 * Workaround : Remove the unneeded alias. 102 */ 103 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 104 #define CBAR_ENB (0x80000000) 105 #define CBAR_KEY (0X000000CB) 106 if (c->x86_model == 9 || c->x86_model == 10) { 107 if (inl(CBAR) & CBAR_ENB) 108 outl(0 | CBAR_KEY, CBAR); 109 } 110 #endif 111 } 112 113 static void init_amd_k6(struct cpuinfo_x86 *c) 114 { 115 #ifdef CONFIG_X86_32 116 struct msr val; 117 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); 118 119 if (c->x86_model < 6) { 120 /* Based on AMD doc 20734R - June 2000 */ 121 if (c->x86_model == 0) { 122 clear_cpu_cap(c, X86_FEATURE_APIC); 123 set_cpu_cap(c, X86_FEATURE_PGE); 124 } 125 return; 126 } 127 128 if (c->x86_model == 6 && c->x86_stepping == 1) { 129 const int K6_BUG_LOOP = 1000000; 130 int n; 131 void (*f_vide)(void); 132 u64 d, d2; 133 134 pr_info("AMD K6 stepping B detected - "); 135 136 /* 137 * It looks like AMD fixed the 2.6.2 bug and improved indirect 138 * calls at the same time. 139 */ 140 141 n = K6_BUG_LOOP; 142 f_vide = vide; 143 OPTIMIZER_HIDE_VAR(f_vide); 144 d = rdtsc(); 145 while (n--) 146 f_vide(); 147 d2 = rdtsc(); 148 d = d2-d; 149 150 if (d > 20*K6_BUG_LOOP) 151 pr_cont("system stability may be impaired when more than 32 MB are used.\n"); 152 else 153 pr_cont("probably OK (after B9730xxxx).\n"); 154 } 155 156 /* K6 with old style WHCR */ 157 if (c->x86_model < 8 || 158 (c->x86_model == 8 && c->x86_stepping < 8)) { 159 /* We can only write allocate on the low 508Mb */ 160 if (mbytes > 508) 161 mbytes = 508; 162 163 rdmsrq(MSR_K6_WHCR, val.q); 164 if ((val.l & 0x0000FFFF) == 0) { 165 unsigned long flags; 166 val.l = (1 << 0) | ((mbytes / 4) << 1); 167 local_irq_save(flags); 168 wbinvd(); 169 wrmsrq(MSR_K6_WHCR, val.q); 170 local_irq_restore(flags); 171 pr_info("Enabling old style K6 write allocation for %d Mb\n", 172 mbytes); 173 } 174 return; 175 } 176 177 if ((c->x86_model == 8 && c->x86_stepping > 7) || 178 c->x86_model == 9 || c->x86_model == 13) { 179 /* The more serious chips .. */ 180 181 if (mbytes > 4092) 182 mbytes = 4092; 183 184 rdmsrq(MSR_K6_WHCR, val.q); 185 if ((val.l & 0xFFFF0000) == 0) { 186 unsigned long flags; 187 val.l = ((mbytes >> 2) << 22) | (1 << 16); 188 local_irq_save(flags); 189 wbinvd(); 190 wrmsrq(MSR_K6_WHCR, val.q); 191 local_irq_restore(flags); 192 pr_info("Enabling new style K6 write allocation for %d Mb\n", 193 mbytes); 194 } 195 196 return; 197 } 198 199 if (c->x86_model == 10) { 200 /* AMD Geode LX is model 10 */ 201 /* placeholder for any needed mods */ 202 return; 203 } 204 #endif 205 } 206 207 static void init_amd_k7(struct cpuinfo_x86 *c) 208 { 209 #ifdef CONFIG_X86_32 210 struct msr val; 211 212 /* 213 * Bit 15 of Athlon specific MSR 15, needs to be 0 214 * to enable SSE on Palomino/Morgan/Barton CPU's. 215 * If the BIOS didn't enable it already, enable it here. 216 */ 217 if (c->x86_model >= 6 && c->x86_model <= 10) { 218 if (!cpu_has(c, X86_FEATURE_XMM)) { 219 pr_info("Enabling disabled K7/SSE Support.\n"); 220 msr_clear_bit(MSR_K7_HWCR, 15); 221 set_cpu_cap(c, X86_FEATURE_XMM); 222 } 223 } 224 225 /* 226 * It's been determined by AMD that Athlons since model 8 stepping 1 227 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 228 * As per AMD technical note 27212 0.2 229 */ 230 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) { 231 rdmsrq(MSR_K7_CLK_CTL, val.q); 232 if ((val.l & 0xfff00000) != 0x20000000) { 233 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", 234 val.l, ((val.l & 0x000fffff) | 0x20000000)); 235 val.l = (val.l & 0x000fffff) | 0x20000000; 236 wrmsrq(MSR_K7_CLK_CTL, val.q); 237 } 238 } 239 240 /* calling is from identify_secondary_cpu() ? */ 241 if (!c->cpu_index) 242 return; 243 244 /* 245 * Certain Athlons might work (for various values of 'work') in SMP 246 * but they are not certified as MP capable. 247 */ 248 /* Athlon 660/661 is valid. */ 249 if ((c->x86_model == 6) && ((c->x86_stepping == 0) || 250 (c->x86_stepping == 1))) 251 return; 252 253 /* Duron 670 is valid */ 254 if ((c->x86_model == 7) && (c->x86_stepping == 0)) 255 return; 256 257 /* 258 * Athlon 662, Duron 671, and Athlon >model 7 have capability 259 * bit. It's worth noting that the A5 stepping (662) of some 260 * Athlon XP's have the MP bit set. 261 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for 262 * more. 263 */ 264 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) || 265 ((c->x86_model == 7) && (c->x86_stepping >= 1)) || 266 (c->x86_model > 7)) 267 if (cpu_has(c, X86_FEATURE_MP)) 268 return; 269 270 /* If we get here, not a certified SMP capable AMD system. */ 271 272 /* 273 * Don't taint if we are running SMP kernel on a single non-MP 274 * approved Athlon 275 */ 276 WARN_ONCE(1, "WARNING: This combination of AMD" 277 " processors is not suitable for SMP.\n"); 278 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 279 #endif 280 } 281 282 #ifdef CONFIG_NUMA 283 /* 284 * To workaround broken NUMA config. Read the comment in 285 * srat_detect_node(). 286 */ 287 static int nearby_node(int apicid) 288 { 289 int i, node; 290 291 for (i = apicid - 1; i >= 0; i--) { 292 node = __apicid_to_node[i]; 293 if (node != NUMA_NO_NODE && node_online(node)) 294 return node; 295 } 296 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 297 node = __apicid_to_node[i]; 298 if (node != NUMA_NO_NODE && node_online(node)) 299 return node; 300 } 301 return first_node(node_online_map); /* Shouldn't happen */ 302 } 303 #endif 304 305 static void srat_detect_node(struct cpuinfo_x86 *c) 306 { 307 #ifdef CONFIG_NUMA 308 int cpu = smp_processor_id(); 309 int node; 310 unsigned apicid = c->topo.apicid; 311 312 node = numa_cpu_node(cpu); 313 if (node == NUMA_NO_NODE) 314 node = per_cpu_llc_id(cpu); 315 316 /* 317 * On multi-fabric platform (e.g. Numascale NumaChip) a 318 * platform-specific handler needs to be called to fixup some 319 * IDs of the CPU. 320 */ 321 if (x86_cpuinit.fixup_cpu_id) 322 x86_cpuinit.fixup_cpu_id(c, node); 323 324 if (!node_online(node)) { 325 /* 326 * Two possibilities here: 327 * 328 * - The CPU is missing memory and no node was created. In 329 * that case try picking one from a nearby CPU. 330 * 331 * - The APIC IDs differ from the HyperTransport node IDs 332 * which the K8 northbridge parsing fills in. Assume 333 * they are all increased by a constant offset, but in 334 * the same order as the HT nodeids. If that doesn't 335 * result in a usable node fall back to the path for the 336 * previous case. 337 * 338 * This workaround operates directly on the mapping between 339 * APIC ID and NUMA node, assuming certain relationship 340 * between APIC ID, HT node ID and NUMA topology. As going 341 * through CPU mapping may alter the outcome, directly 342 * access __apicid_to_node[]. 343 */ 344 int ht_nodeid = c->topo.initial_apicid; 345 346 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 347 node = __apicid_to_node[ht_nodeid]; 348 /* Pick a nearby node */ 349 if (!node_online(node)) 350 node = nearby_node(apicid); 351 } 352 numa_set_node(cpu, node); 353 #endif 354 } 355 356 static void bsp_determine_snp(struct cpuinfo_x86 *c) 357 { 358 #ifdef CONFIG_ARCH_HAS_CC_PLATFORM 359 cc_vendor = CC_VENDOR_AMD; 360 361 if (cpu_has(c, X86_FEATURE_SEV_SNP)) { 362 /* 363 * RMP table entry format is not architectural and is defined by the 364 * per-processor PPR. Restrict SNP support on the known CPU models 365 * for which the RMP table entry format is currently defined or for 366 * processors which support the architecturally defined RMPREAD 367 * instruction. 368 */ 369 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && 370 (cpu_feature_enabled(X86_FEATURE_ZEN3) || 371 cpu_feature_enabled(X86_FEATURE_ZEN4) || 372 cpu_feature_enabled(X86_FEATURE_RMPREAD)) && 373 snp_probe_rmptable_info()) { 374 cc_platform_set(CC_ATTR_HOST_SEV_SNP); 375 } else { 376 setup_clear_cpu_cap(X86_FEATURE_SEV_SNP); 377 cc_platform_clear(CC_ATTR_HOST_SEV_SNP); 378 } 379 } 380 #endif 381 } 382 383 #define ZEN_MODEL_STEP_UCODE(fam, model, step, ucode) \ 384 X86_MATCH_VFM_STEPS(VFM_MAKE(X86_VENDOR_AMD, fam, model), \ 385 step, step, ucode) 386 387 static const struct x86_cpu_id amd_tsa_microcode[] = { 388 ZEN_MODEL_STEP_UCODE(0x19, 0x01, 0x1, 0x0a0011d7), 389 ZEN_MODEL_STEP_UCODE(0x19, 0x01, 0x2, 0x0a00123b), 390 ZEN_MODEL_STEP_UCODE(0x19, 0x08, 0x2, 0x0a00820d), 391 ZEN_MODEL_STEP_UCODE(0x19, 0x11, 0x1, 0x0a10114c), 392 ZEN_MODEL_STEP_UCODE(0x19, 0x11, 0x2, 0x0a10124c), 393 ZEN_MODEL_STEP_UCODE(0x19, 0x18, 0x1, 0x0a108109), 394 ZEN_MODEL_STEP_UCODE(0x19, 0x21, 0x0, 0x0a20102e), 395 ZEN_MODEL_STEP_UCODE(0x19, 0x21, 0x2, 0x0a201211), 396 ZEN_MODEL_STEP_UCODE(0x19, 0x44, 0x1, 0x0a404108), 397 ZEN_MODEL_STEP_UCODE(0x19, 0x50, 0x0, 0x0a500012), 398 ZEN_MODEL_STEP_UCODE(0x19, 0x61, 0x2, 0x0a60120a), 399 ZEN_MODEL_STEP_UCODE(0x19, 0x74, 0x1, 0x0a704108), 400 ZEN_MODEL_STEP_UCODE(0x19, 0x75, 0x2, 0x0a705208), 401 ZEN_MODEL_STEP_UCODE(0x19, 0x78, 0x0, 0x0a708008), 402 ZEN_MODEL_STEP_UCODE(0x19, 0x7c, 0x0, 0x0a70c008), 403 ZEN_MODEL_STEP_UCODE(0x19, 0xa0, 0x2, 0x0aa00216), 404 {}, 405 }; 406 407 static void tsa_init(struct cpuinfo_x86 *c) 408 { 409 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) 410 return; 411 412 if (cpu_has(c, X86_FEATURE_ZEN3) || 413 cpu_has(c, X86_FEATURE_ZEN4)) { 414 if (x86_match_min_microcode_rev(amd_tsa_microcode)) 415 setup_force_cpu_cap(X86_FEATURE_VERW_CLEAR); 416 else 417 pr_debug("%s: current revision: 0x%x\n", __func__, c->microcode); 418 } else { 419 setup_force_cpu_cap(X86_FEATURE_TSA_SQ_NO); 420 setup_force_cpu_cap(X86_FEATURE_TSA_L1_NO); 421 } 422 } 423 424 static void bsp_init_amd(struct cpuinfo_x86 *c) 425 { 426 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 427 428 if (c->x86 > 0x10 || 429 (c->x86 == 0x10 && c->x86_model >= 0x2)) { 430 u64 val; 431 432 rdmsrq(MSR_K7_HWCR, val); 433 if (!(val & BIT(24))) 434 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); 435 } 436 } 437 438 if (c->x86 == 0x15) { 439 unsigned long upperbit; 440 u32 cpuid, assoc; 441 442 cpuid = cpuid_edx(0x80000005); 443 assoc = cpuid >> 16 & 0xff; 444 upperbit = ((cpuid >> 24) << 10) / assoc; 445 446 va_align.mask = (upperbit - 1) & PAGE_MASK; 447 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; 448 449 /* A random value per boot for bit slice [12:upper_bit) */ 450 va_align.bits = get_random_u32() & va_align.mask; 451 } 452 453 if (cpu_has(c, X86_FEATURE_MWAITX)) 454 use_mwaitx_delay(); 455 456 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) && 457 !boot_cpu_has(X86_FEATURE_VIRT_SSBD) && 458 c->x86 >= 0x15 && c->x86 <= 0x17) { 459 unsigned int bit; 460 461 switch (c->x86) { 462 case 0x15: bit = 54; break; 463 case 0x16: bit = 33; break; 464 case 0x17: bit = 10; break; 465 default: return; 466 } 467 /* 468 * Try to cache the base value so further operations can 469 * avoid RMW. If that faults, do not enable SSBD. 470 */ 471 if (!rdmsrq_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) { 472 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD); 473 setup_force_cpu_cap(X86_FEATURE_SSBD); 474 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit; 475 } 476 } 477 478 resctrl_cpu_detect(c); 479 480 /* Figure out Zen generations: */ 481 switch (c->x86) { 482 case 0x17: 483 switch (c->x86_model) { 484 case 0x00 ... 0x2f: 485 case 0x50 ... 0x5f: 486 setup_force_cpu_cap(X86_FEATURE_ZEN1); 487 break; 488 case 0x30 ... 0x4f: 489 case 0x60 ... 0x7f: 490 case 0x90 ... 0x91: 491 case 0xa0 ... 0xaf: 492 setup_force_cpu_cap(X86_FEATURE_ZEN2); 493 break; 494 default: 495 goto warn; 496 } 497 break; 498 499 case 0x19: 500 switch (c->x86_model) { 501 case 0x00 ... 0x0f: 502 case 0x20 ... 0x5f: 503 setup_force_cpu_cap(X86_FEATURE_ZEN3); 504 break; 505 case 0x10 ... 0x1f: 506 case 0x60 ... 0xaf: 507 setup_force_cpu_cap(X86_FEATURE_ZEN4); 508 break; 509 default: 510 goto warn; 511 } 512 break; 513 514 case 0x1a: 515 switch (c->x86_model) { 516 case 0x00 ... 0x2f: 517 case 0x40 ... 0x4f: 518 case 0x60 ... 0x7f: 519 case 0xd0 ... 0xd7: 520 setup_force_cpu_cap(X86_FEATURE_ZEN5); 521 break; 522 case 0x50 ... 0x5f: 523 case 0x80 ... 0xaf: 524 case 0xc0 ... 0xcf: 525 case 0xd8 ... 0xef: 526 setup_force_cpu_cap(X86_FEATURE_ZEN6); 527 break; 528 default: 529 goto warn; 530 } 531 break; 532 533 default: 534 break; 535 } 536 537 bsp_determine_snp(c); 538 tsa_init(c); 539 540 if (cpu_has(c, X86_FEATURE_GP_ON_USER_CPUID)) 541 setup_force_cpu_cap(X86_FEATURE_CPUID_FAULT); 542 543 return; 544 545 warn: 546 WARN_ONCE(1, "Family 0x%x, model: 0x%x??\n", c->x86, c->x86_model); 547 } 548 549 static void early_detect_mem_encrypt(struct cpuinfo_x86 *c) 550 { 551 u64 msr; 552 553 /* 554 * Mark using WBINVD is needed during kexec on processors that 555 * support SME. This provides support for performing a successful 556 * kexec when going from SME inactive to SME active (or vice-versa). 557 * 558 * The cache must be cleared so that if there are entries with the 559 * same physical address, both with and without the encryption bit, 560 * they don't race each other when flushed and potentially end up 561 * with the wrong entry being committed to memory. 562 * 563 * Test the CPUID bit directly because with mem_encrypt=off the 564 * BSP will clear the X86_FEATURE_SME bit and the APs will not 565 * see it set after that. 566 */ 567 if (c->extended_cpuid_level >= 0x8000001f && (cpuid_eax(0x8000001f) & BIT(0))) 568 __this_cpu_write(cache_state_incoherent, true); 569 570 /* 571 * BIOS support is required for SME and SEV. 572 * For SME: If BIOS has enabled SME then adjust x86_phys_bits by 573 * the SME physical address space reduction value. 574 * If BIOS has not enabled SME then don't advertise the 575 * SME feature (set in scattered.c). 576 * If the kernel has not enabled SME via any means then 577 * don't advertise the SME feature. 578 * For SEV: If BIOS has not enabled SEV then don't advertise SEV and 579 * any additional functionality based on it. 580 * 581 * In all cases, since support for SME and SEV requires long mode, 582 * don't advertise the feature under CONFIG_X86_32. 583 */ 584 if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) { 585 /* Check if memory encryption is enabled */ 586 rdmsrq(MSR_AMD64_SYSCFG, msr); 587 if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT)) 588 goto clear_all; 589 590 /* 591 * Always adjust physical address bits. Even though this 592 * will be a value above 32-bits this is still done for 593 * CONFIG_X86_32 so that accurate values are reported. 594 */ 595 c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f; 596 597 if (IS_ENABLED(CONFIG_X86_32)) 598 goto clear_all; 599 600 if (!sme_me_mask) 601 setup_clear_cpu_cap(X86_FEATURE_SME); 602 603 rdmsrq(MSR_K7_HWCR, msr); 604 if (!(msr & MSR_K7_HWCR_SMMLOCK)) 605 goto clear_sev; 606 607 return; 608 609 clear_all: 610 setup_clear_cpu_cap(X86_FEATURE_SME); 611 clear_sev: 612 setup_clear_cpu_cap(X86_FEATURE_SEV); 613 setup_clear_cpu_cap(X86_FEATURE_SEV_ES); 614 setup_clear_cpu_cap(X86_FEATURE_SEV_SNP); 615 } 616 } 617 618 static void early_init_amd(struct cpuinfo_x86 *c) 619 { 620 u64 val; 621 622 if (c->x86 >= 0xf) 623 set_cpu_cap(c, X86_FEATURE_K8); 624 625 rdmsrq_safe(MSR_AMD64_PATCH_LEVEL, &val); 626 c->microcode = (u32)val; 627 628 /* 629 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 630 * with P/T states and does not stop in deep C-states 631 */ 632 if (c->x86_power & (1 << 8)) { 633 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 634 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 635 } 636 637 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ 638 if (c->x86_power & BIT(12)) 639 set_cpu_cap(c, X86_FEATURE_ACC_POWER); 640 641 /* Bit 14 indicates the Runtime Average Power Limit interface. */ 642 if (c->x86_power & BIT(14)) 643 set_cpu_cap(c, X86_FEATURE_RAPL); 644 645 #ifdef CONFIG_X86_64 646 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 647 #else 648 /* Set MTRR capability flag if appropriate */ 649 if (c->x86 == 5) 650 if (c->x86_model == 13 || c->x86_model == 9 || 651 (c->x86_model == 8 && c->x86_stepping >= 8)) 652 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 653 #endif 654 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 655 /* 656 * ApicID can always be treated as an 8-bit value for AMD APIC versions 657 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we 658 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families 659 * after 16h. 660 */ 661 if (boot_cpu_has(X86_FEATURE_APIC)) { 662 if (c->x86 > 0x16) 663 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 664 else if (c->x86 >= 0xf) { 665 /* check CPU config space for extended APIC ID */ 666 unsigned int val; 667 668 val = read_pci_config(0, 24, 0, 0x68); 669 if ((val >> 17 & 0x3) == 0x3) 670 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 671 } 672 } 673 #endif 674 675 /* 676 * This is only needed to tell the kernel whether to use VMCALL 677 * and VMMCALL. VMMCALL is never executed except under virt, so 678 * we can set it unconditionally. 679 */ 680 set_cpu_cap(c, X86_FEATURE_VMMCALL); 681 682 /* F16h erratum 793, CVE-2013-6885 */ 683 if (c->x86 == 0x16 && c->x86_model <= 0xf) 684 msr_set_bit(MSR_AMD64_LS_CFG, 15); 685 686 early_detect_mem_encrypt(c); 687 688 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && !cpu_has(c, X86_FEATURE_IBPB_BRTYPE)) { 689 if (c->x86 == 0x17 && boot_cpu_has(X86_FEATURE_AMD_IBPB)) 690 setup_force_cpu_cap(X86_FEATURE_IBPB_BRTYPE); 691 else if (c->x86 >= 0x19 && !wrmsrq_safe(MSR_IA32_PRED_CMD, PRED_CMD_SBPB)) { 692 setup_force_cpu_cap(X86_FEATURE_IBPB_BRTYPE); 693 setup_force_cpu_cap(X86_FEATURE_SBPB); 694 } 695 } 696 } 697 698 static void init_amd_k8(struct cpuinfo_x86 *c) 699 { 700 u32 level; 701 u64 value; 702 703 /* On C+ stepping K8 rep microcode works well for copy/memset */ 704 level = cpuid_eax(1); 705 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) 706 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 707 708 /* 709 * Some BIOSes incorrectly force this feature, but only K8 revision D 710 * (model = 0x14) and later actually support it. 711 * (AMD Erratum #110, docId: 25759). 712 */ 713 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM) && !cpu_has(c, X86_FEATURE_HYPERVISOR)) { 714 clear_cpu_cap(c, X86_FEATURE_LAHF_LM); 715 if (!rdmsrq_amd_safe(0xc001100d, &value)) { 716 value &= ~BIT_64(32); 717 wrmsrq_amd_safe(0xc001100d, value); 718 } 719 } 720 721 if (!c->x86_model_id[0]) 722 strscpy(c->x86_model_id, "Hammer"); 723 724 #ifdef CONFIG_SMP 725 /* 726 * Disable TLB flush filter by setting HWCR.FFDIS on K8 727 * bit 6 of msr C001_0015 728 * 729 * Errata 63 for SH-B3 steppings 730 * Errata 122 for all steppings (F+ have it disabled by default) 731 */ 732 msr_set_bit(MSR_K7_HWCR, 6); 733 #endif 734 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE); 735 736 /* 737 * Check models and steppings affected by erratum 400. This is 738 * used to select the proper idle routine and to enable the 739 * check whether the machine is affected in arch_post_acpi_subsys_init() 740 * which sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check. 741 */ 742 if (c->x86_model > 0x41 || 743 (c->x86_model == 0x41 && c->x86_stepping >= 0x2)) 744 setup_force_cpu_bug(X86_BUG_AMD_E400); 745 } 746 747 static void init_amd_gh(struct cpuinfo_x86 *c) 748 { 749 #ifdef CONFIG_MMCONF_FAM10H 750 /* do this for boot cpu */ 751 if (c == &boot_cpu_data) 752 check_enable_amd_mmconf_dmi(); 753 754 fam10h_check_enable_mmcfg(); 755 #endif 756 757 /* 758 * Disable GART TLB Walk Errors on Fam10h. We do this here because this 759 * is always needed when GART is enabled, even in a kernel which has no 760 * MCE support built in. BIOS should disable GartTlbWlk Errors already. 761 * If it doesn't, we do it here as suggested by the BKDG. 762 * 763 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 764 */ 765 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10); 766 767 /* 768 * On family 10h BIOS may not have properly enabled WC+ support, causing 769 * it to be converted to CD memtype. This may result in performance 770 * degradation for certain nested-paging guests. Prevent this conversion 771 * by clearing bit 24 in MSR_AMD64_BU_CFG2. 772 * 773 * NOTE: we want to use the _safe accessors so as not to #GP kvm 774 * guests on older kvm hosts. 775 */ 776 msr_clear_bit(MSR_AMD64_BU_CFG2, 24); 777 778 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH); 779 780 /* 781 * Check models and steppings affected by erratum 400. This is 782 * used to select the proper idle routine and to enable the 783 * check whether the machine is affected in arch_post_acpi_subsys_init() 784 * which sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check. 785 */ 786 if (c->x86_model > 0x2 || 787 (c->x86_model == 0x2 && c->x86_stepping >= 0x1)) 788 setup_force_cpu_bug(X86_BUG_AMD_E400); 789 } 790 791 static void init_amd_ln(struct cpuinfo_x86 *c) 792 { 793 /* 794 * Apply erratum 665 fix unconditionally so machines without a BIOS 795 * fix work. 796 */ 797 msr_set_bit(MSR_AMD64_DE_CFG, 31); 798 } 799 800 static bool rdrand_force; 801 802 static int __init rdrand_cmdline(char *str) 803 { 804 if (!str) 805 return -EINVAL; 806 807 if (!strcmp(str, "force")) 808 rdrand_force = true; 809 else 810 return -EINVAL; 811 812 return 0; 813 } 814 early_param("rdrand", rdrand_cmdline); 815 816 static void clear_rdrand_cpuid_bit(struct cpuinfo_x86 *c) 817 { 818 /* 819 * Saving of the MSR used to hide the RDRAND support during 820 * suspend/resume is done by arch/x86/power/cpu.c, which is 821 * dependent on CONFIG_PM_SLEEP. 822 */ 823 if (!IS_ENABLED(CONFIG_PM_SLEEP)) 824 return; 825 826 /* 827 * The self-test can clear X86_FEATURE_RDRAND, so check for 828 * RDRAND support using the CPUID function directly. 829 */ 830 if (!(cpuid_ecx(1) & BIT(30)) || rdrand_force) 831 return; 832 833 msr_clear_bit(MSR_AMD64_CPUID_FN_1, 62); 834 835 /* 836 * Verify that the CPUID change has occurred in case the kernel is 837 * running virtualized and the hypervisor doesn't support the MSR. 838 */ 839 if (cpuid_ecx(1) & BIT(30)) { 840 pr_info_once("BIOS may not properly restore RDRAND after suspend, but hypervisor does not support hiding RDRAND via CPUID.\n"); 841 return; 842 } 843 844 clear_cpu_cap(c, X86_FEATURE_RDRAND); 845 pr_info_once("BIOS may not properly restore RDRAND after suspend, hiding RDRAND via CPUID. Use rdrand=force to reenable.\n"); 846 } 847 848 static void init_amd_jg(struct cpuinfo_x86 *c) 849 { 850 /* 851 * Some BIOS implementations do not restore proper RDRAND support 852 * across suspend and resume. Check on whether to hide the RDRAND 853 * instruction support via CPUID. 854 */ 855 clear_rdrand_cpuid_bit(c); 856 } 857 858 static void init_amd_bd(struct cpuinfo_x86 *c) 859 { 860 u64 value; 861 862 /* 863 * The way access filter has a performance penalty on some workloads. 864 * Disable it on the affected CPUs. 865 */ 866 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) { 867 if (!rdmsrq_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) { 868 value |= 0x1E; 869 wrmsrq_safe(MSR_F15H_IC_CFG, value); 870 } 871 } 872 873 /* 874 * Some BIOS implementations do not restore proper RDRAND support 875 * across suspend and resume. Check on whether to hide the RDRAND 876 * instruction support via CPUID. 877 */ 878 clear_rdrand_cpuid_bit(c); 879 } 880 881 static const struct x86_cpu_id erratum_1386_microcode[] = { 882 ZEN_MODEL_STEP_UCODE(0x17, 0x01, 0x2, 0x0800126e), 883 ZEN_MODEL_STEP_UCODE(0x17, 0x31, 0x0, 0x08301052), 884 {} 885 }; 886 887 static void fix_erratum_1386(struct cpuinfo_x86 *c) 888 { 889 /* 890 * Work around Erratum 1386. The XSAVES instruction malfunctions in 891 * certain circumstances on Zen1/2 uarch, and not all parts have had 892 * updated microcode at the time of writing (March 2023). 893 * 894 * Affected parts all have no supervisor XSAVE states, meaning that 895 * the XSAVEC instruction (which works fine) is equivalent. 896 * 897 * Clear the feature flag only on microcode revisions which 898 * don't have the fix. 899 */ 900 if (x86_match_min_microcode_rev(erratum_1386_microcode)) 901 return; 902 903 clear_cpu_cap(c, X86_FEATURE_XSAVES); 904 } 905 906 void init_spectral_chicken(struct cpuinfo_x86 *c) 907 { 908 #ifdef CONFIG_MITIGATION_UNRET_ENTRY 909 /* 910 * On Zen2 we offer this chicken (bit) on the altar of Speculation. 911 * 912 * This suppresses speculation from the middle of a basic block, i.e. it 913 * suppresses non-branch predictions. 914 */ 915 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) 916 msr_set_bit(MSR_ZEN2_SPECTRAL_CHICKEN, MSR_ZEN2_SPECTRAL_CHICKEN_BIT); 917 #endif 918 } 919 920 static void init_amd_zen_common(void) 921 { 922 setup_force_cpu_cap(X86_FEATURE_ZEN); 923 #ifdef CONFIG_NUMA 924 node_reclaim_distance = 32; 925 #endif 926 } 927 928 static void init_amd_zen1(struct cpuinfo_x86 *c) 929 { 930 fix_erratum_1386(c); 931 932 /* Fix up CPUID bits, but only if not virtualised. */ 933 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) { 934 935 /* Erratum 1076: CPB feature bit not being set in CPUID. */ 936 if (!cpu_has(c, X86_FEATURE_CPB)) 937 set_cpu_cap(c, X86_FEATURE_CPB); 938 } 939 940 pr_notice_once("AMD Zen1 DIV0 bug detected. Disable SMT for full protection.\n"); 941 setup_force_cpu_bug(X86_BUG_DIV0); 942 943 /* 944 * Turn off the Instructions Retired free counter on machines that are 945 * susceptible to erratum #1054 "Instructions Retired Performance 946 * Counter May Be Inaccurate". 947 */ 948 if (c->x86_model < 0x30) { 949 msr_clear_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT); 950 clear_cpu_cap(c, X86_FEATURE_IRPERF); 951 } 952 953 pr_notice_once("AMD Zen1 FPDSS bug detected, enabling mitigation.\n"); 954 msr_set_bit(MSR_AMD64_FP_CFG, MSR_AMD64_FP_CFG_ZEN1_DENORM_FIX_BIT); 955 } 956 957 static const struct x86_cpu_id amd_zenbleed_microcode[] = { 958 ZEN_MODEL_STEP_UCODE(0x17, 0x31, 0x0, 0x0830107b), 959 ZEN_MODEL_STEP_UCODE(0x17, 0x60, 0x1, 0x0860010c), 960 ZEN_MODEL_STEP_UCODE(0x17, 0x68, 0x1, 0x08608107), 961 ZEN_MODEL_STEP_UCODE(0x17, 0x71, 0x0, 0x08701033), 962 ZEN_MODEL_STEP_UCODE(0x17, 0xa0, 0x0, 0x08a00009), 963 {} 964 }; 965 966 static void zen2_zenbleed_check(struct cpuinfo_x86 *c) 967 { 968 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) 969 return; 970 971 if (!cpu_has(c, X86_FEATURE_AVX)) 972 return; 973 974 if (!x86_match_min_microcode_rev(amd_zenbleed_microcode)) { 975 pr_notice_once("Zenbleed: please update your microcode for the most optimal fix\n"); 976 msr_set_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT); 977 } else { 978 msr_clear_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT); 979 } 980 } 981 982 static void init_amd_zen2(struct cpuinfo_x86 *c) 983 { 984 init_spectral_chicken(c); 985 fix_erratum_1386(c); 986 zen2_zenbleed_check(c); 987 988 /* Disable RDSEED on AMD Cyan Skillfish because of an error. */ 989 if (c->x86_model == 0x47 && c->x86_stepping == 0x0) { 990 clear_cpu_cap(c, X86_FEATURE_RDSEED); 991 msr_clear_bit(MSR_AMD64_CPUID_FN_7, 18); 992 pr_emerg("RDSEED is not reliable on this platform; disabling.\n"); 993 } 994 995 /* Correct misconfigured CPUID on some clients. */ 996 clear_cpu_cap(c, X86_FEATURE_INVLPGB); 997 998 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) 999 msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN2_BP_CFG_BUG_FIX_BIT); 1000 } 1001 1002 static void init_amd_zen3(struct cpuinfo_x86 *c) 1003 { 1004 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) { 1005 /* 1006 * Zen3 (Fam19 model < 0x10) parts are not susceptible to 1007 * Branch Type Confusion, but predate the allocation of the 1008 * BTC_NO bit. 1009 */ 1010 if (!cpu_has(c, X86_FEATURE_BTC_NO)) 1011 set_cpu_cap(c, X86_FEATURE_BTC_NO); 1012 } 1013 } 1014 1015 static void init_amd_zen4(struct cpuinfo_x86 *c) 1016 { 1017 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) 1018 msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT); 1019 1020 /* 1021 * These Zen4 SoCs advertise support for virtualized VMLOAD/VMSAVE 1022 * in some BIOS versions but they can lead to random host reboots. 1023 */ 1024 switch (c->x86_model) { 1025 case 0x18 ... 0x1f: 1026 case 0x60 ... 0x7f: 1027 clear_cpu_cap(c, X86_FEATURE_V_VMSAVE_VMLOAD); 1028 break; 1029 } 1030 } 1031 1032 static const struct x86_cpu_id zen5_rdseed_microcode[] = { 1033 ZEN_MODEL_STEP_UCODE(0x1a, 0x02, 0x1, 0x0b00215a), 1034 ZEN_MODEL_STEP_UCODE(0x1a, 0x08, 0x1, 0x0b008121), 1035 ZEN_MODEL_STEP_UCODE(0x1a, 0x11, 0x0, 0x0b101054), 1036 ZEN_MODEL_STEP_UCODE(0x1a, 0x24, 0x0, 0x0b204037), 1037 ZEN_MODEL_STEP_UCODE(0x1a, 0x44, 0x0, 0x0b404035), 1038 ZEN_MODEL_STEP_UCODE(0x1a, 0x44, 0x1, 0x0b404108), 1039 ZEN_MODEL_STEP_UCODE(0x1a, 0x60, 0x0, 0x0b600037), 1040 ZEN_MODEL_STEP_UCODE(0x1a, 0x68, 0x0, 0x0b608038), 1041 ZEN_MODEL_STEP_UCODE(0x1a, 0x70, 0x0, 0x0b700037), 1042 {}, 1043 }; 1044 1045 static void init_amd_zen5(struct cpuinfo_x86 *c) 1046 { 1047 if (!x86_match_min_microcode_rev(zen5_rdseed_microcode)) { 1048 clear_cpu_cap(c, X86_FEATURE_RDSEED); 1049 msr_clear_bit(MSR_AMD64_CPUID_FN_7, 18); 1050 pr_emerg_once("RDSEED32 is broken. Disabling the corresponding CPUID bit.\n"); 1051 } 1052 } 1053 1054 static void init_amd(struct cpuinfo_x86 *c) 1055 { 1056 u64 vm_cr; 1057 1058 early_init_amd(c); 1059 1060 if (c->x86 >= 0x10) 1061 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 1062 1063 /* AMD FSRM also implies FSRS */ 1064 if (cpu_has(c, X86_FEATURE_FSRM)) 1065 set_cpu_cap(c, X86_FEATURE_FSRS); 1066 1067 /* K6s reports MCEs but don't actually have all the MSRs */ 1068 if (c->x86 < 6) 1069 clear_cpu_cap(c, X86_FEATURE_MCE); 1070 1071 switch (c->x86) { 1072 case 4: init_amd_k5(c); break; 1073 case 5: init_amd_k6(c); break; 1074 case 6: init_amd_k7(c); break; 1075 case 0xf: init_amd_k8(c); break; 1076 case 0x10: init_amd_gh(c); break; 1077 case 0x12: init_amd_ln(c); break; 1078 case 0x15: init_amd_bd(c); break; 1079 case 0x16: init_amd_jg(c); break; 1080 } 1081 1082 /* 1083 * Save up on some future enablement work and do common Zen 1084 * settings. 1085 */ 1086 if (c->x86 >= 0x17) 1087 init_amd_zen_common(); 1088 1089 if (boot_cpu_has(X86_FEATURE_ZEN1)) 1090 init_amd_zen1(c); 1091 else if (boot_cpu_has(X86_FEATURE_ZEN2)) 1092 init_amd_zen2(c); 1093 else if (boot_cpu_has(X86_FEATURE_ZEN3)) 1094 init_amd_zen3(c); 1095 else if (boot_cpu_has(X86_FEATURE_ZEN4)) 1096 init_amd_zen4(c); 1097 else if (boot_cpu_has(X86_FEATURE_ZEN5)) 1098 init_amd_zen5(c); 1099 1100 /* 1101 * Enable workaround for FXSAVE leak on CPUs 1102 * without a XSaveErPtr feature 1103 */ 1104 if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR))) 1105 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK); 1106 1107 cpu_detect_cache_sizes(c); 1108 1109 srat_detect_node(c); 1110 1111 init_amd_cacheinfo(c); 1112 1113 if (cpu_has(c, X86_FEATURE_SVM)) { 1114 rdmsrq(MSR_VM_CR, vm_cr); 1115 if (vm_cr & SVM_VM_CR_SVM_DIS_MASK) { 1116 pr_notice_once("SVM disabled (by BIOS) in MSR_VM_CR\n"); 1117 clear_cpu_cap(c, X86_FEATURE_SVM); 1118 } 1119 } 1120 1121 if (!cpu_has(c, X86_FEATURE_LFENCE_RDTSC) && cpu_has(c, X86_FEATURE_XMM2)) { 1122 /* 1123 * Use LFENCE for execution serialization. On families which 1124 * don't have that MSR, LFENCE is already serializing. 1125 * msr_set_bit() uses the safe accessors, too, even if the MSR 1126 * is not present. 1127 */ 1128 msr_set_bit(MSR_AMD64_DE_CFG, 1129 MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT); 1130 1131 /* A serializing LFENCE stops RDTSC speculation */ 1132 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 1133 } 1134 1135 /* 1136 * Family 0x12 and above processors have APIC timer 1137 * running in deep C states. 1138 */ 1139 if (c->x86 > 0x11) 1140 set_cpu_cap(c, X86_FEATURE_ARAT); 1141 1142 /* 3DNow or LM implies PREFETCHW */ 1143 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH)) 1144 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM)) 1145 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH); 1146 1147 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */ 1148 if (!cpu_feature_enabled(X86_FEATURE_XENPV)) 1149 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); 1150 1151 /* Enable the Instructions Retired free counter */ 1152 if (cpu_has(c, X86_FEATURE_IRPERF)) 1153 msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT); 1154 1155 check_null_seg_clears_base(c); 1156 1157 /* 1158 * Make sure EFER[AIBRSE - Automatic IBRS Enable] is set. The APs are brought up 1159 * using the trampoline code and as part of it, MSR_EFER gets prepared there in 1160 * order to be replicated onto them. Regardless, set it here again, if not set, 1161 * to protect against any future refactoring/code reorganization which might 1162 * miss setting this important bit. 1163 */ 1164 if (spectre_v2_in_eibrs_mode(spectre_v2_enabled) && 1165 cpu_has(c, X86_FEATURE_AUTOIBRS)) 1166 WARN_ON_ONCE(msr_set_bit(MSR_EFER, _EFER_AUTOIBRS) < 0); 1167 1168 /* AMD CPUs don't need fencing after x2APIC/TSC_DEADLINE MSR writes. */ 1169 clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE); 1170 1171 /* Enable Translation Cache Extension */ 1172 if (cpu_has(c, X86_FEATURE_TCE)) 1173 msr_set_bit(MSR_EFER, _EFER_TCE); 1174 } 1175 1176 #ifdef CONFIG_X86_32 1177 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) 1178 { 1179 /* AMD errata T13 (order #21922) */ 1180 if (c->x86 == 6) { 1181 /* Duron Rev A0 */ 1182 if (c->x86_model == 3 && c->x86_stepping == 0) 1183 size = 64; 1184 /* Tbird rev A1/A2 */ 1185 if (c->x86_model == 4 && 1186 (c->x86_stepping == 0 || c->x86_stepping == 1)) 1187 size = 256; 1188 } 1189 return size; 1190 } 1191 #endif 1192 1193 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) 1194 { 1195 u32 ebx, eax, ecx, edx; 1196 u16 mask = 0xfff; 1197 1198 if (c->x86 < 0xf) 1199 return; 1200 1201 if (c->extended_cpuid_level < 0x80000006) 1202 return; 1203 1204 cpuid(0x80000006, &eax, &ebx, &ecx, &edx); 1205 1206 tlb_lld_4k = (ebx >> 16) & mask; 1207 tlb_lli_4k = ebx & mask; 1208 1209 /* 1210 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB 1211 * characteristics from the CPUID function 0x80000005 instead. 1212 */ 1213 if (c->x86 == 0xf) { 1214 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 1215 mask = 0xff; 1216 } 1217 1218 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 1219 if (!((eax >> 16) & mask)) 1220 tlb_lld_2m = (cpuid_eax(0x80000005) >> 16) & 0xff; 1221 else 1222 tlb_lld_2m = (eax >> 16) & mask; 1223 1224 /* a 4M entry uses two 2M entries */ 1225 tlb_lld_4m = tlb_lld_2m >> 1; 1226 1227 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 1228 if (!(eax & mask)) { 1229 /* Erratum 658 */ 1230 if (c->x86 == 0x15 && c->x86_model <= 0x1f) { 1231 tlb_lli_2m = 1024; 1232 } else { 1233 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 1234 tlb_lli_2m = eax & 0xff; 1235 } 1236 } else 1237 tlb_lli_2m = eax & mask; 1238 1239 tlb_lli_4m = tlb_lli_2m >> 1; 1240 1241 /* Max number of pages INVLPGB can invalidate in one shot */ 1242 if (cpu_has(c, X86_FEATURE_INVLPGB)) 1243 invlpgb_count_max = (cpuid_edx(0x80000008) & 0xffff) + 1; 1244 } 1245 1246 static const struct cpu_dev amd_cpu_dev = { 1247 .c_vendor = "AMD", 1248 .c_ident = { "AuthenticAMD" }, 1249 #ifdef CONFIG_X86_32 1250 .legacy_models = { 1251 { .family = 4, .model_names = 1252 { 1253 [3] = "486 DX/2", 1254 [7] = "486 DX/2-WB", 1255 [8] = "486 DX/4", 1256 [9] = "486 DX/4-WB", 1257 [14] = "Am5x86-WT", 1258 [15] = "Am5x86-WB" 1259 } 1260 }, 1261 }, 1262 .legacy_cache_size = amd_size_cache, 1263 #endif 1264 .c_early_init = early_init_amd, 1265 .c_detect_tlb = cpu_detect_tlb_amd, 1266 .c_bsp_init = bsp_init_amd, 1267 .c_init = init_amd, 1268 .c_x86_vendor = X86_VENDOR_AMD, 1269 }; 1270 1271 cpu_dev_register(amd_cpu_dev); 1272 1273 static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[4], amd_dr_addr_mask); 1274 1275 static unsigned int amd_msr_dr_addr_masks[] = { 1276 MSR_F16H_DR0_ADDR_MASK, 1277 MSR_F16H_DR1_ADDR_MASK, 1278 MSR_F16H_DR1_ADDR_MASK + 1, 1279 MSR_F16H_DR1_ADDR_MASK + 2 1280 }; 1281 1282 void amd_set_dr_addr_mask(unsigned long mask, unsigned int dr) 1283 { 1284 int cpu = smp_processor_id(); 1285 1286 if (!cpu_feature_enabled(X86_FEATURE_BPEXT)) 1287 return; 1288 1289 if (WARN_ON_ONCE(dr >= ARRAY_SIZE(amd_msr_dr_addr_masks))) 1290 return; 1291 1292 if (per_cpu(amd_dr_addr_mask, cpu)[dr] == mask) 1293 return; 1294 1295 wrmsrq(amd_msr_dr_addr_masks[dr], mask); 1296 per_cpu(amd_dr_addr_mask, cpu)[dr] = mask; 1297 } 1298 1299 unsigned long amd_get_dr_addr_mask(unsigned int dr) 1300 { 1301 if (!cpu_feature_enabled(X86_FEATURE_BPEXT)) 1302 return 0; 1303 1304 if (WARN_ON_ONCE(dr >= ARRAY_SIZE(amd_msr_dr_addr_masks))) 1305 return 0; 1306 1307 return per_cpu(amd_dr_addr_mask[dr], smp_processor_id()); 1308 } 1309 EXPORT_SYMBOL_FOR_KVM(amd_get_dr_addr_mask); 1310 1311 static void zenbleed_check_cpu(void *unused) 1312 { 1313 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 1314 1315 zen2_zenbleed_check(c); 1316 } 1317 1318 void amd_check_microcode(void) 1319 { 1320 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) 1321 return; 1322 1323 if (cpu_feature_enabled(X86_FEATURE_ZEN2)) 1324 on_each_cpu(zenbleed_check_cpu, NULL, 1); 1325 } 1326 1327 static const char * const s5_reset_reason_txt[] = { 1328 [0] = "thermal pin BP_THERMTRIP_L was tripped", 1329 [1] = "power button was pressed for 4 seconds", 1330 [2] = "shutdown pin was tripped", 1331 [4] = "remote ASF power off command was received", 1332 [9] = "internal CPU thermal limit was tripped", 1333 [16] = "system reset pin BP_SYS_RST_L was tripped", 1334 [17] = "software issued PCI reset", 1335 [18] = "software wrote 0x4 to reset control register 0xCF9", 1336 [19] = "software wrote 0x6 to reset control register 0xCF9", 1337 [20] = "software wrote 0xE to reset control register 0xCF9", 1338 [21] = "ACPI power state transition occurred", 1339 [22] = "keyboard reset pin KB_RST_L was tripped", 1340 [23] = "internal CPU shutdown event occurred", 1341 [24] = "system failed to boot before failed boot timer expired", 1342 [25] = "hardware watchdog timer expired", 1343 [26] = "remote ASF reset command was received", 1344 [27] = "an uncorrected error caused a data fabric sync flood event", 1345 [29] = "FCH and MP1 failed warm reset handshake", 1346 [30] = "a parity error occurred", 1347 [31] = "a software sync flood event occurred", 1348 }; 1349 1350 static __init int print_s5_reset_status_mmio(void) 1351 { 1352 void __iomem *addr; 1353 u32 value; 1354 int i; 1355 1356 if (!cpu_feature_enabled(X86_FEATURE_ZEN)) 1357 return 0; 1358 1359 addr = ioremap(FCH_PM_BASE + FCH_PM_S5_RESET_STATUS, sizeof(value)); 1360 if (!addr) 1361 return 0; 1362 1363 value = ioread32(addr); 1364 1365 /* Value with "all bits set" is an error response and should be ignored. */ 1366 if (value == U32_MAX) { 1367 iounmap(addr); 1368 return 0; 1369 } 1370 1371 /* 1372 * Clear all reason bits so they won't be retained if the next reset 1373 * does not update the register. Besides, some bits are never cleared by 1374 * hardware so it's software's responsibility to clear them. 1375 * 1376 * Writing the value back effectively clears all reason bits as they are 1377 * write-1-to-clear. 1378 */ 1379 iowrite32(value, addr); 1380 iounmap(addr); 1381 1382 for (i = 0; i < ARRAY_SIZE(s5_reset_reason_txt); i++) { 1383 if (!(value & BIT(i))) 1384 continue; 1385 1386 if (s5_reset_reason_txt[i]) { 1387 pr_info("x86/amd: Previous system reset reason [0x%08x]: %s\n", 1388 value, s5_reset_reason_txt[i]); 1389 } 1390 } 1391 1392 return 0; 1393 } 1394 late_initcall(print_s5_reset_status_mmio); 1395 1396 static void __init dmi_scan_additional(const struct dmi_header *d, void *p) 1397 { 1398 struct dmi_a_info *info = (struct dmi_a_info *)d; 1399 void *next, *end; 1400 1401 if (!IS_ENABLED(CONFIG_DMI)) 1402 return; 1403 1404 if (info->header.type != DMI_ENTRY_ADDITIONAL || 1405 info->header.length < DMI_A_INFO_MIN_SIZE || 1406 info->count < 1) 1407 return; 1408 1409 next = (void *)(info + 1); 1410 end = (void *)info + info->header.length; 1411 1412 do { 1413 struct dmi_a_info_entry *entry; 1414 const char *string_ptr; 1415 1416 entry = (struct dmi_a_info_entry *)next; 1417 1418 /* 1419 * Not much can be done to validate data. At least the entry 1420 * length shouldn't be 0. 1421 */ 1422 if (!entry->length) 1423 return; 1424 1425 string_ptr = dmi_string_nosave(&info->header, entry->str_num); 1426 1427 /* Sample string: AGESA!V9 StrixKrackanPI-FP8 1.1.0.0c */ 1428 if (!strncmp(string_ptr, "AGESA", 5)) { 1429 pr_info("AGESA: %s\n", string_ptr); 1430 break; 1431 } 1432 1433 next += entry->length; 1434 } while (end - next >= DMI_A_INFO_ENT_MIN_SIZE); 1435 } 1436 1437 static __init int print_dmi_agesa(void) 1438 { 1439 dmi_walk(dmi_scan_additional, NULL); 1440 return 0; 1441 } 1442 late_initcall(print_dmi_agesa); 1443