1 // SPDX-License-Identifier: GPL-2.0-only 2 #include <linux/export.h> 3 #include <linux/bitops.h> 4 #include <linux/elf.h> 5 #include <linux/mm.h> 6 7 #include <linux/io.h> 8 #include <linux/sched.h> 9 #include <linux/sched/clock.h> 10 #include <linux/random.h> 11 #include <linux/topology.h> 12 #include <asm/processor.h> 13 #include <asm/apic.h> 14 #include <asm/cacheinfo.h> 15 #include <asm/cpu.h> 16 #include <asm/cpu_device_id.h> 17 #include <asm/spec-ctrl.h> 18 #include <asm/smp.h> 19 #include <asm/numa.h> 20 #include <asm/pci-direct.h> 21 #include <asm/delay.h> 22 #include <asm/debugreg.h> 23 #include <asm/resctrl.h> 24 #include <asm/msr.h> 25 #include <asm/sev.h> 26 27 #ifdef CONFIG_X86_64 28 # include <asm/mmconfig.h> 29 #endif 30 31 #include "cpu.h" 32 33 u16 invlpgb_count_max __ro_after_init; 34 35 static inline int rdmsrq_amd_safe(unsigned msr, u64 *p) 36 { 37 u32 gprs[8] = { 0 }; 38 int err; 39 40 WARN_ONCE((boot_cpu_data.x86 != 0xf), 41 "%s should only be used on K8!\n", __func__); 42 43 gprs[1] = msr; 44 gprs[7] = 0x9c5a203a; 45 46 err = rdmsr_safe_regs(gprs); 47 48 *p = gprs[0] | ((u64)gprs[2] << 32); 49 50 return err; 51 } 52 53 static inline int wrmsrq_amd_safe(unsigned msr, u64 val) 54 { 55 u32 gprs[8] = { 0 }; 56 57 WARN_ONCE((boot_cpu_data.x86 != 0xf), 58 "%s should only be used on K8!\n", __func__); 59 60 gprs[0] = (u32)val; 61 gprs[1] = msr; 62 gprs[2] = val >> 32; 63 gprs[7] = 0x9c5a203a; 64 65 return wrmsr_safe_regs(gprs); 66 } 67 68 /* 69 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 70 * misexecution of code under Linux. Owners of such processors should 71 * contact AMD for precise details and a CPU swap. 72 * 73 * See http://www.multimania.com/poulot/k6bug.html 74 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" 75 * (Publication # 21266 Issue Date: August 1998) 76 * 77 * The following test is erm.. interesting. AMD neglected to up 78 * the chip setting when fixing the bug but they also tweaked some 79 * performance at the same time.. 80 */ 81 82 #ifdef CONFIG_X86_32 83 extern __visible void vide(void); 84 __asm__(".text\n" 85 ".globl vide\n" 86 ".type vide, @function\n" 87 ".align 4\n" 88 "vide: ret\n"); 89 #endif 90 91 static void init_amd_k5(struct cpuinfo_x86 *c) 92 { 93 #ifdef CONFIG_X86_32 94 /* 95 * General Systems BIOSen alias the cpu frequency registers 96 * of the Elan at 0x000df000. Unfortunately, one of the Linux 97 * drivers subsequently pokes it, and changes the CPU speed. 98 * Workaround : Remove the unneeded alias. 99 */ 100 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 101 #define CBAR_ENB (0x80000000) 102 #define CBAR_KEY (0X000000CB) 103 if (c->x86_model == 9 || c->x86_model == 10) { 104 if (inl(CBAR) & CBAR_ENB) 105 outl(0 | CBAR_KEY, CBAR); 106 } 107 #endif 108 } 109 110 static void init_amd_k6(struct cpuinfo_x86 *c) 111 { 112 #ifdef CONFIG_X86_32 113 u32 l, h; 114 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); 115 116 if (c->x86_model < 6) { 117 /* Based on AMD doc 20734R - June 2000 */ 118 if (c->x86_model == 0) { 119 clear_cpu_cap(c, X86_FEATURE_APIC); 120 set_cpu_cap(c, X86_FEATURE_PGE); 121 } 122 return; 123 } 124 125 if (c->x86_model == 6 && c->x86_stepping == 1) { 126 const int K6_BUG_LOOP = 1000000; 127 int n; 128 void (*f_vide)(void); 129 u64 d, d2; 130 131 pr_info("AMD K6 stepping B detected - "); 132 133 /* 134 * It looks like AMD fixed the 2.6.2 bug and improved indirect 135 * calls at the same time. 136 */ 137 138 n = K6_BUG_LOOP; 139 f_vide = vide; 140 OPTIMIZER_HIDE_VAR(f_vide); 141 d = rdtsc(); 142 while (n--) 143 f_vide(); 144 d2 = rdtsc(); 145 d = d2-d; 146 147 if (d > 20*K6_BUG_LOOP) 148 pr_cont("system stability may be impaired when more than 32 MB are used.\n"); 149 else 150 pr_cont("probably OK (after B9730xxxx).\n"); 151 } 152 153 /* K6 with old style WHCR */ 154 if (c->x86_model < 8 || 155 (c->x86_model == 8 && c->x86_stepping < 8)) { 156 /* We can only write allocate on the low 508Mb */ 157 if (mbytes > 508) 158 mbytes = 508; 159 160 rdmsr(MSR_K6_WHCR, l, h); 161 if ((l&0x0000FFFF) == 0) { 162 unsigned long flags; 163 l = (1<<0)|((mbytes/4)<<1); 164 local_irq_save(flags); 165 wbinvd(); 166 wrmsr(MSR_K6_WHCR, l, h); 167 local_irq_restore(flags); 168 pr_info("Enabling old style K6 write allocation for %d Mb\n", 169 mbytes); 170 } 171 return; 172 } 173 174 if ((c->x86_model == 8 && c->x86_stepping > 7) || 175 c->x86_model == 9 || c->x86_model == 13) { 176 /* The more serious chips .. */ 177 178 if (mbytes > 4092) 179 mbytes = 4092; 180 181 rdmsr(MSR_K6_WHCR, l, h); 182 if ((l&0xFFFF0000) == 0) { 183 unsigned long flags; 184 l = ((mbytes>>2)<<22)|(1<<16); 185 local_irq_save(flags); 186 wbinvd(); 187 wrmsr(MSR_K6_WHCR, l, h); 188 local_irq_restore(flags); 189 pr_info("Enabling new style K6 write allocation for %d Mb\n", 190 mbytes); 191 } 192 193 return; 194 } 195 196 if (c->x86_model == 10) { 197 /* AMD Geode LX is model 10 */ 198 /* placeholder for any needed mods */ 199 return; 200 } 201 #endif 202 } 203 204 static void init_amd_k7(struct cpuinfo_x86 *c) 205 { 206 #ifdef CONFIG_X86_32 207 u32 l, h; 208 209 /* 210 * Bit 15 of Athlon specific MSR 15, needs to be 0 211 * to enable SSE on Palomino/Morgan/Barton CPU's. 212 * If the BIOS didn't enable it already, enable it here. 213 */ 214 if (c->x86_model >= 6 && c->x86_model <= 10) { 215 if (!cpu_has(c, X86_FEATURE_XMM)) { 216 pr_info("Enabling disabled K7/SSE Support.\n"); 217 msr_clear_bit(MSR_K7_HWCR, 15); 218 set_cpu_cap(c, X86_FEATURE_XMM); 219 } 220 } 221 222 /* 223 * It's been determined by AMD that Athlons since model 8 stepping 1 224 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 225 * As per AMD technical note 27212 0.2 226 */ 227 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) { 228 rdmsr(MSR_K7_CLK_CTL, l, h); 229 if ((l & 0xfff00000) != 0x20000000) { 230 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", 231 l, ((l & 0x000fffff)|0x20000000)); 232 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 233 } 234 } 235 236 /* calling is from identify_secondary_cpu() ? */ 237 if (!c->cpu_index) 238 return; 239 240 /* 241 * Certain Athlons might work (for various values of 'work') in SMP 242 * but they are not certified as MP capable. 243 */ 244 /* Athlon 660/661 is valid. */ 245 if ((c->x86_model == 6) && ((c->x86_stepping == 0) || 246 (c->x86_stepping == 1))) 247 return; 248 249 /* Duron 670 is valid */ 250 if ((c->x86_model == 7) && (c->x86_stepping == 0)) 251 return; 252 253 /* 254 * Athlon 662, Duron 671, and Athlon >model 7 have capability 255 * bit. It's worth noting that the A5 stepping (662) of some 256 * Athlon XP's have the MP bit set. 257 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for 258 * more. 259 */ 260 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) || 261 ((c->x86_model == 7) && (c->x86_stepping >= 1)) || 262 (c->x86_model > 7)) 263 if (cpu_has(c, X86_FEATURE_MP)) 264 return; 265 266 /* If we get here, not a certified SMP capable AMD system. */ 267 268 /* 269 * Don't taint if we are running SMP kernel on a single non-MP 270 * approved Athlon 271 */ 272 WARN_ONCE(1, "WARNING: This combination of AMD" 273 " processors is not suitable for SMP.\n"); 274 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 275 #endif 276 } 277 278 #ifdef CONFIG_NUMA 279 /* 280 * To workaround broken NUMA config. Read the comment in 281 * srat_detect_node(). 282 */ 283 static int nearby_node(int apicid) 284 { 285 int i, node; 286 287 for (i = apicid - 1; i >= 0; i--) { 288 node = __apicid_to_node[i]; 289 if (node != NUMA_NO_NODE && node_online(node)) 290 return node; 291 } 292 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 293 node = __apicid_to_node[i]; 294 if (node != NUMA_NO_NODE && node_online(node)) 295 return node; 296 } 297 return first_node(node_online_map); /* Shouldn't happen */ 298 } 299 #endif 300 301 static void srat_detect_node(struct cpuinfo_x86 *c) 302 { 303 #ifdef CONFIG_NUMA 304 int cpu = smp_processor_id(); 305 int node; 306 unsigned apicid = c->topo.apicid; 307 308 node = numa_cpu_node(cpu); 309 if (node == NUMA_NO_NODE) 310 node = per_cpu_llc_id(cpu); 311 312 /* 313 * On multi-fabric platform (e.g. Numascale NumaChip) a 314 * platform-specific handler needs to be called to fixup some 315 * IDs of the CPU. 316 */ 317 if (x86_cpuinit.fixup_cpu_id) 318 x86_cpuinit.fixup_cpu_id(c, node); 319 320 if (!node_online(node)) { 321 /* 322 * Two possibilities here: 323 * 324 * - The CPU is missing memory and no node was created. In 325 * that case try picking one from a nearby CPU. 326 * 327 * - The APIC IDs differ from the HyperTransport node IDs 328 * which the K8 northbridge parsing fills in. Assume 329 * they are all increased by a constant offset, but in 330 * the same order as the HT nodeids. If that doesn't 331 * result in a usable node fall back to the path for the 332 * previous case. 333 * 334 * This workaround operates directly on the mapping between 335 * APIC ID and NUMA node, assuming certain relationship 336 * between APIC ID, HT node ID and NUMA topology. As going 337 * through CPU mapping may alter the outcome, directly 338 * access __apicid_to_node[]. 339 */ 340 int ht_nodeid = c->topo.initial_apicid; 341 342 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 343 node = __apicid_to_node[ht_nodeid]; 344 /* Pick a nearby node */ 345 if (!node_online(node)) 346 node = nearby_node(apicid); 347 } 348 numa_set_node(cpu, node); 349 #endif 350 } 351 352 static void bsp_determine_snp(struct cpuinfo_x86 *c) 353 { 354 #ifdef CONFIG_ARCH_HAS_CC_PLATFORM 355 cc_vendor = CC_VENDOR_AMD; 356 357 if (cpu_has(c, X86_FEATURE_SEV_SNP)) { 358 /* 359 * RMP table entry format is not architectural and is defined by the 360 * per-processor PPR. Restrict SNP support on the known CPU models 361 * for which the RMP table entry format is currently defined or for 362 * processors which support the architecturally defined RMPREAD 363 * instruction. 364 */ 365 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && 366 (cpu_feature_enabled(X86_FEATURE_ZEN3) || 367 cpu_feature_enabled(X86_FEATURE_ZEN4) || 368 cpu_feature_enabled(X86_FEATURE_RMPREAD)) && 369 snp_probe_rmptable_info()) { 370 cc_platform_set(CC_ATTR_HOST_SEV_SNP); 371 } else { 372 setup_clear_cpu_cap(X86_FEATURE_SEV_SNP); 373 cc_platform_clear(CC_ATTR_HOST_SEV_SNP); 374 } 375 } 376 #endif 377 } 378 379 static void bsp_init_amd(struct cpuinfo_x86 *c) 380 { 381 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 382 383 if (c->x86 > 0x10 || 384 (c->x86 == 0x10 && c->x86_model >= 0x2)) { 385 u64 val; 386 387 rdmsrq(MSR_K7_HWCR, val); 388 if (!(val & BIT(24))) 389 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); 390 } 391 } 392 393 if (c->x86 == 0x15) { 394 unsigned long upperbit; 395 u32 cpuid, assoc; 396 397 cpuid = cpuid_edx(0x80000005); 398 assoc = cpuid >> 16 & 0xff; 399 upperbit = ((cpuid >> 24) << 10) / assoc; 400 401 va_align.mask = (upperbit - 1) & PAGE_MASK; 402 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; 403 404 /* A random value per boot for bit slice [12:upper_bit) */ 405 va_align.bits = get_random_u32() & va_align.mask; 406 } 407 408 if (cpu_has(c, X86_FEATURE_MWAITX)) 409 use_mwaitx_delay(); 410 411 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) && 412 !boot_cpu_has(X86_FEATURE_VIRT_SSBD) && 413 c->x86 >= 0x15 && c->x86 <= 0x17) { 414 unsigned int bit; 415 416 switch (c->x86) { 417 case 0x15: bit = 54; break; 418 case 0x16: bit = 33; break; 419 case 0x17: bit = 10; break; 420 default: return; 421 } 422 /* 423 * Try to cache the base value so further operations can 424 * avoid RMW. If that faults, do not enable SSBD. 425 */ 426 if (!rdmsrq_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) { 427 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD); 428 setup_force_cpu_cap(X86_FEATURE_SSBD); 429 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit; 430 } 431 } 432 433 resctrl_cpu_detect(c); 434 435 /* Figure out Zen generations: */ 436 switch (c->x86) { 437 case 0x17: 438 switch (c->x86_model) { 439 case 0x00 ... 0x2f: 440 case 0x50 ... 0x5f: 441 setup_force_cpu_cap(X86_FEATURE_ZEN1); 442 break; 443 case 0x30 ... 0x4f: 444 case 0x60 ... 0x7f: 445 case 0x90 ... 0x91: 446 case 0xa0 ... 0xaf: 447 setup_force_cpu_cap(X86_FEATURE_ZEN2); 448 break; 449 default: 450 goto warn; 451 } 452 break; 453 454 case 0x19: 455 switch (c->x86_model) { 456 case 0x00 ... 0x0f: 457 case 0x20 ... 0x5f: 458 setup_force_cpu_cap(X86_FEATURE_ZEN3); 459 break; 460 case 0x10 ... 0x1f: 461 case 0x60 ... 0xaf: 462 setup_force_cpu_cap(X86_FEATURE_ZEN4); 463 break; 464 default: 465 goto warn; 466 } 467 break; 468 469 case 0x1a: 470 switch (c->x86_model) { 471 case 0x00 ... 0x2f: 472 case 0x40 ... 0x4f: 473 case 0x60 ... 0x7f: 474 setup_force_cpu_cap(X86_FEATURE_ZEN5); 475 break; 476 default: 477 goto warn; 478 } 479 break; 480 481 default: 482 break; 483 } 484 485 bsp_determine_snp(c); 486 return; 487 488 warn: 489 WARN_ONCE(1, "Family 0x%x, model: 0x%x??\n", c->x86, c->x86_model); 490 } 491 492 static void early_detect_mem_encrypt(struct cpuinfo_x86 *c) 493 { 494 u64 msr; 495 496 /* 497 * BIOS support is required for SME and SEV. 498 * For SME: If BIOS has enabled SME then adjust x86_phys_bits by 499 * the SME physical address space reduction value. 500 * If BIOS has not enabled SME then don't advertise the 501 * SME feature (set in scattered.c). 502 * If the kernel has not enabled SME via any means then 503 * don't advertise the SME feature. 504 * For SEV: If BIOS has not enabled SEV then don't advertise SEV and 505 * any additional functionality based on it. 506 * 507 * In all cases, since support for SME and SEV requires long mode, 508 * don't advertise the feature under CONFIG_X86_32. 509 */ 510 if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) { 511 /* Check if memory encryption is enabled */ 512 rdmsrq(MSR_AMD64_SYSCFG, msr); 513 if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT)) 514 goto clear_all; 515 516 /* 517 * Always adjust physical address bits. Even though this 518 * will be a value above 32-bits this is still done for 519 * CONFIG_X86_32 so that accurate values are reported. 520 */ 521 c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f; 522 523 if (IS_ENABLED(CONFIG_X86_32)) 524 goto clear_all; 525 526 if (!sme_me_mask) 527 setup_clear_cpu_cap(X86_FEATURE_SME); 528 529 rdmsrq(MSR_K7_HWCR, msr); 530 if (!(msr & MSR_K7_HWCR_SMMLOCK)) 531 goto clear_sev; 532 533 return; 534 535 clear_all: 536 setup_clear_cpu_cap(X86_FEATURE_SME); 537 clear_sev: 538 setup_clear_cpu_cap(X86_FEATURE_SEV); 539 setup_clear_cpu_cap(X86_FEATURE_SEV_ES); 540 setup_clear_cpu_cap(X86_FEATURE_SEV_SNP); 541 } 542 } 543 544 static void early_init_amd(struct cpuinfo_x86 *c) 545 { 546 u32 dummy; 547 548 if (c->x86 >= 0xf) 549 set_cpu_cap(c, X86_FEATURE_K8); 550 551 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); 552 553 /* 554 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 555 * with P/T states and does not stop in deep C-states 556 */ 557 if (c->x86_power & (1 << 8)) { 558 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 559 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 560 } 561 562 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ 563 if (c->x86_power & BIT(12)) 564 set_cpu_cap(c, X86_FEATURE_ACC_POWER); 565 566 /* Bit 14 indicates the Runtime Average Power Limit interface. */ 567 if (c->x86_power & BIT(14)) 568 set_cpu_cap(c, X86_FEATURE_RAPL); 569 570 #ifdef CONFIG_X86_64 571 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 572 #else 573 /* Set MTRR capability flag if appropriate */ 574 if (c->x86 == 5) 575 if (c->x86_model == 13 || c->x86_model == 9 || 576 (c->x86_model == 8 && c->x86_stepping >= 8)) 577 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 578 #endif 579 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 580 /* 581 * ApicID can always be treated as an 8-bit value for AMD APIC versions 582 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we 583 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families 584 * after 16h. 585 */ 586 if (boot_cpu_has(X86_FEATURE_APIC)) { 587 if (c->x86 > 0x16) 588 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 589 else if (c->x86 >= 0xf) { 590 /* check CPU config space for extended APIC ID */ 591 unsigned int val; 592 593 val = read_pci_config(0, 24, 0, 0x68); 594 if ((val >> 17 & 0x3) == 0x3) 595 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 596 } 597 } 598 #endif 599 600 /* 601 * This is only needed to tell the kernel whether to use VMCALL 602 * and VMMCALL. VMMCALL is never executed except under virt, so 603 * we can set it unconditionally. 604 */ 605 set_cpu_cap(c, X86_FEATURE_VMMCALL); 606 607 /* F16h erratum 793, CVE-2013-6885 */ 608 if (c->x86 == 0x16 && c->x86_model <= 0xf) 609 msr_set_bit(MSR_AMD64_LS_CFG, 15); 610 611 early_detect_mem_encrypt(c); 612 613 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && !cpu_has(c, X86_FEATURE_IBPB_BRTYPE)) { 614 if (c->x86 == 0x17 && boot_cpu_has(X86_FEATURE_AMD_IBPB)) 615 setup_force_cpu_cap(X86_FEATURE_IBPB_BRTYPE); 616 else if (c->x86 >= 0x19 && !wrmsrq_safe(MSR_IA32_PRED_CMD, PRED_CMD_SBPB)) { 617 setup_force_cpu_cap(X86_FEATURE_IBPB_BRTYPE); 618 setup_force_cpu_cap(X86_FEATURE_SBPB); 619 } 620 } 621 } 622 623 static void init_amd_k8(struct cpuinfo_x86 *c) 624 { 625 u32 level; 626 u64 value; 627 628 /* On C+ stepping K8 rep microcode works well for copy/memset */ 629 level = cpuid_eax(1); 630 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) 631 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 632 633 /* 634 * Some BIOSes incorrectly force this feature, but only K8 revision D 635 * (model = 0x14) and later actually support it. 636 * (AMD Erratum #110, docId: 25759). 637 */ 638 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM) && !cpu_has(c, X86_FEATURE_HYPERVISOR)) { 639 clear_cpu_cap(c, X86_FEATURE_LAHF_LM); 640 if (!rdmsrq_amd_safe(0xc001100d, &value)) { 641 value &= ~BIT_64(32); 642 wrmsrq_amd_safe(0xc001100d, value); 643 } 644 } 645 646 if (!c->x86_model_id[0]) 647 strcpy(c->x86_model_id, "Hammer"); 648 649 #ifdef CONFIG_SMP 650 /* 651 * Disable TLB flush filter by setting HWCR.FFDIS on K8 652 * bit 6 of msr C001_0015 653 * 654 * Errata 63 for SH-B3 steppings 655 * Errata 122 for all steppings (F+ have it disabled by default) 656 */ 657 msr_set_bit(MSR_K7_HWCR, 6); 658 #endif 659 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE); 660 661 /* 662 * Check models and steppings affected by erratum 400. This is 663 * used to select the proper idle routine and to enable the 664 * check whether the machine is affected in arch_post_acpi_subsys_init() 665 * which sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check. 666 */ 667 if (c->x86_model > 0x41 || 668 (c->x86_model == 0x41 && c->x86_stepping >= 0x2)) 669 setup_force_cpu_bug(X86_BUG_AMD_E400); 670 } 671 672 static void init_amd_gh(struct cpuinfo_x86 *c) 673 { 674 #ifdef CONFIG_MMCONF_FAM10H 675 /* do this for boot cpu */ 676 if (c == &boot_cpu_data) 677 check_enable_amd_mmconf_dmi(); 678 679 fam10h_check_enable_mmcfg(); 680 #endif 681 682 /* 683 * Disable GART TLB Walk Errors on Fam10h. We do this here because this 684 * is always needed when GART is enabled, even in a kernel which has no 685 * MCE support built in. BIOS should disable GartTlbWlk Errors already. 686 * If it doesn't, we do it here as suggested by the BKDG. 687 * 688 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 689 */ 690 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10); 691 692 /* 693 * On family 10h BIOS may not have properly enabled WC+ support, causing 694 * it to be converted to CD memtype. This may result in performance 695 * degradation for certain nested-paging guests. Prevent this conversion 696 * by clearing bit 24 in MSR_AMD64_BU_CFG2. 697 * 698 * NOTE: we want to use the _safe accessors so as not to #GP kvm 699 * guests on older kvm hosts. 700 */ 701 msr_clear_bit(MSR_AMD64_BU_CFG2, 24); 702 703 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH); 704 705 /* 706 * Check models and steppings affected by erratum 400. This is 707 * used to select the proper idle routine and to enable the 708 * check whether the machine is affected in arch_post_acpi_subsys_init() 709 * which sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check. 710 */ 711 if (c->x86_model > 0x2 || 712 (c->x86_model == 0x2 && c->x86_stepping >= 0x1)) 713 setup_force_cpu_bug(X86_BUG_AMD_E400); 714 } 715 716 static void init_amd_ln(struct cpuinfo_x86 *c) 717 { 718 /* 719 * Apply erratum 665 fix unconditionally so machines without a BIOS 720 * fix work. 721 */ 722 msr_set_bit(MSR_AMD64_DE_CFG, 31); 723 } 724 725 static bool rdrand_force; 726 727 static int __init rdrand_cmdline(char *str) 728 { 729 if (!str) 730 return -EINVAL; 731 732 if (!strcmp(str, "force")) 733 rdrand_force = true; 734 else 735 return -EINVAL; 736 737 return 0; 738 } 739 early_param("rdrand", rdrand_cmdline); 740 741 static void clear_rdrand_cpuid_bit(struct cpuinfo_x86 *c) 742 { 743 /* 744 * Saving of the MSR used to hide the RDRAND support during 745 * suspend/resume is done by arch/x86/power/cpu.c, which is 746 * dependent on CONFIG_PM_SLEEP. 747 */ 748 if (!IS_ENABLED(CONFIG_PM_SLEEP)) 749 return; 750 751 /* 752 * The self-test can clear X86_FEATURE_RDRAND, so check for 753 * RDRAND support using the CPUID function directly. 754 */ 755 if (!(cpuid_ecx(1) & BIT(30)) || rdrand_force) 756 return; 757 758 msr_clear_bit(MSR_AMD64_CPUID_FN_1, 62); 759 760 /* 761 * Verify that the CPUID change has occurred in case the kernel is 762 * running virtualized and the hypervisor doesn't support the MSR. 763 */ 764 if (cpuid_ecx(1) & BIT(30)) { 765 pr_info_once("BIOS may not properly restore RDRAND after suspend, but hypervisor does not support hiding RDRAND via CPUID.\n"); 766 return; 767 } 768 769 clear_cpu_cap(c, X86_FEATURE_RDRAND); 770 pr_info_once("BIOS may not properly restore RDRAND after suspend, hiding RDRAND via CPUID. Use rdrand=force to reenable.\n"); 771 } 772 773 static void init_amd_jg(struct cpuinfo_x86 *c) 774 { 775 /* 776 * Some BIOS implementations do not restore proper RDRAND support 777 * across suspend and resume. Check on whether to hide the RDRAND 778 * instruction support via CPUID. 779 */ 780 clear_rdrand_cpuid_bit(c); 781 } 782 783 static void init_amd_bd(struct cpuinfo_x86 *c) 784 { 785 u64 value; 786 787 /* 788 * The way access filter has a performance penalty on some workloads. 789 * Disable it on the affected CPUs. 790 */ 791 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) { 792 if (!rdmsrq_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) { 793 value |= 0x1E; 794 wrmsrq_safe(MSR_F15H_IC_CFG, value); 795 } 796 } 797 798 /* 799 * Some BIOS implementations do not restore proper RDRAND support 800 * across suspend and resume. Check on whether to hide the RDRAND 801 * instruction support via CPUID. 802 */ 803 clear_rdrand_cpuid_bit(c); 804 } 805 806 static const struct x86_cpu_id erratum_1386_microcode[] = { 807 X86_MATCH_VFM_STEPS(VFM_MAKE(X86_VENDOR_AMD, 0x17, 0x01), 0x2, 0x2, 0x0800126e), 808 X86_MATCH_VFM_STEPS(VFM_MAKE(X86_VENDOR_AMD, 0x17, 0x31), 0x0, 0x0, 0x08301052), 809 {} 810 }; 811 812 static void fix_erratum_1386(struct cpuinfo_x86 *c) 813 { 814 /* 815 * Work around Erratum 1386. The XSAVES instruction malfunctions in 816 * certain circumstances on Zen1/2 uarch, and not all parts have had 817 * updated microcode at the time of writing (March 2023). 818 * 819 * Affected parts all have no supervisor XSAVE states, meaning that 820 * the XSAVEC instruction (which works fine) is equivalent. 821 * 822 * Clear the feature flag only on microcode revisions which 823 * don't have the fix. 824 */ 825 if (x86_match_min_microcode_rev(erratum_1386_microcode)) 826 return; 827 828 clear_cpu_cap(c, X86_FEATURE_XSAVES); 829 } 830 831 void init_spectral_chicken(struct cpuinfo_x86 *c) 832 { 833 #ifdef CONFIG_MITIGATION_UNRET_ENTRY 834 u64 value; 835 836 /* 837 * On Zen2 we offer this chicken (bit) on the altar of Speculation. 838 * 839 * This suppresses speculation from the middle of a basic block, i.e. it 840 * suppresses non-branch predictions. 841 */ 842 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) { 843 if (!rdmsrq_safe(MSR_ZEN2_SPECTRAL_CHICKEN, &value)) { 844 value |= MSR_ZEN2_SPECTRAL_CHICKEN_BIT; 845 wrmsrq_safe(MSR_ZEN2_SPECTRAL_CHICKEN, value); 846 } 847 } 848 #endif 849 } 850 851 static void init_amd_zen_common(void) 852 { 853 setup_force_cpu_cap(X86_FEATURE_ZEN); 854 #ifdef CONFIG_NUMA 855 node_reclaim_distance = 32; 856 #endif 857 } 858 859 static void init_amd_zen1(struct cpuinfo_x86 *c) 860 { 861 fix_erratum_1386(c); 862 863 /* Fix up CPUID bits, but only if not virtualised. */ 864 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) { 865 866 /* Erratum 1076: CPB feature bit not being set in CPUID. */ 867 if (!cpu_has(c, X86_FEATURE_CPB)) 868 set_cpu_cap(c, X86_FEATURE_CPB); 869 } 870 871 pr_notice_once("AMD Zen1 DIV0 bug detected. Disable SMT for full protection.\n"); 872 setup_force_cpu_bug(X86_BUG_DIV0); 873 874 /* 875 * Turn off the Instructions Retired free counter on machines that are 876 * susceptible to erratum #1054 "Instructions Retired Performance 877 * Counter May Be Inaccurate". 878 */ 879 if (c->x86_model < 0x30) { 880 msr_clear_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT); 881 clear_cpu_cap(c, X86_FEATURE_IRPERF); 882 } 883 } 884 885 static bool cpu_has_zenbleed_microcode(void) 886 { 887 u32 good_rev = 0; 888 889 switch (boot_cpu_data.x86_model) { 890 case 0x30 ... 0x3f: good_rev = 0x0830107b; break; 891 case 0x60 ... 0x67: good_rev = 0x0860010c; break; 892 case 0x68 ... 0x6f: good_rev = 0x08608107; break; 893 case 0x70 ... 0x7f: good_rev = 0x08701033; break; 894 case 0xa0 ... 0xaf: good_rev = 0x08a00009; break; 895 896 default: 897 return false; 898 } 899 900 if (boot_cpu_data.microcode < good_rev) 901 return false; 902 903 return true; 904 } 905 906 static void zen2_zenbleed_check(struct cpuinfo_x86 *c) 907 { 908 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) 909 return; 910 911 if (!cpu_has(c, X86_FEATURE_AVX)) 912 return; 913 914 if (!cpu_has_zenbleed_microcode()) { 915 pr_notice_once("Zenbleed: please update your microcode for the most optimal fix\n"); 916 msr_set_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT); 917 } else { 918 msr_clear_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT); 919 } 920 } 921 922 static void init_amd_zen2(struct cpuinfo_x86 *c) 923 { 924 init_spectral_chicken(c); 925 fix_erratum_1386(c); 926 zen2_zenbleed_check(c); 927 } 928 929 static void init_amd_zen3(struct cpuinfo_x86 *c) 930 { 931 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) { 932 /* 933 * Zen3 (Fam19 model < 0x10) parts are not susceptible to 934 * Branch Type Confusion, but predate the allocation of the 935 * BTC_NO bit. 936 */ 937 if (!cpu_has(c, X86_FEATURE_BTC_NO)) 938 set_cpu_cap(c, X86_FEATURE_BTC_NO); 939 } 940 } 941 942 static void init_amd_zen4(struct cpuinfo_x86 *c) 943 { 944 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) 945 msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT); 946 947 /* 948 * These Zen4 SoCs advertise support for virtualized VMLOAD/VMSAVE 949 * in some BIOS versions but they can lead to random host reboots. 950 */ 951 switch (c->x86_model) { 952 case 0x18 ... 0x1f: 953 case 0x60 ... 0x7f: 954 clear_cpu_cap(c, X86_FEATURE_V_VMSAVE_VMLOAD); 955 break; 956 } 957 } 958 959 static void init_amd_zen5(struct cpuinfo_x86 *c) 960 { 961 } 962 963 static void init_amd(struct cpuinfo_x86 *c) 964 { 965 u64 vm_cr; 966 967 early_init_amd(c); 968 969 /* 970 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 971 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 972 */ 973 clear_cpu_cap(c, 0*32+31); 974 975 if (c->x86 >= 0x10) 976 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 977 978 /* AMD FSRM also implies FSRS */ 979 if (cpu_has(c, X86_FEATURE_FSRM)) 980 set_cpu_cap(c, X86_FEATURE_FSRS); 981 982 /* K6s reports MCEs but don't actually have all the MSRs */ 983 if (c->x86 < 6) 984 clear_cpu_cap(c, X86_FEATURE_MCE); 985 986 switch (c->x86) { 987 case 4: init_amd_k5(c); break; 988 case 5: init_amd_k6(c); break; 989 case 6: init_amd_k7(c); break; 990 case 0xf: init_amd_k8(c); break; 991 case 0x10: init_amd_gh(c); break; 992 case 0x12: init_amd_ln(c); break; 993 case 0x15: init_amd_bd(c); break; 994 case 0x16: init_amd_jg(c); break; 995 } 996 997 /* 998 * Save up on some future enablement work and do common Zen 999 * settings. 1000 */ 1001 if (c->x86 >= 0x17) 1002 init_amd_zen_common(); 1003 1004 if (boot_cpu_has(X86_FEATURE_ZEN1)) 1005 init_amd_zen1(c); 1006 else if (boot_cpu_has(X86_FEATURE_ZEN2)) 1007 init_amd_zen2(c); 1008 else if (boot_cpu_has(X86_FEATURE_ZEN3)) 1009 init_amd_zen3(c); 1010 else if (boot_cpu_has(X86_FEATURE_ZEN4)) 1011 init_amd_zen4(c); 1012 else if (boot_cpu_has(X86_FEATURE_ZEN5)) 1013 init_amd_zen5(c); 1014 1015 /* 1016 * Enable workaround for FXSAVE leak on CPUs 1017 * without a XSaveErPtr feature 1018 */ 1019 if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR))) 1020 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK); 1021 1022 cpu_detect_cache_sizes(c); 1023 1024 srat_detect_node(c); 1025 1026 init_amd_cacheinfo(c); 1027 1028 if (cpu_has(c, X86_FEATURE_SVM)) { 1029 rdmsrq(MSR_VM_CR, vm_cr); 1030 if (vm_cr & SVM_VM_CR_SVM_DIS_MASK) { 1031 pr_notice_once("SVM disabled (by BIOS) in MSR_VM_CR\n"); 1032 clear_cpu_cap(c, X86_FEATURE_SVM); 1033 } 1034 } 1035 1036 if (!cpu_has(c, X86_FEATURE_LFENCE_RDTSC) && cpu_has(c, X86_FEATURE_XMM2)) { 1037 /* 1038 * Use LFENCE for execution serialization. On families which 1039 * don't have that MSR, LFENCE is already serializing. 1040 * msr_set_bit() uses the safe accessors, too, even if the MSR 1041 * is not present. 1042 */ 1043 msr_set_bit(MSR_AMD64_DE_CFG, 1044 MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT); 1045 1046 /* A serializing LFENCE stops RDTSC speculation */ 1047 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 1048 } 1049 1050 /* 1051 * Family 0x12 and above processors have APIC timer 1052 * running in deep C states. 1053 */ 1054 if (c->x86 > 0x11) 1055 set_cpu_cap(c, X86_FEATURE_ARAT); 1056 1057 /* 3DNow or LM implies PREFETCHW */ 1058 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH)) 1059 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM)) 1060 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH); 1061 1062 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */ 1063 if (!cpu_feature_enabled(X86_FEATURE_XENPV)) 1064 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); 1065 1066 /* Enable the Instructions Retired free counter */ 1067 if (cpu_has(c, X86_FEATURE_IRPERF)) 1068 msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT); 1069 1070 check_null_seg_clears_base(c); 1071 1072 /* 1073 * Make sure EFER[AIBRSE - Automatic IBRS Enable] is set. The APs are brought up 1074 * using the trampoline code and as part of it, MSR_EFER gets prepared there in 1075 * order to be replicated onto them. Regardless, set it here again, if not set, 1076 * to protect against any future refactoring/code reorganization which might 1077 * miss setting this important bit. 1078 */ 1079 if (spectre_v2_in_eibrs_mode(spectre_v2_enabled) && 1080 cpu_has(c, X86_FEATURE_AUTOIBRS)) 1081 WARN_ON_ONCE(msr_set_bit(MSR_EFER, _EFER_AUTOIBRS) < 0); 1082 1083 /* AMD CPUs don't need fencing after x2APIC/TSC_DEADLINE MSR writes. */ 1084 clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE); 1085 1086 /* Enable Translation Cache Extension */ 1087 if (cpu_has(c, X86_FEATURE_TCE)) 1088 msr_set_bit(MSR_EFER, _EFER_TCE); 1089 } 1090 1091 #ifdef CONFIG_X86_32 1092 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) 1093 { 1094 /* AMD errata T13 (order #21922) */ 1095 if (c->x86 == 6) { 1096 /* Duron Rev A0 */ 1097 if (c->x86_model == 3 && c->x86_stepping == 0) 1098 size = 64; 1099 /* Tbird rev A1/A2 */ 1100 if (c->x86_model == 4 && 1101 (c->x86_stepping == 0 || c->x86_stepping == 1)) 1102 size = 256; 1103 } 1104 return size; 1105 } 1106 #endif 1107 1108 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) 1109 { 1110 u32 ebx, eax, ecx, edx; 1111 u16 mask = 0xfff; 1112 1113 if (c->x86 < 0xf) 1114 return; 1115 1116 if (c->extended_cpuid_level < 0x80000006) 1117 return; 1118 1119 cpuid(0x80000006, &eax, &ebx, &ecx, &edx); 1120 1121 tlb_lld_4k = (ebx >> 16) & mask; 1122 tlb_lli_4k = ebx & mask; 1123 1124 /* 1125 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB 1126 * characteristics from the CPUID function 0x80000005 instead. 1127 */ 1128 if (c->x86 == 0xf) { 1129 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 1130 mask = 0xff; 1131 } 1132 1133 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 1134 if (!((eax >> 16) & mask)) 1135 tlb_lld_2m = (cpuid_eax(0x80000005) >> 16) & 0xff; 1136 else 1137 tlb_lld_2m = (eax >> 16) & mask; 1138 1139 /* a 4M entry uses two 2M entries */ 1140 tlb_lld_4m = tlb_lld_2m >> 1; 1141 1142 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 1143 if (!(eax & mask)) { 1144 /* Erratum 658 */ 1145 if (c->x86 == 0x15 && c->x86_model <= 0x1f) { 1146 tlb_lli_2m = 1024; 1147 } else { 1148 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 1149 tlb_lli_2m = eax & 0xff; 1150 } 1151 } else 1152 tlb_lli_2m = eax & mask; 1153 1154 tlb_lli_4m = tlb_lli_2m >> 1; 1155 1156 /* Max number of pages INVLPGB can invalidate in one shot */ 1157 if (cpu_has(c, X86_FEATURE_INVLPGB)) 1158 invlpgb_count_max = (cpuid_edx(0x80000008) & 0xffff) + 1; 1159 } 1160 1161 static const struct cpu_dev amd_cpu_dev = { 1162 .c_vendor = "AMD", 1163 .c_ident = { "AuthenticAMD" }, 1164 #ifdef CONFIG_X86_32 1165 .legacy_models = { 1166 { .family = 4, .model_names = 1167 { 1168 [3] = "486 DX/2", 1169 [7] = "486 DX/2-WB", 1170 [8] = "486 DX/4", 1171 [9] = "486 DX/4-WB", 1172 [14] = "Am5x86-WT", 1173 [15] = "Am5x86-WB" 1174 } 1175 }, 1176 }, 1177 .legacy_cache_size = amd_size_cache, 1178 #endif 1179 .c_early_init = early_init_amd, 1180 .c_detect_tlb = cpu_detect_tlb_amd, 1181 .c_bsp_init = bsp_init_amd, 1182 .c_init = init_amd, 1183 .c_x86_vendor = X86_VENDOR_AMD, 1184 }; 1185 1186 cpu_dev_register(amd_cpu_dev); 1187 1188 static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[4], amd_dr_addr_mask); 1189 1190 static unsigned int amd_msr_dr_addr_masks[] = { 1191 MSR_F16H_DR0_ADDR_MASK, 1192 MSR_F16H_DR1_ADDR_MASK, 1193 MSR_F16H_DR1_ADDR_MASK + 1, 1194 MSR_F16H_DR1_ADDR_MASK + 2 1195 }; 1196 1197 void amd_set_dr_addr_mask(unsigned long mask, unsigned int dr) 1198 { 1199 int cpu = smp_processor_id(); 1200 1201 if (!cpu_feature_enabled(X86_FEATURE_BPEXT)) 1202 return; 1203 1204 if (WARN_ON_ONCE(dr >= ARRAY_SIZE(amd_msr_dr_addr_masks))) 1205 return; 1206 1207 if (per_cpu(amd_dr_addr_mask, cpu)[dr] == mask) 1208 return; 1209 1210 wrmsrq(amd_msr_dr_addr_masks[dr], mask); 1211 per_cpu(amd_dr_addr_mask, cpu)[dr] = mask; 1212 } 1213 1214 unsigned long amd_get_dr_addr_mask(unsigned int dr) 1215 { 1216 if (!cpu_feature_enabled(X86_FEATURE_BPEXT)) 1217 return 0; 1218 1219 if (WARN_ON_ONCE(dr >= ARRAY_SIZE(amd_msr_dr_addr_masks))) 1220 return 0; 1221 1222 return per_cpu(amd_dr_addr_mask[dr], smp_processor_id()); 1223 } 1224 EXPORT_SYMBOL_GPL(amd_get_dr_addr_mask); 1225 1226 static void zenbleed_check_cpu(void *unused) 1227 { 1228 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 1229 1230 zen2_zenbleed_check(c); 1231 } 1232 1233 void amd_check_microcode(void) 1234 { 1235 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) 1236 return; 1237 1238 if (cpu_feature_enabled(X86_FEATURE_ZEN2)) 1239 on_each_cpu(zenbleed_check_cpu, NULL, 1); 1240 } 1241