1 // SPDX-License-Identifier: GPL-2.0-only 2 #include <linux/export.h> 3 #include <linux/bitops.h> 4 #include <linux/elf.h> 5 #include <linux/mm.h> 6 7 #include <linux/io.h> 8 #include <linux/sched.h> 9 #include <linux/sched/clock.h> 10 #include <linux/random.h> 11 #include <linux/topology.h> 12 #include <asm/processor.h> 13 #include <asm/apic.h> 14 #include <asm/cacheinfo.h> 15 #include <asm/cpu.h> 16 #include <asm/spec-ctrl.h> 17 #include <asm/smp.h> 18 #include <asm/pci-direct.h> 19 #include <asm/delay.h> 20 #include <asm/debugreg.h> 21 22 #ifdef CONFIG_X86_64 23 # include <asm/mmconfig.h> 24 # include <asm/set_memory.h> 25 #endif 26 27 #include "cpu.h" 28 29 static const int amd_erratum_383[]; 30 static const int amd_erratum_400[]; 31 static const int amd_erratum_1054[]; 32 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); 33 34 /* 35 * nodes_per_socket: Stores the number of nodes per socket. 36 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX 37 * Node Identifiers[10:8] 38 */ 39 static u32 nodes_per_socket = 1; 40 41 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) 42 { 43 u32 gprs[8] = { 0 }; 44 int err; 45 46 WARN_ONCE((boot_cpu_data.x86 != 0xf), 47 "%s should only be used on K8!\n", __func__); 48 49 gprs[1] = msr; 50 gprs[7] = 0x9c5a203a; 51 52 err = rdmsr_safe_regs(gprs); 53 54 *p = gprs[0] | ((u64)gprs[2] << 32); 55 56 return err; 57 } 58 59 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) 60 { 61 u32 gprs[8] = { 0 }; 62 63 WARN_ONCE((boot_cpu_data.x86 != 0xf), 64 "%s should only be used on K8!\n", __func__); 65 66 gprs[0] = (u32)val; 67 gprs[1] = msr; 68 gprs[2] = val >> 32; 69 gprs[7] = 0x9c5a203a; 70 71 return wrmsr_safe_regs(gprs); 72 } 73 74 /* 75 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 76 * misexecution of code under Linux. Owners of such processors should 77 * contact AMD for precise details and a CPU swap. 78 * 79 * See http://www.multimania.com/poulot/k6bug.html 80 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" 81 * (Publication # 21266 Issue Date: August 1998) 82 * 83 * The following test is erm.. interesting. AMD neglected to up 84 * the chip setting when fixing the bug but they also tweaked some 85 * performance at the same time.. 86 */ 87 88 #ifdef CONFIG_X86_32 89 extern __visible void vide(void); 90 __asm__(".text\n" 91 ".globl vide\n" 92 ".type vide, @function\n" 93 ".align 4\n" 94 "vide: ret\n"); 95 #endif 96 97 static void init_amd_k5(struct cpuinfo_x86 *c) 98 { 99 #ifdef CONFIG_X86_32 100 /* 101 * General Systems BIOSen alias the cpu frequency registers 102 * of the Elan at 0x000df000. Unfortunately, one of the Linux 103 * drivers subsequently pokes it, and changes the CPU speed. 104 * Workaround : Remove the unneeded alias. 105 */ 106 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 107 #define CBAR_ENB (0x80000000) 108 #define CBAR_KEY (0X000000CB) 109 if (c->x86_model == 9 || c->x86_model == 10) { 110 if (inl(CBAR) & CBAR_ENB) 111 outl(0 | CBAR_KEY, CBAR); 112 } 113 #endif 114 } 115 116 static void init_amd_k6(struct cpuinfo_x86 *c) 117 { 118 #ifdef CONFIG_X86_32 119 u32 l, h; 120 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); 121 122 if (c->x86_model < 6) { 123 /* Based on AMD doc 20734R - June 2000 */ 124 if (c->x86_model == 0) { 125 clear_cpu_cap(c, X86_FEATURE_APIC); 126 set_cpu_cap(c, X86_FEATURE_PGE); 127 } 128 return; 129 } 130 131 if (c->x86_model == 6 && c->x86_stepping == 1) { 132 const int K6_BUG_LOOP = 1000000; 133 int n; 134 void (*f_vide)(void); 135 u64 d, d2; 136 137 pr_info("AMD K6 stepping B detected - "); 138 139 /* 140 * It looks like AMD fixed the 2.6.2 bug and improved indirect 141 * calls at the same time. 142 */ 143 144 n = K6_BUG_LOOP; 145 f_vide = vide; 146 OPTIMIZER_HIDE_VAR(f_vide); 147 d = rdtsc(); 148 while (n--) 149 f_vide(); 150 d2 = rdtsc(); 151 d = d2-d; 152 153 if (d > 20*K6_BUG_LOOP) 154 pr_cont("system stability may be impaired when more than 32 MB are used.\n"); 155 else 156 pr_cont("probably OK (after B9730xxxx).\n"); 157 } 158 159 /* K6 with old style WHCR */ 160 if (c->x86_model < 8 || 161 (c->x86_model == 8 && c->x86_stepping < 8)) { 162 /* We can only write allocate on the low 508Mb */ 163 if (mbytes > 508) 164 mbytes = 508; 165 166 rdmsr(MSR_K6_WHCR, l, h); 167 if ((l&0x0000FFFF) == 0) { 168 unsigned long flags; 169 l = (1<<0)|((mbytes/4)<<1); 170 local_irq_save(flags); 171 wbinvd(); 172 wrmsr(MSR_K6_WHCR, l, h); 173 local_irq_restore(flags); 174 pr_info("Enabling old style K6 write allocation for %d Mb\n", 175 mbytes); 176 } 177 return; 178 } 179 180 if ((c->x86_model == 8 && c->x86_stepping > 7) || 181 c->x86_model == 9 || c->x86_model == 13) { 182 /* The more serious chips .. */ 183 184 if (mbytes > 4092) 185 mbytes = 4092; 186 187 rdmsr(MSR_K6_WHCR, l, h); 188 if ((l&0xFFFF0000) == 0) { 189 unsigned long flags; 190 l = ((mbytes>>2)<<22)|(1<<16); 191 local_irq_save(flags); 192 wbinvd(); 193 wrmsr(MSR_K6_WHCR, l, h); 194 local_irq_restore(flags); 195 pr_info("Enabling new style K6 write allocation for %d Mb\n", 196 mbytes); 197 } 198 199 return; 200 } 201 202 if (c->x86_model == 10) { 203 /* AMD Geode LX is model 10 */ 204 /* placeholder for any needed mods */ 205 return; 206 } 207 #endif 208 } 209 210 static void init_amd_k7(struct cpuinfo_x86 *c) 211 { 212 #ifdef CONFIG_X86_32 213 u32 l, h; 214 215 /* 216 * Bit 15 of Athlon specific MSR 15, needs to be 0 217 * to enable SSE on Palomino/Morgan/Barton CPU's. 218 * If the BIOS didn't enable it already, enable it here. 219 */ 220 if (c->x86_model >= 6 && c->x86_model <= 10) { 221 if (!cpu_has(c, X86_FEATURE_XMM)) { 222 pr_info("Enabling disabled K7/SSE Support.\n"); 223 msr_clear_bit(MSR_K7_HWCR, 15); 224 set_cpu_cap(c, X86_FEATURE_XMM); 225 } 226 } 227 228 /* 229 * It's been determined by AMD that Athlons since model 8 stepping 1 230 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 231 * As per AMD technical note 27212 0.2 232 */ 233 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) { 234 rdmsr(MSR_K7_CLK_CTL, l, h); 235 if ((l & 0xfff00000) != 0x20000000) { 236 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", 237 l, ((l & 0x000fffff)|0x20000000)); 238 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 239 } 240 } 241 242 /* calling is from identify_secondary_cpu() ? */ 243 if (!c->cpu_index) 244 return; 245 246 /* 247 * Certain Athlons might work (for various values of 'work') in SMP 248 * but they are not certified as MP capable. 249 */ 250 /* Athlon 660/661 is valid. */ 251 if ((c->x86_model == 6) && ((c->x86_stepping == 0) || 252 (c->x86_stepping == 1))) 253 return; 254 255 /* Duron 670 is valid */ 256 if ((c->x86_model == 7) && (c->x86_stepping == 0)) 257 return; 258 259 /* 260 * Athlon 662, Duron 671, and Athlon >model 7 have capability 261 * bit. It's worth noting that the A5 stepping (662) of some 262 * Athlon XP's have the MP bit set. 263 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for 264 * more. 265 */ 266 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) || 267 ((c->x86_model == 7) && (c->x86_stepping >= 1)) || 268 (c->x86_model > 7)) 269 if (cpu_has(c, X86_FEATURE_MP)) 270 return; 271 272 /* If we get here, not a certified SMP capable AMD system. */ 273 274 /* 275 * Don't taint if we are running SMP kernel on a single non-MP 276 * approved Athlon 277 */ 278 WARN_ONCE(1, "WARNING: This combination of AMD" 279 " processors is not suitable for SMP.\n"); 280 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 281 #endif 282 } 283 284 #ifdef CONFIG_NUMA 285 /* 286 * To workaround broken NUMA config. Read the comment in 287 * srat_detect_node(). 288 */ 289 static int nearby_node(int apicid) 290 { 291 int i, node; 292 293 for (i = apicid - 1; i >= 0; i--) { 294 node = __apicid_to_node[i]; 295 if (node != NUMA_NO_NODE && node_online(node)) 296 return node; 297 } 298 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 299 node = __apicid_to_node[i]; 300 if (node != NUMA_NO_NODE && node_online(node)) 301 return node; 302 } 303 return first_node(node_online_map); /* Shouldn't happen */ 304 } 305 #endif 306 307 /* 308 * Fix up cpu_core_id for pre-F17h systems to be in the 309 * [0 .. cores_per_node - 1] range. Not really needed but 310 * kept so as not to break existing setups. 311 */ 312 static void legacy_fixup_core_id(struct cpuinfo_x86 *c) 313 { 314 u32 cus_per_node; 315 316 if (c->x86 >= 0x17) 317 return; 318 319 cus_per_node = c->x86_max_cores / nodes_per_socket; 320 c->cpu_core_id %= cus_per_node; 321 } 322 323 /* 324 * Fixup core topology information for 325 * (1) AMD multi-node processors 326 * Assumption: Number of cores in each internal node is the same. 327 * (2) AMD processors supporting compute units 328 */ 329 static void amd_get_topology(struct cpuinfo_x86 *c) 330 { 331 u8 node_id; 332 int cpu = smp_processor_id(); 333 334 /* get information required for multi-node processors */ 335 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 336 int err; 337 u32 eax, ebx, ecx, edx; 338 339 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); 340 341 node_id = ecx & 0xff; 342 343 if (c->x86 == 0x15) 344 c->cu_id = ebx & 0xff; 345 346 if (c->x86 >= 0x17) { 347 c->cpu_core_id = ebx & 0xff; 348 349 if (smp_num_siblings > 1) 350 c->x86_max_cores /= smp_num_siblings; 351 } 352 353 /* 354 * In case leaf B is available, use it to derive 355 * topology information. 356 */ 357 err = detect_extended_topology(c); 358 if (!err) 359 c->x86_coreid_bits = get_count_order(c->x86_max_cores); 360 361 cacheinfo_amd_init_llc_id(c, cpu, node_id); 362 363 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { 364 u64 value; 365 366 rdmsrl(MSR_FAM10H_NODE_ID, value); 367 node_id = value & 7; 368 369 per_cpu(cpu_llc_id, cpu) = node_id; 370 } else 371 return; 372 373 if (nodes_per_socket > 1) { 374 set_cpu_cap(c, X86_FEATURE_AMD_DCM); 375 legacy_fixup_core_id(c); 376 } 377 } 378 379 /* 380 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores. 381 * Assumes number of cores is a power of two. 382 */ 383 static void amd_detect_cmp(struct cpuinfo_x86 *c) 384 { 385 unsigned bits; 386 int cpu = smp_processor_id(); 387 388 bits = c->x86_coreid_bits; 389 /* Low order bits define the core id (index of core in socket) */ 390 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); 391 /* Convert the initial APIC ID into the socket ID */ 392 c->phys_proc_id = c->initial_apicid >> bits; 393 /* use socket ID also for last level cache */ 394 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; 395 } 396 397 static void amd_detect_ppin(struct cpuinfo_x86 *c) 398 { 399 unsigned long long val; 400 401 if (!cpu_has(c, X86_FEATURE_AMD_PPIN)) 402 return; 403 404 /* When PPIN is defined in CPUID, still need to check PPIN_CTL MSR */ 405 if (rdmsrl_safe(MSR_AMD_PPIN_CTL, &val)) 406 goto clear_ppin; 407 408 /* PPIN is locked in disabled mode, clear feature bit */ 409 if ((val & 3UL) == 1UL) 410 goto clear_ppin; 411 412 /* If PPIN is disabled, try to enable it */ 413 if (!(val & 2UL)) { 414 wrmsrl_safe(MSR_AMD_PPIN_CTL, val | 2UL); 415 rdmsrl_safe(MSR_AMD_PPIN_CTL, &val); 416 } 417 418 /* If PPIN_EN bit is 1, return from here; otherwise fall through */ 419 if (val & 2UL) 420 return; 421 422 clear_ppin: 423 clear_cpu_cap(c, X86_FEATURE_AMD_PPIN); 424 } 425 426 u16 amd_get_nb_id(int cpu) 427 { 428 return per_cpu(cpu_llc_id, cpu); 429 } 430 EXPORT_SYMBOL_GPL(amd_get_nb_id); 431 432 u32 amd_get_nodes_per_socket(void) 433 { 434 return nodes_per_socket; 435 } 436 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket); 437 438 static void srat_detect_node(struct cpuinfo_x86 *c) 439 { 440 #ifdef CONFIG_NUMA 441 int cpu = smp_processor_id(); 442 int node; 443 unsigned apicid = c->apicid; 444 445 node = numa_cpu_node(cpu); 446 if (node == NUMA_NO_NODE) 447 node = per_cpu(cpu_llc_id, cpu); 448 449 /* 450 * On multi-fabric platform (e.g. Numascale NumaChip) a 451 * platform-specific handler needs to be called to fixup some 452 * IDs of the CPU. 453 */ 454 if (x86_cpuinit.fixup_cpu_id) 455 x86_cpuinit.fixup_cpu_id(c, node); 456 457 if (!node_online(node)) { 458 /* 459 * Two possibilities here: 460 * 461 * - The CPU is missing memory and no node was created. In 462 * that case try picking one from a nearby CPU. 463 * 464 * - The APIC IDs differ from the HyperTransport node IDs 465 * which the K8 northbridge parsing fills in. Assume 466 * they are all increased by a constant offset, but in 467 * the same order as the HT nodeids. If that doesn't 468 * result in a usable node fall back to the path for the 469 * previous case. 470 * 471 * This workaround operates directly on the mapping between 472 * APIC ID and NUMA node, assuming certain relationship 473 * between APIC ID, HT node ID and NUMA topology. As going 474 * through CPU mapping may alter the outcome, directly 475 * access __apicid_to_node[]. 476 */ 477 int ht_nodeid = c->initial_apicid; 478 479 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 480 node = __apicid_to_node[ht_nodeid]; 481 /* Pick a nearby node */ 482 if (!node_online(node)) 483 node = nearby_node(apicid); 484 } 485 numa_set_node(cpu, node); 486 #endif 487 } 488 489 static void early_init_amd_mc(struct cpuinfo_x86 *c) 490 { 491 #ifdef CONFIG_SMP 492 unsigned bits, ecx; 493 494 /* Multi core CPU? */ 495 if (c->extended_cpuid_level < 0x80000008) 496 return; 497 498 ecx = cpuid_ecx(0x80000008); 499 500 c->x86_max_cores = (ecx & 0xff) + 1; 501 502 /* CPU telling us the core id bits shift? */ 503 bits = (ecx >> 12) & 0xF; 504 505 /* Otherwise recompute */ 506 if (bits == 0) { 507 while ((1 << bits) < c->x86_max_cores) 508 bits++; 509 } 510 511 c->x86_coreid_bits = bits; 512 #endif 513 } 514 515 static void bsp_init_amd(struct cpuinfo_x86 *c) 516 { 517 518 #ifdef CONFIG_X86_64 519 if (c->x86 >= 0xf) { 520 unsigned long long tseg; 521 522 /* 523 * Split up direct mapping around the TSEG SMM area. 524 * Don't do it for gbpages because there seems very little 525 * benefit in doing so. 526 */ 527 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { 528 unsigned long pfn = tseg >> PAGE_SHIFT; 529 530 pr_debug("tseg: %010llx\n", tseg); 531 if (pfn_range_is_mapped(pfn, pfn + 1)) 532 set_memory_4k((unsigned long)__va(tseg), 1); 533 } 534 } 535 #endif 536 537 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 538 539 if (c->x86 > 0x10 || 540 (c->x86 == 0x10 && c->x86_model >= 0x2)) { 541 u64 val; 542 543 rdmsrl(MSR_K7_HWCR, val); 544 if (!(val & BIT(24))) 545 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); 546 } 547 } 548 549 if (c->x86 == 0x15) { 550 unsigned long upperbit; 551 u32 cpuid, assoc; 552 553 cpuid = cpuid_edx(0x80000005); 554 assoc = cpuid >> 16 & 0xff; 555 upperbit = ((cpuid >> 24) << 10) / assoc; 556 557 va_align.mask = (upperbit - 1) & PAGE_MASK; 558 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; 559 560 /* A random value per boot for bit slice [12:upper_bit) */ 561 va_align.bits = get_random_int() & va_align.mask; 562 } 563 564 if (cpu_has(c, X86_FEATURE_MWAITX)) 565 use_mwaitx_delay(); 566 567 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 568 u32 ecx; 569 570 ecx = cpuid_ecx(0x8000001e); 571 nodes_per_socket = ((ecx >> 8) & 7) + 1; 572 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) { 573 u64 value; 574 575 rdmsrl(MSR_FAM10H_NODE_ID, value); 576 nodes_per_socket = ((value >> 3) & 7) + 1; 577 } 578 579 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) && 580 !boot_cpu_has(X86_FEATURE_VIRT_SSBD) && 581 c->x86 >= 0x15 && c->x86 <= 0x17) { 582 unsigned int bit; 583 584 switch (c->x86) { 585 case 0x15: bit = 54; break; 586 case 0x16: bit = 33; break; 587 case 0x17: bit = 10; break; 588 default: return; 589 } 590 /* 591 * Try to cache the base value so further operations can 592 * avoid RMW. If that faults, do not enable SSBD. 593 */ 594 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) { 595 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD); 596 setup_force_cpu_cap(X86_FEATURE_SSBD); 597 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit; 598 } 599 } 600 } 601 602 static void early_detect_mem_encrypt(struct cpuinfo_x86 *c) 603 { 604 u64 msr; 605 606 /* 607 * BIOS support is required for SME and SEV. 608 * For SME: If BIOS has enabled SME then adjust x86_phys_bits by 609 * the SME physical address space reduction value. 610 * If BIOS has not enabled SME then don't advertise the 611 * SME feature (set in scattered.c). 612 * For SEV: If BIOS has not enabled SEV then don't advertise the 613 * SEV feature (set in scattered.c). 614 * 615 * In all cases, since support for SME and SEV requires long mode, 616 * don't advertise the feature under CONFIG_X86_32. 617 */ 618 if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) { 619 /* Check if memory encryption is enabled */ 620 rdmsrl(MSR_K8_SYSCFG, msr); 621 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT)) 622 goto clear_all; 623 624 /* 625 * Always adjust physical address bits. Even though this 626 * will be a value above 32-bits this is still done for 627 * CONFIG_X86_32 so that accurate values are reported. 628 */ 629 c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f; 630 631 if (IS_ENABLED(CONFIG_X86_32)) 632 goto clear_all; 633 634 rdmsrl(MSR_K7_HWCR, msr); 635 if (!(msr & MSR_K7_HWCR_SMMLOCK)) 636 goto clear_sev; 637 638 return; 639 640 clear_all: 641 setup_clear_cpu_cap(X86_FEATURE_SME); 642 clear_sev: 643 setup_clear_cpu_cap(X86_FEATURE_SEV); 644 } 645 } 646 647 static void early_init_amd(struct cpuinfo_x86 *c) 648 { 649 u64 value; 650 u32 dummy; 651 652 early_init_amd_mc(c); 653 654 #ifdef CONFIG_X86_32 655 if (c->x86 == 6) 656 set_cpu_cap(c, X86_FEATURE_K7); 657 #endif 658 659 if (c->x86 >= 0xf) 660 set_cpu_cap(c, X86_FEATURE_K8); 661 662 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); 663 664 /* 665 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 666 * with P/T states and does not stop in deep C-states 667 */ 668 if (c->x86_power & (1 << 8)) { 669 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 670 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 671 } 672 673 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ 674 if (c->x86_power & BIT(12)) 675 set_cpu_cap(c, X86_FEATURE_ACC_POWER); 676 677 #ifdef CONFIG_X86_64 678 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 679 #else 680 /* Set MTRR capability flag if appropriate */ 681 if (c->x86 == 5) 682 if (c->x86_model == 13 || c->x86_model == 9 || 683 (c->x86_model == 8 && c->x86_stepping >= 8)) 684 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 685 #endif 686 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 687 /* 688 * ApicID can always be treated as an 8-bit value for AMD APIC versions 689 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we 690 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families 691 * after 16h. 692 */ 693 if (boot_cpu_has(X86_FEATURE_APIC)) { 694 if (c->x86 > 0x16) 695 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 696 else if (c->x86 >= 0xf) { 697 /* check CPU config space for extended APIC ID */ 698 unsigned int val; 699 700 val = read_pci_config(0, 24, 0, 0x68); 701 if ((val >> 17 & 0x3) == 0x3) 702 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 703 } 704 } 705 #endif 706 707 /* 708 * This is only needed to tell the kernel whether to use VMCALL 709 * and VMMCALL. VMMCALL is never executed except under virt, so 710 * we can set it unconditionally. 711 */ 712 set_cpu_cap(c, X86_FEATURE_VMMCALL); 713 714 /* F16h erratum 793, CVE-2013-6885 */ 715 if (c->x86 == 0x16 && c->x86_model <= 0xf) 716 msr_set_bit(MSR_AMD64_LS_CFG, 15); 717 718 /* 719 * Check whether the machine is affected by erratum 400. This is 720 * used to select the proper idle routine and to enable the check 721 * whether the machine is affected in arch_post_acpi_init(), which 722 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check. 723 */ 724 if (cpu_has_amd_erratum(c, amd_erratum_400)) 725 set_cpu_bug(c, X86_BUG_AMD_E400); 726 727 early_detect_mem_encrypt(c); 728 729 /* Re-enable TopologyExtensions if switched off by BIOS */ 730 if (c->x86 == 0x15 && 731 (c->x86_model >= 0x10 && c->x86_model <= 0x6f) && 732 !cpu_has(c, X86_FEATURE_TOPOEXT)) { 733 734 if (msr_set_bit(0xc0011005, 54) > 0) { 735 rdmsrl(0xc0011005, value); 736 if (value & BIT_64(54)) { 737 set_cpu_cap(c, X86_FEATURE_TOPOEXT); 738 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n"); 739 } 740 } 741 } 742 743 if (cpu_has(c, X86_FEATURE_TOPOEXT)) 744 smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1; 745 } 746 747 static void init_amd_k8(struct cpuinfo_x86 *c) 748 { 749 u32 level; 750 u64 value; 751 752 /* On C+ stepping K8 rep microcode works well for copy/memset */ 753 level = cpuid_eax(1); 754 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) 755 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 756 757 /* 758 * Some BIOSes incorrectly force this feature, but only K8 revision D 759 * (model = 0x14) and later actually support it. 760 * (AMD Erratum #110, docId: 25759). 761 */ 762 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { 763 clear_cpu_cap(c, X86_FEATURE_LAHF_LM); 764 if (!rdmsrl_amd_safe(0xc001100d, &value)) { 765 value &= ~BIT_64(32); 766 wrmsrl_amd_safe(0xc001100d, value); 767 } 768 } 769 770 if (!c->x86_model_id[0]) 771 strcpy(c->x86_model_id, "Hammer"); 772 773 #ifdef CONFIG_SMP 774 /* 775 * Disable TLB flush filter by setting HWCR.FFDIS on K8 776 * bit 6 of msr C001_0015 777 * 778 * Errata 63 for SH-B3 steppings 779 * Errata 122 for all steppings (F+ have it disabled by default) 780 */ 781 msr_set_bit(MSR_K7_HWCR, 6); 782 #endif 783 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE); 784 } 785 786 static void init_amd_gh(struct cpuinfo_x86 *c) 787 { 788 #ifdef CONFIG_MMCONF_FAM10H 789 /* do this for boot cpu */ 790 if (c == &boot_cpu_data) 791 check_enable_amd_mmconf_dmi(); 792 793 fam10h_check_enable_mmcfg(); 794 #endif 795 796 /* 797 * Disable GART TLB Walk Errors on Fam10h. We do this here because this 798 * is always needed when GART is enabled, even in a kernel which has no 799 * MCE support built in. BIOS should disable GartTlbWlk Errors already. 800 * If it doesn't, we do it here as suggested by the BKDG. 801 * 802 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 803 */ 804 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10); 805 806 /* 807 * On family 10h BIOS may not have properly enabled WC+ support, causing 808 * it to be converted to CD memtype. This may result in performance 809 * degradation for certain nested-paging guests. Prevent this conversion 810 * by clearing bit 24 in MSR_AMD64_BU_CFG2. 811 * 812 * NOTE: we want to use the _safe accessors so as not to #GP kvm 813 * guests on older kvm hosts. 814 */ 815 msr_clear_bit(MSR_AMD64_BU_CFG2, 24); 816 817 if (cpu_has_amd_erratum(c, amd_erratum_383)) 818 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH); 819 } 820 821 #define MSR_AMD64_DE_CFG 0xC0011029 822 823 static void init_amd_ln(struct cpuinfo_x86 *c) 824 { 825 /* 826 * Apply erratum 665 fix unconditionally so machines without a BIOS 827 * fix work. 828 */ 829 msr_set_bit(MSR_AMD64_DE_CFG, 31); 830 } 831 832 static bool rdrand_force; 833 834 static int __init rdrand_cmdline(char *str) 835 { 836 if (!str) 837 return -EINVAL; 838 839 if (!strcmp(str, "force")) 840 rdrand_force = true; 841 else 842 return -EINVAL; 843 844 return 0; 845 } 846 early_param("rdrand", rdrand_cmdline); 847 848 static void clear_rdrand_cpuid_bit(struct cpuinfo_x86 *c) 849 { 850 /* 851 * Saving of the MSR used to hide the RDRAND support during 852 * suspend/resume is done by arch/x86/power/cpu.c, which is 853 * dependent on CONFIG_PM_SLEEP. 854 */ 855 if (!IS_ENABLED(CONFIG_PM_SLEEP)) 856 return; 857 858 /* 859 * The nordrand option can clear X86_FEATURE_RDRAND, so check for 860 * RDRAND support using the CPUID function directly. 861 */ 862 if (!(cpuid_ecx(1) & BIT(30)) || rdrand_force) 863 return; 864 865 msr_clear_bit(MSR_AMD64_CPUID_FN_1, 62); 866 867 /* 868 * Verify that the CPUID change has occurred in case the kernel is 869 * running virtualized and the hypervisor doesn't support the MSR. 870 */ 871 if (cpuid_ecx(1) & BIT(30)) { 872 pr_info_once("BIOS may not properly restore RDRAND after suspend, but hypervisor does not support hiding RDRAND via CPUID.\n"); 873 return; 874 } 875 876 clear_cpu_cap(c, X86_FEATURE_RDRAND); 877 pr_info_once("BIOS may not properly restore RDRAND after suspend, hiding RDRAND via CPUID. Use rdrand=force to reenable.\n"); 878 } 879 880 static void init_amd_jg(struct cpuinfo_x86 *c) 881 { 882 /* 883 * Some BIOS implementations do not restore proper RDRAND support 884 * across suspend and resume. Check on whether to hide the RDRAND 885 * instruction support via CPUID. 886 */ 887 clear_rdrand_cpuid_bit(c); 888 } 889 890 static void init_amd_bd(struct cpuinfo_x86 *c) 891 { 892 u64 value; 893 894 /* 895 * The way access filter has a performance penalty on some workloads. 896 * Disable it on the affected CPUs. 897 */ 898 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) { 899 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) { 900 value |= 0x1E; 901 wrmsrl_safe(MSR_F15H_IC_CFG, value); 902 } 903 } 904 905 /* 906 * Some BIOS implementations do not restore proper RDRAND support 907 * across suspend and resume. Check on whether to hide the RDRAND 908 * instruction support via CPUID. 909 */ 910 clear_rdrand_cpuid_bit(c); 911 } 912 913 static void init_amd_zn(struct cpuinfo_x86 *c) 914 { 915 set_cpu_cap(c, X86_FEATURE_ZEN); 916 917 #ifdef CONFIG_NUMA 918 node_reclaim_distance = 32; 919 #endif 920 921 /* 922 * Fix erratum 1076: CPB feature bit not being set in CPUID. 923 * Always set it, except when running under a hypervisor. 924 */ 925 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && !cpu_has(c, X86_FEATURE_CPB)) 926 set_cpu_cap(c, X86_FEATURE_CPB); 927 } 928 929 static void init_amd(struct cpuinfo_x86 *c) 930 { 931 early_init_amd(c); 932 933 /* 934 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 935 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 936 */ 937 clear_cpu_cap(c, 0*32+31); 938 939 if (c->x86 >= 0x10) 940 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 941 942 /* get apicid instead of initial apic id from cpuid */ 943 c->apicid = hard_smp_processor_id(); 944 945 /* K6s reports MCEs but don't actually have all the MSRs */ 946 if (c->x86 < 6) 947 clear_cpu_cap(c, X86_FEATURE_MCE); 948 949 switch (c->x86) { 950 case 4: init_amd_k5(c); break; 951 case 5: init_amd_k6(c); break; 952 case 6: init_amd_k7(c); break; 953 case 0xf: init_amd_k8(c); break; 954 case 0x10: init_amd_gh(c); break; 955 case 0x12: init_amd_ln(c); break; 956 case 0x15: init_amd_bd(c); break; 957 case 0x16: init_amd_jg(c); break; 958 case 0x17: fallthrough; 959 case 0x19: init_amd_zn(c); break; 960 } 961 962 /* 963 * Enable workaround for FXSAVE leak on CPUs 964 * without a XSaveErPtr feature 965 */ 966 if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR))) 967 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK); 968 969 cpu_detect_cache_sizes(c); 970 971 amd_detect_cmp(c); 972 amd_get_topology(c); 973 srat_detect_node(c); 974 amd_detect_ppin(c); 975 976 init_amd_cacheinfo(c); 977 978 if (cpu_has(c, X86_FEATURE_XMM2)) { 979 /* 980 * Use LFENCE for execution serialization. On families which 981 * don't have that MSR, LFENCE is already serializing. 982 * msr_set_bit() uses the safe accessors, too, even if the MSR 983 * is not present. 984 */ 985 msr_set_bit(MSR_F10H_DECFG, 986 MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT); 987 988 /* A serializing LFENCE stops RDTSC speculation */ 989 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 990 } 991 992 /* 993 * Family 0x12 and above processors have APIC timer 994 * running in deep C states. 995 */ 996 if (c->x86 > 0x11) 997 set_cpu_cap(c, X86_FEATURE_ARAT); 998 999 /* 3DNow or LM implies PREFETCHW */ 1000 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH)) 1001 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM)) 1002 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH); 1003 1004 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */ 1005 if (!cpu_has(c, X86_FEATURE_XENPV)) 1006 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); 1007 1008 /* 1009 * Turn on the Instructions Retired free counter on machines not 1010 * susceptible to erratum #1054 "Instructions Retired Performance 1011 * Counter May Be Inaccurate". 1012 */ 1013 if (cpu_has(c, X86_FEATURE_IRPERF) && 1014 !cpu_has_amd_erratum(c, amd_erratum_1054)) 1015 msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT); 1016 } 1017 1018 #ifdef CONFIG_X86_32 1019 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) 1020 { 1021 /* AMD errata T13 (order #21922) */ 1022 if (c->x86 == 6) { 1023 /* Duron Rev A0 */ 1024 if (c->x86_model == 3 && c->x86_stepping == 0) 1025 size = 64; 1026 /* Tbird rev A1/A2 */ 1027 if (c->x86_model == 4 && 1028 (c->x86_stepping == 0 || c->x86_stepping == 1)) 1029 size = 256; 1030 } 1031 return size; 1032 } 1033 #endif 1034 1035 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) 1036 { 1037 u32 ebx, eax, ecx, edx; 1038 u16 mask = 0xfff; 1039 1040 if (c->x86 < 0xf) 1041 return; 1042 1043 if (c->extended_cpuid_level < 0x80000006) 1044 return; 1045 1046 cpuid(0x80000006, &eax, &ebx, &ecx, &edx); 1047 1048 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask; 1049 tlb_lli_4k[ENTRIES] = ebx & mask; 1050 1051 /* 1052 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB 1053 * characteristics from the CPUID function 0x80000005 instead. 1054 */ 1055 if (c->x86 == 0xf) { 1056 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 1057 mask = 0xff; 1058 } 1059 1060 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 1061 if (!((eax >> 16) & mask)) 1062 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff; 1063 else 1064 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask; 1065 1066 /* a 4M entry uses two 2M entries */ 1067 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1; 1068 1069 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 1070 if (!(eax & mask)) { 1071 /* Erratum 658 */ 1072 if (c->x86 == 0x15 && c->x86_model <= 0x1f) { 1073 tlb_lli_2m[ENTRIES] = 1024; 1074 } else { 1075 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 1076 tlb_lli_2m[ENTRIES] = eax & 0xff; 1077 } 1078 } else 1079 tlb_lli_2m[ENTRIES] = eax & mask; 1080 1081 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; 1082 } 1083 1084 static const struct cpu_dev amd_cpu_dev = { 1085 .c_vendor = "AMD", 1086 .c_ident = { "AuthenticAMD" }, 1087 #ifdef CONFIG_X86_32 1088 .legacy_models = { 1089 { .family = 4, .model_names = 1090 { 1091 [3] = "486 DX/2", 1092 [7] = "486 DX/2-WB", 1093 [8] = "486 DX/4", 1094 [9] = "486 DX/4-WB", 1095 [14] = "Am5x86-WT", 1096 [15] = "Am5x86-WB" 1097 } 1098 }, 1099 }, 1100 .legacy_cache_size = amd_size_cache, 1101 #endif 1102 .c_early_init = early_init_amd, 1103 .c_detect_tlb = cpu_detect_tlb_amd, 1104 .c_bsp_init = bsp_init_amd, 1105 .c_init = init_amd, 1106 .c_x86_vendor = X86_VENDOR_AMD, 1107 }; 1108 1109 cpu_dev_register(amd_cpu_dev); 1110 1111 /* 1112 * AMD errata checking 1113 * 1114 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or 1115 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that 1116 * have an OSVW id assigned, which it takes as first argument. Both take a 1117 * variable number of family-specific model-stepping ranges created by 1118 * AMD_MODEL_RANGE(). 1119 * 1120 * Example: 1121 * 1122 * const int amd_erratum_319[] = 1123 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), 1124 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), 1125 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); 1126 */ 1127 1128 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } 1129 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } 1130 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ 1131 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) 1132 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) 1133 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) 1134 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) 1135 1136 static const int amd_erratum_400[] = 1137 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), 1138 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); 1139 1140 static const int amd_erratum_383[] = 1141 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); 1142 1143 /* #1054: Instructions Retired Performance Counter May Be Inaccurate */ 1144 static const int amd_erratum_1054[] = 1145 AMD_OSVW_ERRATUM(0, AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf)); 1146 1147 1148 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) 1149 { 1150 int osvw_id = *erratum++; 1151 u32 range; 1152 u32 ms; 1153 1154 if (osvw_id >= 0 && osvw_id < 65536 && 1155 cpu_has(cpu, X86_FEATURE_OSVW)) { 1156 u64 osvw_len; 1157 1158 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); 1159 if (osvw_id < osvw_len) { 1160 u64 osvw_bits; 1161 1162 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), 1163 osvw_bits); 1164 return osvw_bits & (1ULL << (osvw_id & 0x3f)); 1165 } 1166 } 1167 1168 /* OSVW unavailable or ID unknown, match family-model-stepping range */ 1169 ms = (cpu->x86_model << 4) | cpu->x86_stepping; 1170 while ((range = *erratum++)) 1171 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && 1172 (ms >= AMD_MODEL_RANGE_START(range)) && 1173 (ms <= AMD_MODEL_RANGE_END(range))) 1174 return true; 1175 1176 return false; 1177 } 1178 1179 void set_dr_addr_mask(unsigned long mask, int dr) 1180 { 1181 if (!boot_cpu_has(X86_FEATURE_BPEXT)) 1182 return; 1183 1184 switch (dr) { 1185 case 0: 1186 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0); 1187 break; 1188 case 1: 1189 case 2: 1190 case 3: 1191 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0); 1192 break; 1193 default: 1194 break; 1195 } 1196 } 1197