1 // SPDX-License-Identifier: GPL-2.0-only 2 #include <linux/export.h> 3 #include <linux/bitops.h> 4 #include <linux/elf.h> 5 #include <linux/mm.h> 6 7 #include <linux/io.h> 8 #include <linux/sched.h> 9 #include <linux/sched/clock.h> 10 #include <linux/random.h> 11 #include <linux/topology.h> 12 #include <asm/amd/fch.h> 13 #include <asm/processor.h> 14 #include <asm/apic.h> 15 #include <asm/cacheinfo.h> 16 #include <asm/cpu.h> 17 #include <asm/cpu_device_id.h> 18 #include <asm/spec-ctrl.h> 19 #include <asm/smp.h> 20 #include <asm/numa.h> 21 #include <asm/pci-direct.h> 22 #include <asm/delay.h> 23 #include <asm/debugreg.h> 24 #include <asm/resctrl.h> 25 #include <asm/msr.h> 26 #include <asm/sev.h> 27 28 #ifdef CONFIG_X86_64 29 # include <asm/mmconfig.h> 30 #endif 31 32 #include "cpu.h" 33 34 u16 invlpgb_count_max __ro_after_init = 1; 35 36 static inline int rdmsrq_amd_safe(unsigned msr, u64 *p) 37 { 38 u32 gprs[8] = { 0 }; 39 int err; 40 41 WARN_ONCE((boot_cpu_data.x86 != 0xf), 42 "%s should only be used on K8!\n", __func__); 43 44 gprs[1] = msr; 45 gprs[7] = 0x9c5a203a; 46 47 err = rdmsr_safe_regs(gprs); 48 49 *p = gprs[0] | ((u64)gprs[2] << 32); 50 51 return err; 52 } 53 54 static inline int wrmsrq_amd_safe(unsigned msr, u64 val) 55 { 56 u32 gprs[8] = { 0 }; 57 58 WARN_ONCE((boot_cpu_data.x86 != 0xf), 59 "%s should only be used on K8!\n", __func__); 60 61 gprs[0] = (u32)val; 62 gprs[1] = msr; 63 gprs[2] = val >> 32; 64 gprs[7] = 0x9c5a203a; 65 66 return wrmsr_safe_regs(gprs); 67 } 68 69 /* 70 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 71 * misexecution of code under Linux. Owners of such processors should 72 * contact AMD for precise details and a CPU swap. 73 * 74 * See http://www.multimania.com/poulot/k6bug.html 75 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" 76 * (Publication # 21266 Issue Date: August 1998) 77 * 78 * The following test is erm.. interesting. AMD neglected to up 79 * the chip setting when fixing the bug but they also tweaked some 80 * performance at the same time.. 81 */ 82 83 #ifdef CONFIG_X86_32 84 extern __visible void vide(void); 85 __asm__(".text\n" 86 ".globl vide\n" 87 ".type vide, @function\n" 88 ".align 4\n" 89 "vide: ret\n"); 90 #endif 91 92 static void init_amd_k5(struct cpuinfo_x86 *c) 93 { 94 #ifdef CONFIG_X86_32 95 /* 96 * General Systems BIOSen alias the cpu frequency registers 97 * of the Elan at 0x000df000. Unfortunately, one of the Linux 98 * drivers subsequently pokes it, and changes the CPU speed. 99 * Workaround : Remove the unneeded alias. 100 */ 101 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 102 #define CBAR_ENB (0x80000000) 103 #define CBAR_KEY (0X000000CB) 104 if (c->x86_model == 9 || c->x86_model == 10) { 105 if (inl(CBAR) & CBAR_ENB) 106 outl(0 | CBAR_KEY, CBAR); 107 } 108 #endif 109 } 110 111 static void init_amd_k6(struct cpuinfo_x86 *c) 112 { 113 #ifdef CONFIG_X86_32 114 u32 l, h; 115 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); 116 117 if (c->x86_model < 6) { 118 /* Based on AMD doc 20734R - June 2000 */ 119 if (c->x86_model == 0) { 120 clear_cpu_cap(c, X86_FEATURE_APIC); 121 set_cpu_cap(c, X86_FEATURE_PGE); 122 } 123 return; 124 } 125 126 if (c->x86_model == 6 && c->x86_stepping == 1) { 127 const int K6_BUG_LOOP = 1000000; 128 int n; 129 void (*f_vide)(void); 130 u64 d, d2; 131 132 pr_info("AMD K6 stepping B detected - "); 133 134 /* 135 * It looks like AMD fixed the 2.6.2 bug and improved indirect 136 * calls at the same time. 137 */ 138 139 n = K6_BUG_LOOP; 140 f_vide = vide; 141 OPTIMIZER_HIDE_VAR(f_vide); 142 d = rdtsc(); 143 while (n--) 144 f_vide(); 145 d2 = rdtsc(); 146 d = d2-d; 147 148 if (d > 20*K6_BUG_LOOP) 149 pr_cont("system stability may be impaired when more than 32 MB are used.\n"); 150 else 151 pr_cont("probably OK (after B9730xxxx).\n"); 152 } 153 154 /* K6 with old style WHCR */ 155 if (c->x86_model < 8 || 156 (c->x86_model == 8 && c->x86_stepping < 8)) { 157 /* We can only write allocate on the low 508Mb */ 158 if (mbytes > 508) 159 mbytes = 508; 160 161 rdmsr(MSR_K6_WHCR, l, h); 162 if ((l&0x0000FFFF) == 0) { 163 unsigned long flags; 164 l = (1<<0)|((mbytes/4)<<1); 165 local_irq_save(flags); 166 wbinvd(); 167 wrmsr(MSR_K6_WHCR, l, h); 168 local_irq_restore(flags); 169 pr_info("Enabling old style K6 write allocation for %d Mb\n", 170 mbytes); 171 } 172 return; 173 } 174 175 if ((c->x86_model == 8 && c->x86_stepping > 7) || 176 c->x86_model == 9 || c->x86_model == 13) { 177 /* The more serious chips .. */ 178 179 if (mbytes > 4092) 180 mbytes = 4092; 181 182 rdmsr(MSR_K6_WHCR, l, h); 183 if ((l&0xFFFF0000) == 0) { 184 unsigned long flags; 185 l = ((mbytes>>2)<<22)|(1<<16); 186 local_irq_save(flags); 187 wbinvd(); 188 wrmsr(MSR_K6_WHCR, l, h); 189 local_irq_restore(flags); 190 pr_info("Enabling new style K6 write allocation for %d Mb\n", 191 mbytes); 192 } 193 194 return; 195 } 196 197 if (c->x86_model == 10) { 198 /* AMD Geode LX is model 10 */ 199 /* placeholder for any needed mods */ 200 return; 201 } 202 #endif 203 } 204 205 static void init_amd_k7(struct cpuinfo_x86 *c) 206 { 207 #ifdef CONFIG_X86_32 208 u32 l, h; 209 210 /* 211 * Bit 15 of Athlon specific MSR 15, needs to be 0 212 * to enable SSE on Palomino/Morgan/Barton CPU's. 213 * If the BIOS didn't enable it already, enable it here. 214 */ 215 if (c->x86_model >= 6 && c->x86_model <= 10) { 216 if (!cpu_has(c, X86_FEATURE_XMM)) { 217 pr_info("Enabling disabled K7/SSE Support.\n"); 218 msr_clear_bit(MSR_K7_HWCR, 15); 219 set_cpu_cap(c, X86_FEATURE_XMM); 220 } 221 } 222 223 /* 224 * It's been determined by AMD that Athlons since model 8 stepping 1 225 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 226 * As per AMD technical note 27212 0.2 227 */ 228 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) { 229 rdmsr(MSR_K7_CLK_CTL, l, h); 230 if ((l & 0xfff00000) != 0x20000000) { 231 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", 232 l, ((l & 0x000fffff)|0x20000000)); 233 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 234 } 235 } 236 237 /* calling is from identify_secondary_cpu() ? */ 238 if (!c->cpu_index) 239 return; 240 241 /* 242 * Certain Athlons might work (for various values of 'work') in SMP 243 * but they are not certified as MP capable. 244 */ 245 /* Athlon 660/661 is valid. */ 246 if ((c->x86_model == 6) && ((c->x86_stepping == 0) || 247 (c->x86_stepping == 1))) 248 return; 249 250 /* Duron 670 is valid */ 251 if ((c->x86_model == 7) && (c->x86_stepping == 0)) 252 return; 253 254 /* 255 * Athlon 662, Duron 671, and Athlon >model 7 have capability 256 * bit. It's worth noting that the A5 stepping (662) of some 257 * Athlon XP's have the MP bit set. 258 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for 259 * more. 260 */ 261 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) || 262 ((c->x86_model == 7) && (c->x86_stepping >= 1)) || 263 (c->x86_model > 7)) 264 if (cpu_has(c, X86_FEATURE_MP)) 265 return; 266 267 /* If we get here, not a certified SMP capable AMD system. */ 268 269 /* 270 * Don't taint if we are running SMP kernel on a single non-MP 271 * approved Athlon 272 */ 273 WARN_ONCE(1, "WARNING: This combination of AMD" 274 " processors is not suitable for SMP.\n"); 275 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 276 #endif 277 } 278 279 #ifdef CONFIG_NUMA 280 /* 281 * To workaround broken NUMA config. Read the comment in 282 * srat_detect_node(). 283 */ 284 static int nearby_node(int apicid) 285 { 286 int i, node; 287 288 for (i = apicid - 1; i >= 0; i--) { 289 node = __apicid_to_node[i]; 290 if (node != NUMA_NO_NODE && node_online(node)) 291 return node; 292 } 293 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 294 node = __apicid_to_node[i]; 295 if (node != NUMA_NO_NODE && node_online(node)) 296 return node; 297 } 298 return first_node(node_online_map); /* Shouldn't happen */ 299 } 300 #endif 301 302 static void srat_detect_node(struct cpuinfo_x86 *c) 303 { 304 #ifdef CONFIG_NUMA 305 int cpu = smp_processor_id(); 306 int node; 307 unsigned apicid = c->topo.apicid; 308 309 node = numa_cpu_node(cpu); 310 if (node == NUMA_NO_NODE) 311 node = per_cpu_llc_id(cpu); 312 313 /* 314 * On multi-fabric platform (e.g. Numascale NumaChip) a 315 * platform-specific handler needs to be called to fixup some 316 * IDs of the CPU. 317 */ 318 if (x86_cpuinit.fixup_cpu_id) 319 x86_cpuinit.fixup_cpu_id(c, node); 320 321 if (!node_online(node)) { 322 /* 323 * Two possibilities here: 324 * 325 * - The CPU is missing memory and no node was created. In 326 * that case try picking one from a nearby CPU. 327 * 328 * - The APIC IDs differ from the HyperTransport node IDs 329 * which the K8 northbridge parsing fills in. Assume 330 * they are all increased by a constant offset, but in 331 * the same order as the HT nodeids. If that doesn't 332 * result in a usable node fall back to the path for the 333 * previous case. 334 * 335 * This workaround operates directly on the mapping between 336 * APIC ID and NUMA node, assuming certain relationship 337 * between APIC ID, HT node ID and NUMA topology. As going 338 * through CPU mapping may alter the outcome, directly 339 * access __apicid_to_node[]. 340 */ 341 int ht_nodeid = c->topo.initial_apicid; 342 343 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 344 node = __apicid_to_node[ht_nodeid]; 345 /* Pick a nearby node */ 346 if (!node_online(node)) 347 node = nearby_node(apicid); 348 } 349 numa_set_node(cpu, node); 350 #endif 351 } 352 353 static void bsp_determine_snp(struct cpuinfo_x86 *c) 354 { 355 #ifdef CONFIG_ARCH_HAS_CC_PLATFORM 356 cc_vendor = CC_VENDOR_AMD; 357 358 if (cpu_has(c, X86_FEATURE_SEV_SNP)) { 359 /* 360 * RMP table entry format is not architectural and is defined by the 361 * per-processor PPR. Restrict SNP support on the known CPU models 362 * for which the RMP table entry format is currently defined or for 363 * processors which support the architecturally defined RMPREAD 364 * instruction. 365 */ 366 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && 367 (cpu_feature_enabled(X86_FEATURE_ZEN3) || 368 cpu_feature_enabled(X86_FEATURE_ZEN4) || 369 cpu_feature_enabled(X86_FEATURE_RMPREAD)) && 370 snp_probe_rmptable_info()) { 371 cc_platform_set(CC_ATTR_HOST_SEV_SNP); 372 } else { 373 setup_clear_cpu_cap(X86_FEATURE_SEV_SNP); 374 cc_platform_clear(CC_ATTR_HOST_SEV_SNP); 375 } 376 } 377 #endif 378 } 379 380 static void bsp_init_amd(struct cpuinfo_x86 *c) 381 { 382 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 383 384 if (c->x86 > 0x10 || 385 (c->x86 == 0x10 && c->x86_model >= 0x2)) { 386 u64 val; 387 388 rdmsrq(MSR_K7_HWCR, val); 389 if (!(val & BIT(24))) 390 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); 391 } 392 } 393 394 if (c->x86 == 0x15) { 395 unsigned long upperbit; 396 u32 cpuid, assoc; 397 398 cpuid = cpuid_edx(0x80000005); 399 assoc = cpuid >> 16 & 0xff; 400 upperbit = ((cpuid >> 24) << 10) / assoc; 401 402 va_align.mask = (upperbit - 1) & PAGE_MASK; 403 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; 404 405 /* A random value per boot for bit slice [12:upper_bit) */ 406 va_align.bits = get_random_u32() & va_align.mask; 407 } 408 409 if (cpu_has(c, X86_FEATURE_MWAITX)) 410 use_mwaitx_delay(); 411 412 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) && 413 !boot_cpu_has(X86_FEATURE_VIRT_SSBD) && 414 c->x86 >= 0x15 && c->x86 <= 0x17) { 415 unsigned int bit; 416 417 switch (c->x86) { 418 case 0x15: bit = 54; break; 419 case 0x16: bit = 33; break; 420 case 0x17: bit = 10; break; 421 default: return; 422 } 423 /* 424 * Try to cache the base value so further operations can 425 * avoid RMW. If that faults, do not enable SSBD. 426 */ 427 if (!rdmsrq_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) { 428 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD); 429 setup_force_cpu_cap(X86_FEATURE_SSBD); 430 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit; 431 } 432 } 433 434 resctrl_cpu_detect(c); 435 436 /* Figure out Zen generations: */ 437 switch (c->x86) { 438 case 0x17: 439 switch (c->x86_model) { 440 case 0x00 ... 0x2f: 441 case 0x50 ... 0x5f: 442 setup_force_cpu_cap(X86_FEATURE_ZEN1); 443 break; 444 case 0x30 ... 0x4f: 445 case 0x60 ... 0x7f: 446 case 0x90 ... 0x91: 447 case 0xa0 ... 0xaf: 448 setup_force_cpu_cap(X86_FEATURE_ZEN2); 449 break; 450 default: 451 goto warn; 452 } 453 break; 454 455 case 0x19: 456 switch (c->x86_model) { 457 case 0x00 ... 0x0f: 458 case 0x20 ... 0x5f: 459 setup_force_cpu_cap(X86_FEATURE_ZEN3); 460 break; 461 case 0x10 ... 0x1f: 462 case 0x60 ... 0xaf: 463 setup_force_cpu_cap(X86_FEATURE_ZEN4); 464 break; 465 default: 466 goto warn; 467 } 468 break; 469 470 case 0x1a: 471 switch (c->x86_model) { 472 case 0x00 ... 0x2f: 473 case 0x40 ... 0x4f: 474 case 0x60 ... 0x7f: 475 setup_force_cpu_cap(X86_FEATURE_ZEN5); 476 break; 477 case 0x50 ... 0x5f: 478 case 0x90 ... 0xaf: 479 case 0xc0 ... 0xcf: 480 setup_force_cpu_cap(X86_FEATURE_ZEN6); 481 break; 482 default: 483 goto warn; 484 } 485 break; 486 487 default: 488 break; 489 } 490 491 bsp_determine_snp(c); 492 return; 493 494 warn: 495 WARN_ONCE(1, "Family 0x%x, model: 0x%x??\n", c->x86, c->x86_model); 496 } 497 498 static void early_detect_mem_encrypt(struct cpuinfo_x86 *c) 499 { 500 u64 msr; 501 502 /* 503 * BIOS support is required for SME and SEV. 504 * For SME: If BIOS has enabled SME then adjust x86_phys_bits by 505 * the SME physical address space reduction value. 506 * If BIOS has not enabled SME then don't advertise the 507 * SME feature (set in scattered.c). 508 * If the kernel has not enabled SME via any means then 509 * don't advertise the SME feature. 510 * For SEV: If BIOS has not enabled SEV then don't advertise SEV and 511 * any additional functionality based on it. 512 * 513 * In all cases, since support for SME and SEV requires long mode, 514 * don't advertise the feature under CONFIG_X86_32. 515 */ 516 if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) { 517 /* Check if memory encryption is enabled */ 518 rdmsrq(MSR_AMD64_SYSCFG, msr); 519 if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT)) 520 goto clear_all; 521 522 /* 523 * Always adjust physical address bits. Even though this 524 * will be a value above 32-bits this is still done for 525 * CONFIG_X86_32 so that accurate values are reported. 526 */ 527 c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f; 528 529 if (IS_ENABLED(CONFIG_X86_32)) 530 goto clear_all; 531 532 if (!sme_me_mask) 533 setup_clear_cpu_cap(X86_FEATURE_SME); 534 535 rdmsrq(MSR_K7_HWCR, msr); 536 if (!(msr & MSR_K7_HWCR_SMMLOCK)) 537 goto clear_sev; 538 539 return; 540 541 clear_all: 542 setup_clear_cpu_cap(X86_FEATURE_SME); 543 clear_sev: 544 setup_clear_cpu_cap(X86_FEATURE_SEV); 545 setup_clear_cpu_cap(X86_FEATURE_SEV_ES); 546 setup_clear_cpu_cap(X86_FEATURE_SEV_SNP); 547 } 548 } 549 550 static void early_init_amd(struct cpuinfo_x86 *c) 551 { 552 u32 dummy; 553 554 if (c->x86 >= 0xf) 555 set_cpu_cap(c, X86_FEATURE_K8); 556 557 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); 558 559 /* 560 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 561 * with P/T states and does not stop in deep C-states 562 */ 563 if (c->x86_power & (1 << 8)) { 564 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 565 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 566 } 567 568 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ 569 if (c->x86_power & BIT(12)) 570 set_cpu_cap(c, X86_FEATURE_ACC_POWER); 571 572 /* Bit 14 indicates the Runtime Average Power Limit interface. */ 573 if (c->x86_power & BIT(14)) 574 set_cpu_cap(c, X86_FEATURE_RAPL); 575 576 #ifdef CONFIG_X86_64 577 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 578 #else 579 /* Set MTRR capability flag if appropriate */ 580 if (c->x86 == 5) 581 if (c->x86_model == 13 || c->x86_model == 9 || 582 (c->x86_model == 8 && c->x86_stepping >= 8)) 583 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 584 #endif 585 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 586 /* 587 * ApicID can always be treated as an 8-bit value for AMD APIC versions 588 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we 589 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families 590 * after 16h. 591 */ 592 if (boot_cpu_has(X86_FEATURE_APIC)) { 593 if (c->x86 > 0x16) 594 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 595 else if (c->x86 >= 0xf) { 596 /* check CPU config space for extended APIC ID */ 597 unsigned int val; 598 599 val = read_pci_config(0, 24, 0, 0x68); 600 if ((val >> 17 & 0x3) == 0x3) 601 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 602 } 603 } 604 #endif 605 606 /* 607 * This is only needed to tell the kernel whether to use VMCALL 608 * and VMMCALL. VMMCALL is never executed except under virt, so 609 * we can set it unconditionally. 610 */ 611 set_cpu_cap(c, X86_FEATURE_VMMCALL); 612 613 /* F16h erratum 793, CVE-2013-6885 */ 614 if (c->x86 == 0x16 && c->x86_model <= 0xf) 615 msr_set_bit(MSR_AMD64_LS_CFG, 15); 616 617 early_detect_mem_encrypt(c); 618 619 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && !cpu_has(c, X86_FEATURE_IBPB_BRTYPE)) { 620 if (c->x86 == 0x17 && boot_cpu_has(X86_FEATURE_AMD_IBPB)) 621 setup_force_cpu_cap(X86_FEATURE_IBPB_BRTYPE); 622 else if (c->x86 >= 0x19 && !wrmsrq_safe(MSR_IA32_PRED_CMD, PRED_CMD_SBPB)) { 623 setup_force_cpu_cap(X86_FEATURE_IBPB_BRTYPE); 624 setup_force_cpu_cap(X86_FEATURE_SBPB); 625 } 626 } 627 } 628 629 static void init_amd_k8(struct cpuinfo_x86 *c) 630 { 631 u32 level; 632 u64 value; 633 634 /* On C+ stepping K8 rep microcode works well for copy/memset */ 635 level = cpuid_eax(1); 636 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) 637 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 638 639 /* 640 * Some BIOSes incorrectly force this feature, but only K8 revision D 641 * (model = 0x14) and later actually support it. 642 * (AMD Erratum #110, docId: 25759). 643 */ 644 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM) && !cpu_has(c, X86_FEATURE_HYPERVISOR)) { 645 clear_cpu_cap(c, X86_FEATURE_LAHF_LM); 646 if (!rdmsrq_amd_safe(0xc001100d, &value)) { 647 value &= ~BIT_64(32); 648 wrmsrq_amd_safe(0xc001100d, value); 649 } 650 } 651 652 if (!c->x86_model_id[0]) 653 strscpy(c->x86_model_id, "Hammer"); 654 655 #ifdef CONFIG_SMP 656 /* 657 * Disable TLB flush filter by setting HWCR.FFDIS on K8 658 * bit 6 of msr C001_0015 659 * 660 * Errata 63 for SH-B3 steppings 661 * Errata 122 for all steppings (F+ have it disabled by default) 662 */ 663 msr_set_bit(MSR_K7_HWCR, 6); 664 #endif 665 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE); 666 667 /* 668 * Check models and steppings affected by erratum 400. This is 669 * used to select the proper idle routine and to enable the 670 * check whether the machine is affected in arch_post_acpi_subsys_init() 671 * which sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check. 672 */ 673 if (c->x86_model > 0x41 || 674 (c->x86_model == 0x41 && c->x86_stepping >= 0x2)) 675 setup_force_cpu_bug(X86_BUG_AMD_E400); 676 } 677 678 static void init_amd_gh(struct cpuinfo_x86 *c) 679 { 680 #ifdef CONFIG_MMCONF_FAM10H 681 /* do this for boot cpu */ 682 if (c == &boot_cpu_data) 683 check_enable_amd_mmconf_dmi(); 684 685 fam10h_check_enable_mmcfg(); 686 #endif 687 688 /* 689 * Disable GART TLB Walk Errors on Fam10h. We do this here because this 690 * is always needed when GART is enabled, even in a kernel which has no 691 * MCE support built in. BIOS should disable GartTlbWlk Errors already. 692 * If it doesn't, we do it here as suggested by the BKDG. 693 * 694 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 695 */ 696 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10); 697 698 /* 699 * On family 10h BIOS may not have properly enabled WC+ support, causing 700 * it to be converted to CD memtype. This may result in performance 701 * degradation for certain nested-paging guests. Prevent this conversion 702 * by clearing bit 24 in MSR_AMD64_BU_CFG2. 703 * 704 * NOTE: we want to use the _safe accessors so as not to #GP kvm 705 * guests on older kvm hosts. 706 */ 707 msr_clear_bit(MSR_AMD64_BU_CFG2, 24); 708 709 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH); 710 711 /* 712 * Check models and steppings affected by erratum 400. This is 713 * used to select the proper idle routine and to enable the 714 * check whether the machine is affected in arch_post_acpi_subsys_init() 715 * which sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check. 716 */ 717 if (c->x86_model > 0x2 || 718 (c->x86_model == 0x2 && c->x86_stepping >= 0x1)) 719 setup_force_cpu_bug(X86_BUG_AMD_E400); 720 } 721 722 static void init_amd_ln(struct cpuinfo_x86 *c) 723 { 724 /* 725 * Apply erratum 665 fix unconditionally so machines without a BIOS 726 * fix work. 727 */ 728 msr_set_bit(MSR_AMD64_DE_CFG, 31); 729 } 730 731 static bool rdrand_force; 732 733 static int __init rdrand_cmdline(char *str) 734 { 735 if (!str) 736 return -EINVAL; 737 738 if (!strcmp(str, "force")) 739 rdrand_force = true; 740 else 741 return -EINVAL; 742 743 return 0; 744 } 745 early_param("rdrand", rdrand_cmdline); 746 747 static void clear_rdrand_cpuid_bit(struct cpuinfo_x86 *c) 748 { 749 /* 750 * Saving of the MSR used to hide the RDRAND support during 751 * suspend/resume is done by arch/x86/power/cpu.c, which is 752 * dependent on CONFIG_PM_SLEEP. 753 */ 754 if (!IS_ENABLED(CONFIG_PM_SLEEP)) 755 return; 756 757 /* 758 * The self-test can clear X86_FEATURE_RDRAND, so check for 759 * RDRAND support using the CPUID function directly. 760 */ 761 if (!(cpuid_ecx(1) & BIT(30)) || rdrand_force) 762 return; 763 764 msr_clear_bit(MSR_AMD64_CPUID_FN_1, 62); 765 766 /* 767 * Verify that the CPUID change has occurred in case the kernel is 768 * running virtualized and the hypervisor doesn't support the MSR. 769 */ 770 if (cpuid_ecx(1) & BIT(30)) { 771 pr_info_once("BIOS may not properly restore RDRAND after suspend, but hypervisor does not support hiding RDRAND via CPUID.\n"); 772 return; 773 } 774 775 clear_cpu_cap(c, X86_FEATURE_RDRAND); 776 pr_info_once("BIOS may not properly restore RDRAND after suspend, hiding RDRAND via CPUID. Use rdrand=force to reenable.\n"); 777 } 778 779 static void init_amd_jg(struct cpuinfo_x86 *c) 780 { 781 /* 782 * Some BIOS implementations do not restore proper RDRAND support 783 * across suspend and resume. Check on whether to hide the RDRAND 784 * instruction support via CPUID. 785 */ 786 clear_rdrand_cpuid_bit(c); 787 } 788 789 static void init_amd_bd(struct cpuinfo_x86 *c) 790 { 791 u64 value; 792 793 /* 794 * The way access filter has a performance penalty on some workloads. 795 * Disable it on the affected CPUs. 796 */ 797 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) { 798 if (!rdmsrq_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) { 799 value |= 0x1E; 800 wrmsrq_safe(MSR_F15H_IC_CFG, value); 801 } 802 } 803 804 /* 805 * Some BIOS implementations do not restore proper RDRAND support 806 * across suspend and resume. Check on whether to hide the RDRAND 807 * instruction support via CPUID. 808 */ 809 clear_rdrand_cpuid_bit(c); 810 } 811 812 static const struct x86_cpu_id erratum_1386_microcode[] = { 813 X86_MATCH_VFM_STEPS(VFM_MAKE(X86_VENDOR_AMD, 0x17, 0x01), 0x2, 0x2, 0x0800126e), 814 X86_MATCH_VFM_STEPS(VFM_MAKE(X86_VENDOR_AMD, 0x17, 0x31), 0x0, 0x0, 0x08301052), 815 {} 816 }; 817 818 static void fix_erratum_1386(struct cpuinfo_x86 *c) 819 { 820 /* 821 * Work around Erratum 1386. The XSAVES instruction malfunctions in 822 * certain circumstances on Zen1/2 uarch, and not all parts have had 823 * updated microcode at the time of writing (March 2023). 824 * 825 * Affected parts all have no supervisor XSAVE states, meaning that 826 * the XSAVEC instruction (which works fine) is equivalent. 827 * 828 * Clear the feature flag only on microcode revisions which 829 * don't have the fix. 830 */ 831 if (x86_match_min_microcode_rev(erratum_1386_microcode)) 832 return; 833 834 clear_cpu_cap(c, X86_FEATURE_XSAVES); 835 } 836 837 void init_spectral_chicken(struct cpuinfo_x86 *c) 838 { 839 #ifdef CONFIG_MITIGATION_UNRET_ENTRY 840 u64 value; 841 842 /* 843 * On Zen2 we offer this chicken (bit) on the altar of Speculation. 844 * 845 * This suppresses speculation from the middle of a basic block, i.e. it 846 * suppresses non-branch predictions. 847 */ 848 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) { 849 if (!rdmsrq_safe(MSR_ZEN2_SPECTRAL_CHICKEN, &value)) { 850 value |= MSR_ZEN2_SPECTRAL_CHICKEN_BIT; 851 wrmsrq_safe(MSR_ZEN2_SPECTRAL_CHICKEN, value); 852 } 853 } 854 #endif 855 } 856 857 static void init_amd_zen_common(void) 858 { 859 setup_force_cpu_cap(X86_FEATURE_ZEN); 860 #ifdef CONFIG_NUMA 861 node_reclaim_distance = 32; 862 #endif 863 } 864 865 static void init_amd_zen1(struct cpuinfo_x86 *c) 866 { 867 fix_erratum_1386(c); 868 869 /* Fix up CPUID bits, but only if not virtualised. */ 870 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) { 871 872 /* Erratum 1076: CPB feature bit not being set in CPUID. */ 873 if (!cpu_has(c, X86_FEATURE_CPB)) 874 set_cpu_cap(c, X86_FEATURE_CPB); 875 } 876 877 pr_notice_once("AMD Zen1 DIV0 bug detected. Disable SMT for full protection.\n"); 878 setup_force_cpu_bug(X86_BUG_DIV0); 879 880 /* 881 * Turn off the Instructions Retired free counter on machines that are 882 * susceptible to erratum #1054 "Instructions Retired Performance 883 * Counter May Be Inaccurate". 884 */ 885 if (c->x86_model < 0x30) { 886 msr_clear_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT); 887 clear_cpu_cap(c, X86_FEATURE_IRPERF); 888 } 889 } 890 891 static bool cpu_has_zenbleed_microcode(void) 892 { 893 u32 good_rev = 0; 894 895 switch (boot_cpu_data.x86_model) { 896 case 0x30 ... 0x3f: good_rev = 0x0830107b; break; 897 case 0x60 ... 0x67: good_rev = 0x0860010c; break; 898 case 0x68 ... 0x6f: good_rev = 0x08608107; break; 899 case 0x70 ... 0x7f: good_rev = 0x08701033; break; 900 case 0xa0 ... 0xaf: good_rev = 0x08a00009; break; 901 902 default: 903 return false; 904 } 905 906 if (boot_cpu_data.microcode < good_rev) 907 return false; 908 909 return true; 910 } 911 912 static void zen2_zenbleed_check(struct cpuinfo_x86 *c) 913 { 914 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) 915 return; 916 917 if (!cpu_has(c, X86_FEATURE_AVX)) 918 return; 919 920 if (!cpu_has_zenbleed_microcode()) { 921 pr_notice_once("Zenbleed: please update your microcode for the most optimal fix\n"); 922 msr_set_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT); 923 } else { 924 msr_clear_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT); 925 } 926 } 927 928 static void init_amd_zen2(struct cpuinfo_x86 *c) 929 { 930 init_spectral_chicken(c); 931 fix_erratum_1386(c); 932 zen2_zenbleed_check(c); 933 } 934 935 static void init_amd_zen3(struct cpuinfo_x86 *c) 936 { 937 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) { 938 /* 939 * Zen3 (Fam19 model < 0x10) parts are not susceptible to 940 * Branch Type Confusion, but predate the allocation of the 941 * BTC_NO bit. 942 */ 943 if (!cpu_has(c, X86_FEATURE_BTC_NO)) 944 set_cpu_cap(c, X86_FEATURE_BTC_NO); 945 } 946 } 947 948 static void init_amd_zen4(struct cpuinfo_x86 *c) 949 { 950 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) 951 msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT); 952 953 /* 954 * These Zen4 SoCs advertise support for virtualized VMLOAD/VMSAVE 955 * in some BIOS versions but they can lead to random host reboots. 956 */ 957 switch (c->x86_model) { 958 case 0x18 ... 0x1f: 959 case 0x60 ... 0x7f: 960 clear_cpu_cap(c, X86_FEATURE_V_VMSAVE_VMLOAD); 961 break; 962 } 963 } 964 965 static void init_amd_zen5(struct cpuinfo_x86 *c) 966 { 967 } 968 969 static void init_amd(struct cpuinfo_x86 *c) 970 { 971 u64 vm_cr; 972 973 early_init_amd(c); 974 975 /* 976 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 977 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 978 */ 979 clear_cpu_cap(c, 0*32+31); 980 981 if (c->x86 >= 0x10) 982 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 983 984 /* AMD FSRM also implies FSRS */ 985 if (cpu_has(c, X86_FEATURE_FSRM)) 986 set_cpu_cap(c, X86_FEATURE_FSRS); 987 988 /* K6s reports MCEs but don't actually have all the MSRs */ 989 if (c->x86 < 6) 990 clear_cpu_cap(c, X86_FEATURE_MCE); 991 992 switch (c->x86) { 993 case 4: init_amd_k5(c); break; 994 case 5: init_amd_k6(c); break; 995 case 6: init_amd_k7(c); break; 996 case 0xf: init_amd_k8(c); break; 997 case 0x10: init_amd_gh(c); break; 998 case 0x12: init_amd_ln(c); break; 999 case 0x15: init_amd_bd(c); break; 1000 case 0x16: init_amd_jg(c); break; 1001 } 1002 1003 /* 1004 * Save up on some future enablement work and do common Zen 1005 * settings. 1006 */ 1007 if (c->x86 >= 0x17) 1008 init_amd_zen_common(); 1009 1010 if (boot_cpu_has(X86_FEATURE_ZEN1)) 1011 init_amd_zen1(c); 1012 else if (boot_cpu_has(X86_FEATURE_ZEN2)) 1013 init_amd_zen2(c); 1014 else if (boot_cpu_has(X86_FEATURE_ZEN3)) 1015 init_amd_zen3(c); 1016 else if (boot_cpu_has(X86_FEATURE_ZEN4)) 1017 init_amd_zen4(c); 1018 else if (boot_cpu_has(X86_FEATURE_ZEN5)) 1019 init_amd_zen5(c); 1020 1021 /* 1022 * Enable workaround for FXSAVE leak on CPUs 1023 * without a XSaveErPtr feature 1024 */ 1025 if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR))) 1026 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK); 1027 1028 cpu_detect_cache_sizes(c); 1029 1030 srat_detect_node(c); 1031 1032 init_amd_cacheinfo(c); 1033 1034 if (cpu_has(c, X86_FEATURE_SVM)) { 1035 rdmsrq(MSR_VM_CR, vm_cr); 1036 if (vm_cr & SVM_VM_CR_SVM_DIS_MASK) { 1037 pr_notice_once("SVM disabled (by BIOS) in MSR_VM_CR\n"); 1038 clear_cpu_cap(c, X86_FEATURE_SVM); 1039 } 1040 } 1041 1042 if (!cpu_has(c, X86_FEATURE_LFENCE_RDTSC) && cpu_has(c, X86_FEATURE_XMM2)) { 1043 /* 1044 * Use LFENCE for execution serialization. On families which 1045 * don't have that MSR, LFENCE is already serializing. 1046 * msr_set_bit() uses the safe accessors, too, even if the MSR 1047 * is not present. 1048 */ 1049 msr_set_bit(MSR_AMD64_DE_CFG, 1050 MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT); 1051 1052 /* A serializing LFENCE stops RDTSC speculation */ 1053 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 1054 } 1055 1056 /* 1057 * Family 0x12 and above processors have APIC timer 1058 * running in deep C states. 1059 */ 1060 if (c->x86 > 0x11) 1061 set_cpu_cap(c, X86_FEATURE_ARAT); 1062 1063 /* 3DNow or LM implies PREFETCHW */ 1064 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH)) 1065 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM)) 1066 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH); 1067 1068 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */ 1069 if (!cpu_feature_enabled(X86_FEATURE_XENPV)) 1070 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); 1071 1072 /* Enable the Instructions Retired free counter */ 1073 if (cpu_has(c, X86_FEATURE_IRPERF)) 1074 msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT); 1075 1076 check_null_seg_clears_base(c); 1077 1078 /* 1079 * Make sure EFER[AIBRSE - Automatic IBRS Enable] is set. The APs are brought up 1080 * using the trampoline code and as part of it, MSR_EFER gets prepared there in 1081 * order to be replicated onto them. Regardless, set it here again, if not set, 1082 * to protect against any future refactoring/code reorganization which might 1083 * miss setting this important bit. 1084 */ 1085 if (spectre_v2_in_eibrs_mode(spectre_v2_enabled) && 1086 cpu_has(c, X86_FEATURE_AUTOIBRS)) 1087 WARN_ON_ONCE(msr_set_bit(MSR_EFER, _EFER_AUTOIBRS) < 0); 1088 1089 /* AMD CPUs don't need fencing after x2APIC/TSC_DEADLINE MSR writes. */ 1090 clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE); 1091 1092 /* Enable Translation Cache Extension */ 1093 if (cpu_has(c, X86_FEATURE_TCE)) 1094 msr_set_bit(MSR_EFER, _EFER_TCE); 1095 } 1096 1097 #ifdef CONFIG_X86_32 1098 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) 1099 { 1100 /* AMD errata T13 (order #21922) */ 1101 if (c->x86 == 6) { 1102 /* Duron Rev A0 */ 1103 if (c->x86_model == 3 && c->x86_stepping == 0) 1104 size = 64; 1105 /* Tbird rev A1/A2 */ 1106 if (c->x86_model == 4 && 1107 (c->x86_stepping == 0 || c->x86_stepping == 1)) 1108 size = 256; 1109 } 1110 return size; 1111 } 1112 #endif 1113 1114 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) 1115 { 1116 u32 ebx, eax, ecx, edx; 1117 u16 mask = 0xfff; 1118 1119 if (c->x86 < 0xf) 1120 return; 1121 1122 if (c->extended_cpuid_level < 0x80000006) 1123 return; 1124 1125 cpuid(0x80000006, &eax, &ebx, &ecx, &edx); 1126 1127 tlb_lld_4k = (ebx >> 16) & mask; 1128 tlb_lli_4k = ebx & mask; 1129 1130 /* 1131 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB 1132 * characteristics from the CPUID function 0x80000005 instead. 1133 */ 1134 if (c->x86 == 0xf) { 1135 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 1136 mask = 0xff; 1137 } 1138 1139 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 1140 if (!((eax >> 16) & mask)) 1141 tlb_lld_2m = (cpuid_eax(0x80000005) >> 16) & 0xff; 1142 else 1143 tlb_lld_2m = (eax >> 16) & mask; 1144 1145 /* a 4M entry uses two 2M entries */ 1146 tlb_lld_4m = tlb_lld_2m >> 1; 1147 1148 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 1149 if (!(eax & mask)) { 1150 /* Erratum 658 */ 1151 if (c->x86 == 0x15 && c->x86_model <= 0x1f) { 1152 tlb_lli_2m = 1024; 1153 } else { 1154 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 1155 tlb_lli_2m = eax & 0xff; 1156 } 1157 } else 1158 tlb_lli_2m = eax & mask; 1159 1160 tlb_lli_4m = tlb_lli_2m >> 1; 1161 1162 /* Max number of pages INVLPGB can invalidate in one shot */ 1163 if (cpu_has(c, X86_FEATURE_INVLPGB)) 1164 invlpgb_count_max = (cpuid_edx(0x80000008) & 0xffff) + 1; 1165 } 1166 1167 static const struct cpu_dev amd_cpu_dev = { 1168 .c_vendor = "AMD", 1169 .c_ident = { "AuthenticAMD" }, 1170 #ifdef CONFIG_X86_32 1171 .legacy_models = { 1172 { .family = 4, .model_names = 1173 { 1174 [3] = "486 DX/2", 1175 [7] = "486 DX/2-WB", 1176 [8] = "486 DX/4", 1177 [9] = "486 DX/4-WB", 1178 [14] = "Am5x86-WT", 1179 [15] = "Am5x86-WB" 1180 } 1181 }, 1182 }, 1183 .legacy_cache_size = amd_size_cache, 1184 #endif 1185 .c_early_init = early_init_amd, 1186 .c_detect_tlb = cpu_detect_tlb_amd, 1187 .c_bsp_init = bsp_init_amd, 1188 .c_init = init_amd, 1189 .c_x86_vendor = X86_VENDOR_AMD, 1190 }; 1191 1192 cpu_dev_register(amd_cpu_dev); 1193 1194 static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[4], amd_dr_addr_mask); 1195 1196 static unsigned int amd_msr_dr_addr_masks[] = { 1197 MSR_F16H_DR0_ADDR_MASK, 1198 MSR_F16H_DR1_ADDR_MASK, 1199 MSR_F16H_DR1_ADDR_MASK + 1, 1200 MSR_F16H_DR1_ADDR_MASK + 2 1201 }; 1202 1203 void amd_set_dr_addr_mask(unsigned long mask, unsigned int dr) 1204 { 1205 int cpu = smp_processor_id(); 1206 1207 if (!cpu_feature_enabled(X86_FEATURE_BPEXT)) 1208 return; 1209 1210 if (WARN_ON_ONCE(dr >= ARRAY_SIZE(amd_msr_dr_addr_masks))) 1211 return; 1212 1213 if (per_cpu(amd_dr_addr_mask, cpu)[dr] == mask) 1214 return; 1215 1216 wrmsrq(amd_msr_dr_addr_masks[dr], mask); 1217 per_cpu(amd_dr_addr_mask, cpu)[dr] = mask; 1218 } 1219 1220 unsigned long amd_get_dr_addr_mask(unsigned int dr) 1221 { 1222 if (!cpu_feature_enabled(X86_FEATURE_BPEXT)) 1223 return 0; 1224 1225 if (WARN_ON_ONCE(dr >= ARRAY_SIZE(amd_msr_dr_addr_masks))) 1226 return 0; 1227 1228 return per_cpu(amd_dr_addr_mask[dr], smp_processor_id()); 1229 } 1230 EXPORT_SYMBOL_GPL(amd_get_dr_addr_mask); 1231 1232 static void zenbleed_check_cpu(void *unused) 1233 { 1234 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 1235 1236 zen2_zenbleed_check(c); 1237 } 1238 1239 void amd_check_microcode(void) 1240 { 1241 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) 1242 return; 1243 1244 if (cpu_feature_enabled(X86_FEATURE_ZEN2)) 1245 on_each_cpu(zenbleed_check_cpu, NULL, 1); 1246 } 1247 1248 static const char * const s5_reset_reason_txt[] = { 1249 [0] = "thermal pin BP_THERMTRIP_L was tripped", 1250 [1] = "power button was pressed for 4 seconds", 1251 [2] = "shutdown pin was tripped", 1252 [4] = "remote ASF power off command was received", 1253 [9] = "internal CPU thermal limit was tripped", 1254 [16] = "system reset pin BP_SYS_RST_L was tripped", 1255 [17] = "software issued PCI reset", 1256 [18] = "software wrote 0x4 to reset control register 0xCF9", 1257 [19] = "software wrote 0x6 to reset control register 0xCF9", 1258 [20] = "software wrote 0xE to reset control register 0xCF9", 1259 [21] = "ACPI power state transition occurred", 1260 [22] = "keyboard reset pin KB_RST_L was tripped", 1261 [23] = "internal CPU shutdown event occurred", 1262 [24] = "system failed to boot before failed boot timer expired", 1263 [25] = "hardware watchdog timer expired", 1264 [26] = "remote ASF reset command was received", 1265 [27] = "an uncorrected error caused a data fabric sync flood event", 1266 [29] = "FCH and MP1 failed warm reset handshake", 1267 [30] = "a parity error occurred", 1268 [31] = "a software sync flood event occurred", 1269 }; 1270 1271 static __init int print_s5_reset_status_mmio(void) 1272 { 1273 unsigned long value; 1274 void __iomem *addr; 1275 int i; 1276 1277 if (!cpu_feature_enabled(X86_FEATURE_ZEN)) 1278 return 0; 1279 1280 addr = ioremap(FCH_PM_BASE + FCH_PM_S5_RESET_STATUS, sizeof(value)); 1281 if (!addr) 1282 return 0; 1283 1284 value = ioread32(addr); 1285 iounmap(addr); 1286 1287 for (i = 0; i < ARRAY_SIZE(s5_reset_reason_txt); i++) { 1288 if (!(value & BIT(i))) 1289 continue; 1290 1291 if (s5_reset_reason_txt[i]) { 1292 pr_info("x86/amd: Previous system reset reason [0x%08lx]: %s\n", 1293 value, s5_reset_reason_txt[i]); 1294 } 1295 } 1296 1297 return 0; 1298 } 1299 late_initcall(print_s5_reset_status_mmio); 1300