1 #include <linux/init.h> 2 #include <linux/bitops.h> 3 #include <linux/elf.h> 4 #include <linux/mm.h> 5 6 #include <linux/io.h> 7 #include <asm/processor.h> 8 #include <asm/apic.h> 9 #include <asm/cpu.h> 10 #include <asm/pci-direct.h> 11 12 #ifdef CONFIG_X86_64 13 # include <asm/numa_64.h> 14 # include <asm/mmconfig.h> 15 # include <asm/cacheflush.h> 16 #endif 17 18 #include "cpu.h" 19 20 #ifdef CONFIG_X86_32 21 /* 22 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 23 * misexecution of code under Linux. Owners of such processors should 24 * contact AMD for precise details and a CPU swap. 25 * 26 * See http://www.multimania.com/poulot/k6bug.html 27 * http://www.amd.com/K6/k6docs/revgd.html 28 * 29 * The following test is erm.. interesting. AMD neglected to up 30 * the chip setting when fixing the bug but they also tweaked some 31 * performance at the same time.. 32 */ 33 34 extern void vide(void); 35 __asm__(".align 4\nvide: ret"); 36 37 static void __cpuinit init_amd_k5(struct cpuinfo_x86 *c) 38 { 39 /* 40 * General Systems BIOSen alias the cpu frequency registers 41 * of the Elan at 0x000df000. Unfortuantly, one of the Linux 42 * drivers subsequently pokes it, and changes the CPU speed. 43 * Workaround : Remove the unneeded alias. 44 */ 45 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 46 #define CBAR_ENB (0x80000000) 47 #define CBAR_KEY (0X000000CB) 48 if (c->x86_model == 9 || c->x86_model == 10) { 49 if (inl(CBAR) & CBAR_ENB) 50 outl(0 | CBAR_KEY, CBAR); 51 } 52 } 53 54 55 static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c) 56 { 57 u32 l, h; 58 int mbytes = num_physpages >> (20-PAGE_SHIFT); 59 60 if (c->x86_model < 6) { 61 /* Based on AMD doc 20734R - June 2000 */ 62 if (c->x86_model == 0) { 63 clear_cpu_cap(c, X86_FEATURE_APIC); 64 set_cpu_cap(c, X86_FEATURE_PGE); 65 } 66 return; 67 } 68 69 if (c->x86_model == 6 && c->x86_mask == 1) { 70 const int K6_BUG_LOOP = 1000000; 71 int n; 72 void (*f_vide)(void); 73 unsigned long d, d2; 74 75 printk(KERN_INFO "AMD K6 stepping B detected - "); 76 77 /* 78 * It looks like AMD fixed the 2.6.2 bug and improved indirect 79 * calls at the same time. 80 */ 81 82 n = K6_BUG_LOOP; 83 f_vide = vide; 84 rdtscl(d); 85 while (n--) 86 f_vide(); 87 rdtscl(d2); 88 d = d2-d; 89 90 if (d > 20*K6_BUG_LOOP) 91 printk(KERN_CONT 92 "system stability may be impaired when more than 32 MB are used.\n"); 93 else 94 printk(KERN_CONT "probably OK (after B9730xxxx).\n"); 95 printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n"); 96 } 97 98 /* K6 with old style WHCR */ 99 if (c->x86_model < 8 || 100 (c->x86_model == 8 && c->x86_mask < 8)) { 101 /* We can only write allocate on the low 508Mb */ 102 if (mbytes > 508) 103 mbytes = 508; 104 105 rdmsr(MSR_K6_WHCR, l, h); 106 if ((l&0x0000FFFF) == 0) { 107 unsigned long flags; 108 l = (1<<0)|((mbytes/4)<<1); 109 local_irq_save(flags); 110 wbinvd(); 111 wrmsr(MSR_K6_WHCR, l, h); 112 local_irq_restore(flags); 113 printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n", 114 mbytes); 115 } 116 return; 117 } 118 119 if ((c->x86_model == 8 && c->x86_mask > 7) || 120 c->x86_model == 9 || c->x86_model == 13) { 121 /* The more serious chips .. */ 122 123 if (mbytes > 4092) 124 mbytes = 4092; 125 126 rdmsr(MSR_K6_WHCR, l, h); 127 if ((l&0xFFFF0000) == 0) { 128 unsigned long flags; 129 l = ((mbytes>>2)<<22)|(1<<16); 130 local_irq_save(flags); 131 wbinvd(); 132 wrmsr(MSR_K6_WHCR, l, h); 133 local_irq_restore(flags); 134 printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n", 135 mbytes); 136 } 137 138 return; 139 } 140 141 if (c->x86_model == 10) { 142 /* AMD Geode LX is model 10 */ 143 /* placeholder for any needed mods */ 144 return; 145 } 146 } 147 148 static void __cpuinit amd_k7_smp_check(struct cpuinfo_x86 *c) 149 { 150 #ifdef CONFIG_SMP 151 /* calling is from identify_secondary_cpu() ? */ 152 if (!c->cpu_index) 153 return; 154 155 /* 156 * Certain Athlons might work (for various values of 'work') in SMP 157 * but they are not certified as MP capable. 158 */ 159 /* Athlon 660/661 is valid. */ 160 if ((c->x86_model == 6) && ((c->x86_mask == 0) || 161 (c->x86_mask == 1))) 162 goto valid_k7; 163 164 /* Duron 670 is valid */ 165 if ((c->x86_model == 7) && (c->x86_mask == 0)) 166 goto valid_k7; 167 168 /* 169 * Athlon 662, Duron 671, and Athlon >model 7 have capability 170 * bit. It's worth noting that the A5 stepping (662) of some 171 * Athlon XP's have the MP bit set. 172 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for 173 * more. 174 */ 175 if (((c->x86_model == 6) && (c->x86_mask >= 2)) || 176 ((c->x86_model == 7) && (c->x86_mask >= 1)) || 177 (c->x86_model > 7)) 178 if (cpu_has_mp) 179 goto valid_k7; 180 181 /* If we get here, not a certified SMP capable AMD system. */ 182 183 /* 184 * Don't taint if we are running SMP kernel on a single non-MP 185 * approved Athlon 186 */ 187 WARN_ONCE(1, "WARNING: This combination of AMD" 188 " processors is not suitable for SMP.\n"); 189 if (!test_taint(TAINT_UNSAFE_SMP)) 190 add_taint(TAINT_UNSAFE_SMP); 191 192 valid_k7: 193 ; 194 #endif 195 } 196 197 static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c) 198 { 199 u32 l, h; 200 201 /* 202 * Bit 15 of Athlon specific MSR 15, needs to be 0 203 * to enable SSE on Palomino/Morgan/Barton CPU's. 204 * If the BIOS didn't enable it already, enable it here. 205 */ 206 if (c->x86_model >= 6 && c->x86_model <= 10) { 207 if (!cpu_has(c, X86_FEATURE_XMM)) { 208 printk(KERN_INFO "Enabling disabled K7/SSE Support.\n"); 209 rdmsr(MSR_K7_HWCR, l, h); 210 l &= ~0x00008000; 211 wrmsr(MSR_K7_HWCR, l, h); 212 set_cpu_cap(c, X86_FEATURE_XMM); 213 } 214 } 215 216 /* 217 * It's been determined by AMD that Athlons since model 8 stepping 1 218 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 219 * As per AMD technical note 27212 0.2 220 */ 221 if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) { 222 rdmsr(MSR_K7_CLK_CTL, l, h); 223 if ((l & 0xfff00000) != 0x20000000) { 224 printk(KERN_INFO 225 "CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", 226 l, ((l & 0x000fffff)|0x20000000)); 227 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 228 } 229 } 230 231 set_cpu_cap(c, X86_FEATURE_K7); 232 233 amd_k7_smp_check(c); 234 } 235 #endif 236 237 #ifdef CONFIG_NUMA 238 /* 239 * To workaround broken NUMA config. Read the comment in 240 * srat_detect_node(). 241 */ 242 static int __cpuinit nearby_node(int apicid) 243 { 244 int i, node; 245 246 for (i = apicid - 1; i >= 0; i--) { 247 node = __apicid_to_node[i]; 248 if (node != NUMA_NO_NODE && node_online(node)) 249 return node; 250 } 251 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 252 node = __apicid_to_node[i]; 253 if (node != NUMA_NO_NODE && node_online(node)) 254 return node; 255 } 256 return first_node(node_online_map); /* Shouldn't happen */ 257 } 258 #endif 259 260 /* 261 * Fixup core topology information for 262 * (1) AMD multi-node processors 263 * Assumption: Number of cores in each internal node is the same. 264 * (2) AMD processors supporting compute units 265 */ 266 #ifdef CONFIG_X86_HT 267 static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c) 268 { 269 u32 nodes, cores_per_cu = 1; 270 u8 node_id; 271 int cpu = smp_processor_id(); 272 273 /* get information required for multi-node processors */ 274 if (cpu_has(c, X86_FEATURE_TOPOEXT)) { 275 u32 eax, ebx, ecx, edx; 276 277 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); 278 nodes = ((ecx >> 8) & 7) + 1; 279 node_id = ecx & 7; 280 281 /* get compute unit information */ 282 smp_num_siblings = ((ebx >> 8) & 3) + 1; 283 c->compute_unit_id = ebx & 0xff; 284 cores_per_cu += ((ebx >> 8) & 3); 285 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { 286 u64 value; 287 288 rdmsrl(MSR_FAM10H_NODE_ID, value); 289 nodes = ((value >> 3) & 7) + 1; 290 node_id = value & 7; 291 } else 292 return; 293 294 /* fixup multi-node processor information */ 295 if (nodes > 1) { 296 u32 cores_per_node; 297 u32 cus_per_node; 298 299 set_cpu_cap(c, X86_FEATURE_AMD_DCM); 300 cores_per_node = c->x86_max_cores / nodes; 301 cus_per_node = cores_per_node / cores_per_cu; 302 303 /* store NodeID, use llc_shared_map to store sibling info */ 304 per_cpu(cpu_llc_id, cpu) = node_id; 305 306 /* core id has to be in the [0 .. cores_per_node - 1] range */ 307 c->cpu_core_id %= cores_per_node; 308 c->compute_unit_id %= cus_per_node; 309 } 310 } 311 #endif 312 313 /* 314 * On a AMD dual core setup the lower bits of the APIC id distingush the cores. 315 * Assumes number of cores is a power of two. 316 */ 317 static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c) 318 { 319 #ifdef CONFIG_X86_HT 320 unsigned bits; 321 int cpu = smp_processor_id(); 322 323 bits = c->x86_coreid_bits; 324 /* Low order bits define the core id (index of core in socket) */ 325 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); 326 /* Convert the initial APIC ID into the socket ID */ 327 c->phys_proc_id = c->initial_apicid >> bits; 328 /* use socket ID also for last level cache */ 329 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; 330 amd_get_topology(c); 331 #endif 332 } 333 334 int amd_get_nb_id(int cpu) 335 { 336 int id = 0; 337 #ifdef CONFIG_SMP 338 id = per_cpu(cpu_llc_id, cpu); 339 #endif 340 return id; 341 } 342 EXPORT_SYMBOL_GPL(amd_get_nb_id); 343 344 static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c) 345 { 346 #ifdef CONFIG_NUMA 347 int cpu = smp_processor_id(); 348 int node; 349 unsigned apicid = c->apicid; 350 351 node = numa_cpu_node(cpu); 352 if (node == NUMA_NO_NODE) 353 node = per_cpu(cpu_llc_id, cpu); 354 355 if (!node_online(node)) { 356 /* 357 * Two possibilities here: 358 * 359 * - The CPU is missing memory and no node was created. In 360 * that case try picking one from a nearby CPU. 361 * 362 * - The APIC IDs differ from the HyperTransport node IDs 363 * which the K8 northbridge parsing fills in. Assume 364 * they are all increased by a constant offset, but in 365 * the same order as the HT nodeids. If that doesn't 366 * result in a usable node fall back to the path for the 367 * previous case. 368 * 369 * This workaround operates directly on the mapping between 370 * APIC ID and NUMA node, assuming certain relationship 371 * between APIC ID, HT node ID and NUMA topology. As going 372 * through CPU mapping may alter the outcome, directly 373 * access __apicid_to_node[]. 374 */ 375 int ht_nodeid = c->initial_apicid; 376 377 if (ht_nodeid >= 0 && 378 __apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 379 node = __apicid_to_node[ht_nodeid]; 380 /* Pick a nearby node */ 381 if (!node_online(node)) 382 node = nearby_node(apicid); 383 } 384 numa_set_node(cpu, node); 385 #endif 386 } 387 388 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c) 389 { 390 #ifdef CONFIG_X86_HT 391 unsigned bits, ecx; 392 393 /* Multi core CPU? */ 394 if (c->extended_cpuid_level < 0x80000008) 395 return; 396 397 ecx = cpuid_ecx(0x80000008); 398 399 c->x86_max_cores = (ecx & 0xff) + 1; 400 401 /* CPU telling us the core id bits shift? */ 402 bits = (ecx >> 12) & 0xF; 403 404 /* Otherwise recompute */ 405 if (bits == 0) { 406 while ((1 << bits) < c->x86_max_cores) 407 bits++; 408 } 409 410 c->x86_coreid_bits = bits; 411 #endif 412 } 413 414 static void __cpuinit bsp_init_amd(struct cpuinfo_x86 *c) 415 { 416 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 417 418 if (c->x86 > 0x10 || 419 (c->x86 == 0x10 && c->x86_model >= 0x2)) { 420 u64 val; 421 422 rdmsrl(MSR_K7_HWCR, val); 423 if (!(val & BIT(24))) 424 printk(KERN_WARNING FW_BUG "TSC doesn't count " 425 "with P0 frequency!\n"); 426 } 427 } 428 429 if (c->x86 == 0x15) { 430 unsigned long upperbit; 431 u32 cpuid, assoc; 432 433 cpuid = cpuid_edx(0x80000005); 434 assoc = cpuid >> 16 & 0xff; 435 upperbit = ((cpuid >> 24) << 10) / assoc; 436 437 va_align.mask = (upperbit - 1) & PAGE_MASK; 438 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; 439 } 440 } 441 442 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c) 443 { 444 u32 dummy; 445 446 early_init_amd_mc(c); 447 448 /* 449 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 450 * with P/T states and does not stop in deep C-states 451 */ 452 if (c->x86_power & (1 << 8)) { 453 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 454 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 455 } 456 457 #ifdef CONFIG_X86_64 458 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 459 #else 460 /* Set MTRR capability flag if appropriate */ 461 if (c->x86 == 5) 462 if (c->x86_model == 13 || c->x86_model == 9 || 463 (c->x86_model == 8 && c->x86_mask >= 8)) 464 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 465 #endif 466 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 467 /* check CPU config space for extended APIC ID */ 468 if (cpu_has_apic && c->x86 >= 0xf) { 469 unsigned int val; 470 val = read_pci_config(0, 24, 0, 0x68); 471 if ((val & ((1 << 17) | (1 << 18))) == ((1 << 17) | (1 << 18))) 472 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 473 } 474 #endif 475 476 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); 477 } 478 479 static void __cpuinit init_amd(struct cpuinfo_x86 *c) 480 { 481 #ifdef CONFIG_SMP 482 unsigned long long value; 483 484 /* 485 * Disable TLB flush filter by setting HWCR.FFDIS on K8 486 * bit 6 of msr C001_0015 487 * 488 * Errata 63 for SH-B3 steppings 489 * Errata 122 for all steppings (F+ have it disabled by default) 490 */ 491 if (c->x86 == 0xf) { 492 rdmsrl(MSR_K7_HWCR, value); 493 value |= 1 << 6; 494 wrmsrl(MSR_K7_HWCR, value); 495 } 496 #endif 497 498 early_init_amd(c); 499 500 /* 501 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 502 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 503 */ 504 clear_cpu_cap(c, 0*32+31); 505 506 #ifdef CONFIG_X86_64 507 /* On C+ stepping K8 rep microcode works well for copy/memset */ 508 if (c->x86 == 0xf) { 509 u32 level; 510 511 level = cpuid_eax(1); 512 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) 513 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 514 515 /* 516 * Some BIOSes incorrectly force this feature, but only K8 517 * revision D (model = 0x14) and later actually support it. 518 * (AMD Erratum #110, docId: 25759). 519 */ 520 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { 521 u64 val; 522 523 clear_cpu_cap(c, X86_FEATURE_LAHF_LM); 524 if (!rdmsrl_amd_safe(0xc001100d, &val)) { 525 val &= ~(1ULL << 32); 526 wrmsrl_amd_safe(0xc001100d, val); 527 } 528 } 529 530 } 531 if (c->x86 >= 0x10) 532 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 533 534 /* get apicid instead of initial apic id from cpuid */ 535 c->apicid = hard_smp_processor_id(); 536 #else 537 538 /* 539 * FIXME: We should handle the K5 here. Set up the write 540 * range and also turn on MSR 83 bits 4 and 31 (write alloc, 541 * no bus pipeline) 542 */ 543 544 switch (c->x86) { 545 case 4: 546 init_amd_k5(c); 547 break; 548 case 5: 549 init_amd_k6(c); 550 break; 551 case 6: /* An Athlon/Duron */ 552 init_amd_k7(c); 553 break; 554 } 555 556 /* K6s reports MCEs but don't actually have all the MSRs */ 557 if (c->x86 < 6) 558 clear_cpu_cap(c, X86_FEATURE_MCE); 559 #endif 560 561 /* Enable workaround for FXSAVE leak */ 562 if (c->x86 >= 6) 563 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK); 564 565 if (!c->x86_model_id[0]) { 566 switch (c->x86) { 567 case 0xf: 568 /* Should distinguish Models here, but this is only 569 a fallback anyways. */ 570 strcpy(c->x86_model_id, "Hammer"); 571 break; 572 } 573 } 574 575 cpu_detect_cache_sizes(c); 576 577 /* Multi core CPU? */ 578 if (c->extended_cpuid_level >= 0x80000008) { 579 amd_detect_cmp(c); 580 srat_detect_node(c); 581 } 582 583 #ifdef CONFIG_X86_32 584 detect_ht(c); 585 #endif 586 587 if (c->extended_cpuid_level >= 0x80000006) { 588 if (cpuid_edx(0x80000006) & 0xf000) 589 num_cache_leaves = 4; 590 else 591 num_cache_leaves = 3; 592 } 593 594 if (c->x86 >= 0xf) 595 set_cpu_cap(c, X86_FEATURE_K8); 596 597 if (cpu_has_xmm2) { 598 /* MFENCE stops RDTSC speculation */ 599 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); 600 } 601 602 #ifdef CONFIG_X86_64 603 if (c->x86 == 0x10) { 604 /* do this for boot cpu */ 605 if (c == &boot_cpu_data) 606 check_enable_amd_mmconf_dmi(); 607 608 fam10h_check_enable_mmcfg(); 609 } 610 611 if (c == &boot_cpu_data && c->x86 >= 0xf) { 612 unsigned long long tseg; 613 614 /* 615 * Split up direct mapping around the TSEG SMM area. 616 * Don't do it for gbpages because there seems very little 617 * benefit in doing so. 618 */ 619 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { 620 printk(KERN_DEBUG "tseg: %010llx\n", tseg); 621 if ((tseg>>PMD_SHIFT) < 622 (max_low_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) || 623 ((tseg>>PMD_SHIFT) < 624 (max_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) && 625 (tseg>>PMD_SHIFT) >= (1ULL<<(32 - PMD_SHIFT)))) 626 set_memory_4k((unsigned long)__va(tseg), 1); 627 } 628 } 629 #endif 630 631 /* 632 * Family 0x12 and above processors have APIC timer 633 * running in deep C states. 634 */ 635 if (c->x86 > 0x11) 636 set_cpu_cap(c, X86_FEATURE_ARAT); 637 638 /* 639 * Disable GART TLB Walk Errors on Fam10h. We do this here 640 * because this is always needed when GART is enabled, even in a 641 * kernel which has no MCE support built in. 642 */ 643 if (c->x86 == 0x10) { 644 /* 645 * BIOS should disable GartTlbWlk Errors themself. If 646 * it doesn't do it here as suggested by the BKDG. 647 * 648 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 649 */ 650 u64 mask; 651 int err; 652 653 err = rdmsrl_safe(MSR_AMD64_MCx_MASK(4), &mask); 654 if (err == 0) { 655 mask |= (1 << 10); 656 checking_wrmsrl(MSR_AMD64_MCx_MASK(4), mask); 657 } 658 } 659 } 660 661 #ifdef CONFIG_X86_32 662 static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, 663 unsigned int size) 664 { 665 /* AMD errata T13 (order #21922) */ 666 if ((c->x86 == 6)) { 667 /* Duron Rev A0 */ 668 if (c->x86_model == 3 && c->x86_mask == 0) 669 size = 64; 670 /* Tbird rev A1/A2 */ 671 if (c->x86_model == 4 && 672 (c->x86_mask == 0 || c->x86_mask == 1)) 673 size = 256; 674 } 675 return size; 676 } 677 #endif 678 679 static const struct cpu_dev __cpuinitconst amd_cpu_dev = { 680 .c_vendor = "AMD", 681 .c_ident = { "AuthenticAMD" }, 682 #ifdef CONFIG_X86_32 683 .c_models = { 684 { .vendor = X86_VENDOR_AMD, .family = 4, .model_names = 685 { 686 [3] = "486 DX/2", 687 [7] = "486 DX/2-WB", 688 [8] = "486 DX/4", 689 [9] = "486 DX/4-WB", 690 [14] = "Am5x86-WT", 691 [15] = "Am5x86-WB" 692 } 693 }, 694 }, 695 .c_size_cache = amd_size_cache, 696 #endif 697 .c_early_init = early_init_amd, 698 .c_bsp_init = bsp_init_amd, 699 .c_init = init_amd, 700 .c_x86_vendor = X86_VENDOR_AMD, 701 }; 702 703 cpu_dev_register(amd_cpu_dev); 704 705 /* 706 * AMD errata checking 707 * 708 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or 709 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that 710 * have an OSVW id assigned, which it takes as first argument. Both take a 711 * variable number of family-specific model-stepping ranges created by 712 * AMD_MODEL_RANGE(). Each erratum also has to be declared as extern const 713 * int[] in arch/x86/include/asm/processor.h. 714 * 715 * Example: 716 * 717 * const int amd_erratum_319[] = 718 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), 719 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), 720 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); 721 */ 722 723 const int amd_erratum_400[] = 724 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), 725 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); 726 EXPORT_SYMBOL_GPL(amd_erratum_400); 727 728 const int amd_erratum_383[] = 729 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); 730 EXPORT_SYMBOL_GPL(amd_erratum_383); 731 732 bool cpu_has_amd_erratum(const int *erratum) 733 { 734 struct cpuinfo_x86 *cpu = __this_cpu_ptr(&cpu_info); 735 int osvw_id = *erratum++; 736 u32 range; 737 u32 ms; 738 739 /* 740 * If called early enough that current_cpu_data hasn't been initialized 741 * yet, fall back to boot_cpu_data. 742 */ 743 if (cpu->x86 == 0) 744 cpu = &boot_cpu_data; 745 746 if (cpu->x86_vendor != X86_VENDOR_AMD) 747 return false; 748 749 if (osvw_id >= 0 && osvw_id < 65536 && 750 cpu_has(cpu, X86_FEATURE_OSVW)) { 751 u64 osvw_len; 752 753 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); 754 if (osvw_id < osvw_len) { 755 u64 osvw_bits; 756 757 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), 758 osvw_bits); 759 return osvw_bits & (1ULL << (osvw_id & 0x3f)); 760 } 761 } 762 763 /* OSVW unavailable or ID unknown, match family-model-stepping range */ 764 ms = (cpu->x86_model << 4) | cpu->x86_mask; 765 while ((range = *erratum++)) 766 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && 767 (ms >= AMD_MODEL_RANGE_START(range)) && 768 (ms <= AMD_MODEL_RANGE_END(range))) 769 return true; 770 771 return false; 772 } 773 774 EXPORT_SYMBOL_GPL(cpu_has_amd_erratum); 775