1 #include <linux/export.h> 2 #include <linux/bitops.h> 3 #include <linux/elf.h> 4 #include <linux/mm.h> 5 6 #include <linux/io.h> 7 #include <linux/sched.h> 8 #include <linux/random.h> 9 #include <asm/processor.h> 10 #include <asm/apic.h> 11 #include <asm/cpu.h> 12 #include <asm/smp.h> 13 #include <asm/pci-direct.h> 14 #include <asm/delay.h> 15 16 #ifdef CONFIG_X86_64 17 # include <asm/mmconfig.h> 18 # include <asm/cacheflush.h> 19 #endif 20 21 #include "cpu.h" 22 23 /* 24 * nodes_per_socket: Stores the number of nodes per socket. 25 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX 26 * Node Identifiers[10:8] 27 */ 28 static u32 nodes_per_socket = 1; 29 30 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) 31 { 32 u32 gprs[8] = { 0 }; 33 int err; 34 35 WARN_ONCE((boot_cpu_data.x86 != 0xf), 36 "%s should only be used on K8!\n", __func__); 37 38 gprs[1] = msr; 39 gprs[7] = 0x9c5a203a; 40 41 err = rdmsr_safe_regs(gprs); 42 43 *p = gprs[0] | ((u64)gprs[2] << 32); 44 45 return err; 46 } 47 48 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) 49 { 50 u32 gprs[8] = { 0 }; 51 52 WARN_ONCE((boot_cpu_data.x86 != 0xf), 53 "%s should only be used on K8!\n", __func__); 54 55 gprs[0] = (u32)val; 56 gprs[1] = msr; 57 gprs[2] = val >> 32; 58 gprs[7] = 0x9c5a203a; 59 60 return wrmsr_safe_regs(gprs); 61 } 62 63 /* 64 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 65 * misexecution of code under Linux. Owners of such processors should 66 * contact AMD for precise details and a CPU swap. 67 * 68 * See http://www.multimania.com/poulot/k6bug.html 69 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" 70 * (Publication # 21266 Issue Date: August 1998) 71 * 72 * The following test is erm.. interesting. AMD neglected to up 73 * the chip setting when fixing the bug but they also tweaked some 74 * performance at the same time.. 75 */ 76 77 extern __visible void vide(void); 78 __asm__(".globl vide\n" 79 ".type vide, @function\n" 80 ".align 4\n" 81 "vide: ret\n"); 82 83 static void init_amd_k5(struct cpuinfo_x86 *c) 84 { 85 #ifdef CONFIG_X86_32 86 /* 87 * General Systems BIOSen alias the cpu frequency registers 88 * of the Elan at 0x000df000. Unfortuantly, one of the Linux 89 * drivers subsequently pokes it, and changes the CPU speed. 90 * Workaround : Remove the unneeded alias. 91 */ 92 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 93 #define CBAR_ENB (0x80000000) 94 #define CBAR_KEY (0X000000CB) 95 if (c->x86_model == 9 || c->x86_model == 10) { 96 if (inl(CBAR) & CBAR_ENB) 97 outl(0 | CBAR_KEY, CBAR); 98 } 99 #endif 100 } 101 102 static void init_amd_k6(struct cpuinfo_x86 *c) 103 { 104 #ifdef CONFIG_X86_32 105 u32 l, h; 106 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); 107 108 if (c->x86_model < 6) { 109 /* Based on AMD doc 20734R - June 2000 */ 110 if (c->x86_model == 0) { 111 clear_cpu_cap(c, X86_FEATURE_APIC); 112 set_cpu_cap(c, X86_FEATURE_PGE); 113 } 114 return; 115 } 116 117 if (c->x86_model == 6 && c->x86_mask == 1) { 118 const int K6_BUG_LOOP = 1000000; 119 int n; 120 void (*f_vide)(void); 121 u64 d, d2; 122 123 printk(KERN_INFO "AMD K6 stepping B detected - "); 124 125 /* 126 * It looks like AMD fixed the 2.6.2 bug and improved indirect 127 * calls at the same time. 128 */ 129 130 n = K6_BUG_LOOP; 131 f_vide = vide; 132 d = rdtsc(); 133 while (n--) 134 f_vide(); 135 d2 = rdtsc(); 136 d = d2-d; 137 138 if (d > 20*K6_BUG_LOOP) 139 printk(KERN_CONT 140 "system stability may be impaired when more than 32 MB are used.\n"); 141 else 142 printk(KERN_CONT "probably OK (after B9730xxxx).\n"); 143 } 144 145 /* K6 with old style WHCR */ 146 if (c->x86_model < 8 || 147 (c->x86_model == 8 && c->x86_mask < 8)) { 148 /* We can only write allocate on the low 508Mb */ 149 if (mbytes > 508) 150 mbytes = 508; 151 152 rdmsr(MSR_K6_WHCR, l, h); 153 if ((l&0x0000FFFF) == 0) { 154 unsigned long flags; 155 l = (1<<0)|((mbytes/4)<<1); 156 local_irq_save(flags); 157 wbinvd(); 158 wrmsr(MSR_K6_WHCR, l, h); 159 local_irq_restore(flags); 160 printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n", 161 mbytes); 162 } 163 return; 164 } 165 166 if ((c->x86_model == 8 && c->x86_mask > 7) || 167 c->x86_model == 9 || c->x86_model == 13) { 168 /* The more serious chips .. */ 169 170 if (mbytes > 4092) 171 mbytes = 4092; 172 173 rdmsr(MSR_K6_WHCR, l, h); 174 if ((l&0xFFFF0000) == 0) { 175 unsigned long flags; 176 l = ((mbytes>>2)<<22)|(1<<16); 177 local_irq_save(flags); 178 wbinvd(); 179 wrmsr(MSR_K6_WHCR, l, h); 180 local_irq_restore(flags); 181 printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n", 182 mbytes); 183 } 184 185 return; 186 } 187 188 if (c->x86_model == 10) { 189 /* AMD Geode LX is model 10 */ 190 /* placeholder for any needed mods */ 191 return; 192 } 193 #endif 194 } 195 196 static void init_amd_k7(struct cpuinfo_x86 *c) 197 { 198 #ifdef CONFIG_X86_32 199 u32 l, h; 200 201 /* 202 * Bit 15 of Athlon specific MSR 15, needs to be 0 203 * to enable SSE on Palomino/Morgan/Barton CPU's. 204 * If the BIOS didn't enable it already, enable it here. 205 */ 206 if (c->x86_model >= 6 && c->x86_model <= 10) { 207 if (!cpu_has(c, X86_FEATURE_XMM)) { 208 printk(KERN_INFO "Enabling disabled K7/SSE Support.\n"); 209 msr_clear_bit(MSR_K7_HWCR, 15); 210 set_cpu_cap(c, X86_FEATURE_XMM); 211 } 212 } 213 214 /* 215 * It's been determined by AMD that Athlons since model 8 stepping 1 216 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 217 * As per AMD technical note 27212 0.2 218 */ 219 if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) { 220 rdmsr(MSR_K7_CLK_CTL, l, h); 221 if ((l & 0xfff00000) != 0x20000000) { 222 printk(KERN_INFO 223 "CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", 224 l, ((l & 0x000fffff)|0x20000000)); 225 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 226 } 227 } 228 229 set_cpu_cap(c, X86_FEATURE_K7); 230 231 /* calling is from identify_secondary_cpu() ? */ 232 if (!c->cpu_index) 233 return; 234 235 /* 236 * Certain Athlons might work (for various values of 'work') in SMP 237 * but they are not certified as MP capable. 238 */ 239 /* Athlon 660/661 is valid. */ 240 if ((c->x86_model == 6) && ((c->x86_mask == 0) || 241 (c->x86_mask == 1))) 242 return; 243 244 /* Duron 670 is valid */ 245 if ((c->x86_model == 7) && (c->x86_mask == 0)) 246 return; 247 248 /* 249 * Athlon 662, Duron 671, and Athlon >model 7 have capability 250 * bit. It's worth noting that the A5 stepping (662) of some 251 * Athlon XP's have the MP bit set. 252 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for 253 * more. 254 */ 255 if (((c->x86_model == 6) && (c->x86_mask >= 2)) || 256 ((c->x86_model == 7) && (c->x86_mask >= 1)) || 257 (c->x86_model > 7)) 258 if (cpu_has(c, X86_FEATURE_MP)) 259 return; 260 261 /* If we get here, not a certified SMP capable AMD system. */ 262 263 /* 264 * Don't taint if we are running SMP kernel on a single non-MP 265 * approved Athlon 266 */ 267 WARN_ONCE(1, "WARNING: This combination of AMD" 268 " processors is not suitable for SMP.\n"); 269 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 270 #endif 271 } 272 273 #ifdef CONFIG_NUMA 274 /* 275 * To workaround broken NUMA config. Read the comment in 276 * srat_detect_node(). 277 */ 278 static int nearby_node(int apicid) 279 { 280 int i, node; 281 282 for (i = apicid - 1; i >= 0; i--) { 283 node = __apicid_to_node[i]; 284 if (node != NUMA_NO_NODE && node_online(node)) 285 return node; 286 } 287 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 288 node = __apicid_to_node[i]; 289 if (node != NUMA_NO_NODE && node_online(node)) 290 return node; 291 } 292 return first_node(node_online_map); /* Shouldn't happen */ 293 } 294 #endif 295 296 /* 297 * Fixup core topology information for 298 * (1) AMD multi-node processors 299 * Assumption: Number of cores in each internal node is the same. 300 * (2) AMD processors supporting compute units 301 */ 302 #ifdef CONFIG_SMP 303 static void amd_get_topology(struct cpuinfo_x86 *c) 304 { 305 u32 cores_per_cu = 1; 306 u8 node_id; 307 int cpu = smp_processor_id(); 308 309 /* get information required for multi-node processors */ 310 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 311 u32 eax, ebx, ecx, edx; 312 313 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); 314 nodes_per_socket = ((ecx >> 8) & 7) + 1; 315 node_id = ecx & 7; 316 317 /* get compute unit information */ 318 smp_num_siblings = ((ebx >> 8) & 3) + 1; 319 c->compute_unit_id = ebx & 0xff; 320 cores_per_cu += ((ebx >> 8) & 3); 321 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { 322 u64 value; 323 324 rdmsrl(MSR_FAM10H_NODE_ID, value); 325 nodes_per_socket = ((value >> 3) & 7) + 1; 326 node_id = value & 7; 327 } else 328 return; 329 330 /* fixup multi-node processor information */ 331 if (nodes_per_socket > 1) { 332 u32 cores_per_node; 333 u32 cus_per_node; 334 335 set_cpu_cap(c, X86_FEATURE_AMD_DCM); 336 cores_per_node = c->x86_max_cores / nodes_per_socket; 337 cus_per_node = cores_per_node / cores_per_cu; 338 339 /* store NodeID, use llc_shared_map to store sibling info */ 340 per_cpu(cpu_llc_id, cpu) = node_id; 341 342 /* core id has to be in the [0 .. cores_per_node - 1] range */ 343 c->cpu_core_id %= cores_per_node; 344 c->compute_unit_id %= cus_per_node; 345 } 346 } 347 #endif 348 349 /* 350 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores. 351 * Assumes number of cores is a power of two. 352 */ 353 static void amd_detect_cmp(struct cpuinfo_x86 *c) 354 { 355 #ifdef CONFIG_SMP 356 unsigned bits; 357 int cpu = smp_processor_id(); 358 unsigned int socket_id, core_complex_id; 359 360 bits = c->x86_coreid_bits; 361 /* Low order bits define the core id (index of core in socket) */ 362 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); 363 /* Convert the initial APIC ID into the socket ID */ 364 c->phys_proc_id = c->initial_apicid >> bits; 365 /* use socket ID also for last level cache */ 366 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; 367 amd_get_topology(c); 368 369 /* 370 * Fix percpu cpu_llc_id here as LLC topology is different 371 * for Fam17h systems. 372 */ 373 if (c->x86 != 0x17 || !cpuid_edx(0x80000006)) 374 return; 375 376 socket_id = (c->apicid >> bits) - 1; 377 core_complex_id = (c->apicid & ((1 << bits) - 1)) >> 3; 378 379 per_cpu(cpu_llc_id, cpu) = (socket_id << 3) | core_complex_id; 380 #endif 381 } 382 383 u16 amd_get_nb_id(int cpu) 384 { 385 u16 id = 0; 386 #ifdef CONFIG_SMP 387 id = per_cpu(cpu_llc_id, cpu); 388 #endif 389 return id; 390 } 391 EXPORT_SYMBOL_GPL(amd_get_nb_id); 392 393 u32 amd_get_nodes_per_socket(void) 394 { 395 return nodes_per_socket; 396 } 397 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket); 398 399 static void srat_detect_node(struct cpuinfo_x86 *c) 400 { 401 #ifdef CONFIG_NUMA 402 int cpu = smp_processor_id(); 403 int node; 404 unsigned apicid = c->apicid; 405 406 node = numa_cpu_node(cpu); 407 if (node == NUMA_NO_NODE) 408 node = per_cpu(cpu_llc_id, cpu); 409 410 /* 411 * On multi-fabric platform (e.g. Numascale NumaChip) a 412 * platform-specific handler needs to be called to fixup some 413 * IDs of the CPU. 414 */ 415 if (x86_cpuinit.fixup_cpu_id) 416 x86_cpuinit.fixup_cpu_id(c, node); 417 418 if (!node_online(node)) { 419 /* 420 * Two possibilities here: 421 * 422 * - The CPU is missing memory and no node was created. In 423 * that case try picking one from a nearby CPU. 424 * 425 * - The APIC IDs differ from the HyperTransport node IDs 426 * which the K8 northbridge parsing fills in. Assume 427 * they are all increased by a constant offset, but in 428 * the same order as the HT nodeids. If that doesn't 429 * result in a usable node fall back to the path for the 430 * previous case. 431 * 432 * This workaround operates directly on the mapping between 433 * APIC ID and NUMA node, assuming certain relationship 434 * between APIC ID, HT node ID and NUMA topology. As going 435 * through CPU mapping may alter the outcome, directly 436 * access __apicid_to_node[]. 437 */ 438 int ht_nodeid = c->initial_apicid; 439 440 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 441 node = __apicid_to_node[ht_nodeid]; 442 /* Pick a nearby node */ 443 if (!node_online(node)) 444 node = nearby_node(apicid); 445 } 446 numa_set_node(cpu, node); 447 #endif 448 } 449 450 static void early_init_amd_mc(struct cpuinfo_x86 *c) 451 { 452 #ifdef CONFIG_SMP 453 unsigned bits, ecx; 454 455 /* Multi core CPU? */ 456 if (c->extended_cpuid_level < 0x80000008) 457 return; 458 459 ecx = cpuid_ecx(0x80000008); 460 461 c->x86_max_cores = (ecx & 0xff) + 1; 462 463 /* CPU telling us the core id bits shift? */ 464 bits = (ecx >> 12) & 0xF; 465 466 /* Otherwise recompute */ 467 if (bits == 0) { 468 while ((1 << bits) < c->x86_max_cores) 469 bits++; 470 } 471 472 c->x86_coreid_bits = bits; 473 #endif 474 } 475 476 static void bsp_init_amd(struct cpuinfo_x86 *c) 477 { 478 479 #ifdef CONFIG_X86_64 480 if (c->x86 >= 0xf) { 481 unsigned long long tseg; 482 483 /* 484 * Split up direct mapping around the TSEG SMM area. 485 * Don't do it for gbpages because there seems very little 486 * benefit in doing so. 487 */ 488 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { 489 unsigned long pfn = tseg >> PAGE_SHIFT; 490 491 printk(KERN_DEBUG "tseg: %010llx\n", tseg); 492 if (pfn_range_is_mapped(pfn, pfn + 1)) 493 set_memory_4k((unsigned long)__va(tseg), 1); 494 } 495 } 496 #endif 497 498 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 499 500 if (c->x86 > 0x10 || 501 (c->x86 == 0x10 && c->x86_model >= 0x2)) { 502 u64 val; 503 504 rdmsrl(MSR_K7_HWCR, val); 505 if (!(val & BIT(24))) 506 printk(KERN_WARNING FW_BUG "TSC doesn't count " 507 "with P0 frequency!\n"); 508 } 509 } 510 511 if (c->x86 == 0x15) { 512 unsigned long upperbit; 513 u32 cpuid, assoc; 514 515 cpuid = cpuid_edx(0x80000005); 516 assoc = cpuid >> 16 & 0xff; 517 upperbit = ((cpuid >> 24) << 10) / assoc; 518 519 va_align.mask = (upperbit - 1) & PAGE_MASK; 520 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; 521 522 /* A random value per boot for bit slice [12:upper_bit) */ 523 va_align.bits = get_random_int() & va_align.mask; 524 } 525 526 if (cpu_has(c, X86_FEATURE_MWAITX)) 527 use_mwaitx_delay(); 528 } 529 530 static void early_init_amd(struct cpuinfo_x86 *c) 531 { 532 early_init_amd_mc(c); 533 534 /* 535 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 536 * with P/T states and does not stop in deep C-states 537 */ 538 if (c->x86_power & (1 << 8)) { 539 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 540 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 541 if (!check_tsc_unstable()) 542 set_sched_clock_stable(); 543 } 544 545 #ifdef CONFIG_X86_64 546 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 547 #else 548 /* Set MTRR capability flag if appropriate */ 549 if (c->x86 == 5) 550 if (c->x86_model == 13 || c->x86_model == 9 || 551 (c->x86_model == 8 && c->x86_mask >= 8)) 552 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 553 #endif 554 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 555 /* 556 * ApicID can always be treated as an 8-bit value for AMD APIC versions 557 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we 558 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families 559 * after 16h. 560 */ 561 if (cpu_has_apic && c->x86 > 0x16) { 562 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 563 } else if (cpu_has_apic && c->x86 >= 0xf) { 564 /* check CPU config space for extended APIC ID */ 565 unsigned int val; 566 val = read_pci_config(0, 24, 0, 0x68); 567 if ((val & ((1 << 17) | (1 << 18))) == ((1 << 17) | (1 << 18))) 568 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 569 } 570 #endif 571 572 /* 573 * This is only needed to tell the kernel whether to use VMCALL 574 * and VMMCALL. VMMCALL is never executed except under virt, so 575 * we can set it unconditionally. 576 */ 577 set_cpu_cap(c, X86_FEATURE_VMMCALL); 578 579 /* F16h erratum 793, CVE-2013-6885 */ 580 if (c->x86 == 0x16 && c->x86_model <= 0xf) 581 msr_set_bit(MSR_AMD64_LS_CFG, 15); 582 } 583 584 static const int amd_erratum_383[]; 585 static const int amd_erratum_400[]; 586 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); 587 588 static void init_amd_k8(struct cpuinfo_x86 *c) 589 { 590 u32 level; 591 u64 value; 592 593 /* On C+ stepping K8 rep microcode works well for copy/memset */ 594 level = cpuid_eax(1); 595 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) 596 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 597 598 /* 599 * Some BIOSes incorrectly force this feature, but only K8 revision D 600 * (model = 0x14) and later actually support it. 601 * (AMD Erratum #110, docId: 25759). 602 */ 603 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { 604 clear_cpu_cap(c, X86_FEATURE_LAHF_LM); 605 if (!rdmsrl_amd_safe(0xc001100d, &value)) { 606 value &= ~BIT_64(32); 607 wrmsrl_amd_safe(0xc001100d, value); 608 } 609 } 610 611 if (!c->x86_model_id[0]) 612 strcpy(c->x86_model_id, "Hammer"); 613 614 #ifdef CONFIG_SMP 615 /* 616 * Disable TLB flush filter by setting HWCR.FFDIS on K8 617 * bit 6 of msr C001_0015 618 * 619 * Errata 63 for SH-B3 steppings 620 * Errata 122 for all steppings (F+ have it disabled by default) 621 */ 622 msr_set_bit(MSR_K7_HWCR, 6); 623 #endif 624 } 625 626 static void init_amd_gh(struct cpuinfo_x86 *c) 627 { 628 #ifdef CONFIG_X86_64 629 /* do this for boot cpu */ 630 if (c == &boot_cpu_data) 631 check_enable_amd_mmconf_dmi(); 632 633 fam10h_check_enable_mmcfg(); 634 #endif 635 636 /* 637 * Disable GART TLB Walk Errors on Fam10h. We do this here because this 638 * is always needed when GART is enabled, even in a kernel which has no 639 * MCE support built in. BIOS should disable GartTlbWlk Errors already. 640 * If it doesn't, we do it here as suggested by the BKDG. 641 * 642 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 643 */ 644 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10); 645 646 /* 647 * On family 10h BIOS may not have properly enabled WC+ support, causing 648 * it to be converted to CD memtype. This may result in performance 649 * degradation for certain nested-paging guests. Prevent this conversion 650 * by clearing bit 24 in MSR_AMD64_BU_CFG2. 651 * 652 * NOTE: we want to use the _safe accessors so as not to #GP kvm 653 * guests on older kvm hosts. 654 */ 655 msr_clear_bit(MSR_AMD64_BU_CFG2, 24); 656 657 if (cpu_has_amd_erratum(c, amd_erratum_383)) 658 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH); 659 } 660 661 static void init_amd_bd(struct cpuinfo_x86 *c) 662 { 663 u64 value; 664 665 /* re-enable TopologyExtensions if switched off by BIOS */ 666 if ((c->x86_model >= 0x10) && (c->x86_model <= 0x1f) && 667 !cpu_has(c, X86_FEATURE_TOPOEXT)) { 668 669 if (msr_set_bit(0xc0011005, 54) > 0) { 670 rdmsrl(0xc0011005, value); 671 if (value & BIT_64(54)) { 672 set_cpu_cap(c, X86_FEATURE_TOPOEXT); 673 pr_info(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n"); 674 } 675 } 676 } 677 678 /* 679 * The way access filter has a performance penalty on some workloads. 680 * Disable it on the affected CPUs. 681 */ 682 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) { 683 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) { 684 value |= 0x1E; 685 wrmsrl_safe(MSR_F15H_IC_CFG, value); 686 } 687 } 688 } 689 690 static void init_amd(struct cpuinfo_x86 *c) 691 { 692 u32 dummy; 693 694 early_init_amd(c); 695 696 /* 697 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 698 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 699 */ 700 clear_cpu_cap(c, 0*32+31); 701 702 if (c->x86 >= 0x10) 703 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 704 705 /* get apicid instead of initial apic id from cpuid */ 706 c->apicid = hard_smp_processor_id(); 707 708 /* K6s reports MCEs but don't actually have all the MSRs */ 709 if (c->x86 < 6) 710 clear_cpu_cap(c, X86_FEATURE_MCE); 711 712 switch (c->x86) { 713 case 4: init_amd_k5(c); break; 714 case 5: init_amd_k6(c); break; 715 case 6: init_amd_k7(c); break; 716 case 0xf: init_amd_k8(c); break; 717 case 0x10: init_amd_gh(c); break; 718 case 0x15: init_amd_bd(c); break; 719 } 720 721 /* Enable workaround for FXSAVE leak */ 722 if (c->x86 >= 6) 723 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK); 724 725 cpu_detect_cache_sizes(c); 726 727 /* Multi core CPU? */ 728 if (c->extended_cpuid_level >= 0x80000008) { 729 amd_detect_cmp(c); 730 srat_detect_node(c); 731 } 732 733 #ifdef CONFIG_X86_32 734 detect_ht(c); 735 #endif 736 737 init_amd_cacheinfo(c); 738 739 if (c->x86 >= 0xf) 740 set_cpu_cap(c, X86_FEATURE_K8); 741 742 if (cpu_has_xmm2) { 743 /* MFENCE stops RDTSC speculation */ 744 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); 745 } 746 747 /* 748 * Family 0x12 and above processors have APIC timer 749 * running in deep C states. 750 */ 751 if (c->x86 > 0x11) 752 set_cpu_cap(c, X86_FEATURE_ARAT); 753 754 if (cpu_has_amd_erratum(c, amd_erratum_400)) 755 set_cpu_bug(c, X86_BUG_AMD_APIC_C1E); 756 757 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); 758 759 /* 3DNow or LM implies PREFETCHW */ 760 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH)) 761 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM)) 762 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH); 763 764 /* AMD CPUs don't reset SS attributes on SYSRET */ 765 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); 766 } 767 768 #ifdef CONFIG_X86_32 769 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) 770 { 771 /* AMD errata T13 (order #21922) */ 772 if ((c->x86 == 6)) { 773 /* Duron Rev A0 */ 774 if (c->x86_model == 3 && c->x86_mask == 0) 775 size = 64; 776 /* Tbird rev A1/A2 */ 777 if (c->x86_model == 4 && 778 (c->x86_mask == 0 || c->x86_mask == 1)) 779 size = 256; 780 } 781 return size; 782 } 783 #endif 784 785 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) 786 { 787 u32 ebx, eax, ecx, edx; 788 u16 mask = 0xfff; 789 790 if (c->x86 < 0xf) 791 return; 792 793 if (c->extended_cpuid_level < 0x80000006) 794 return; 795 796 cpuid(0x80000006, &eax, &ebx, &ecx, &edx); 797 798 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask; 799 tlb_lli_4k[ENTRIES] = ebx & mask; 800 801 /* 802 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB 803 * characteristics from the CPUID function 0x80000005 instead. 804 */ 805 if (c->x86 == 0xf) { 806 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 807 mask = 0xff; 808 } 809 810 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 811 if (!((eax >> 16) & mask)) 812 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff; 813 else 814 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask; 815 816 /* a 4M entry uses two 2M entries */ 817 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1; 818 819 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 820 if (!(eax & mask)) { 821 /* Erratum 658 */ 822 if (c->x86 == 0x15 && c->x86_model <= 0x1f) { 823 tlb_lli_2m[ENTRIES] = 1024; 824 } else { 825 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 826 tlb_lli_2m[ENTRIES] = eax & 0xff; 827 } 828 } else 829 tlb_lli_2m[ENTRIES] = eax & mask; 830 831 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; 832 } 833 834 static const struct cpu_dev amd_cpu_dev = { 835 .c_vendor = "AMD", 836 .c_ident = { "AuthenticAMD" }, 837 #ifdef CONFIG_X86_32 838 .legacy_models = { 839 { .family = 4, .model_names = 840 { 841 [3] = "486 DX/2", 842 [7] = "486 DX/2-WB", 843 [8] = "486 DX/4", 844 [9] = "486 DX/4-WB", 845 [14] = "Am5x86-WT", 846 [15] = "Am5x86-WB" 847 } 848 }, 849 }, 850 .legacy_cache_size = amd_size_cache, 851 #endif 852 .c_early_init = early_init_amd, 853 .c_detect_tlb = cpu_detect_tlb_amd, 854 .c_bsp_init = bsp_init_amd, 855 .c_init = init_amd, 856 .c_x86_vendor = X86_VENDOR_AMD, 857 }; 858 859 cpu_dev_register(amd_cpu_dev); 860 861 /* 862 * AMD errata checking 863 * 864 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or 865 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that 866 * have an OSVW id assigned, which it takes as first argument. Both take a 867 * variable number of family-specific model-stepping ranges created by 868 * AMD_MODEL_RANGE(). 869 * 870 * Example: 871 * 872 * const int amd_erratum_319[] = 873 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), 874 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), 875 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); 876 */ 877 878 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } 879 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } 880 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ 881 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) 882 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) 883 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) 884 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) 885 886 static const int amd_erratum_400[] = 887 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), 888 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); 889 890 static const int amd_erratum_383[] = 891 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); 892 893 894 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) 895 { 896 int osvw_id = *erratum++; 897 u32 range; 898 u32 ms; 899 900 if (osvw_id >= 0 && osvw_id < 65536 && 901 cpu_has(cpu, X86_FEATURE_OSVW)) { 902 u64 osvw_len; 903 904 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); 905 if (osvw_id < osvw_len) { 906 u64 osvw_bits; 907 908 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), 909 osvw_bits); 910 return osvw_bits & (1ULL << (osvw_id & 0x3f)); 911 } 912 } 913 914 /* OSVW unavailable or ID unknown, match family-model-stepping range */ 915 ms = (cpu->x86_model << 4) | cpu->x86_mask; 916 while ((range = *erratum++)) 917 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && 918 (ms >= AMD_MODEL_RANGE_START(range)) && 919 (ms <= AMD_MODEL_RANGE_END(range))) 920 return true; 921 922 return false; 923 } 924 925 void set_dr_addr_mask(unsigned long mask, int dr) 926 { 927 if (!boot_cpu_has(X86_FEATURE_BPEXT)) 928 return; 929 930 switch (dr) { 931 case 0: 932 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0); 933 break; 934 case 1: 935 case 2: 936 case 3: 937 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0); 938 break; 939 default: 940 break; 941 } 942 } 943