1 #include <linux/export.h> 2 #include <linux/init.h> 3 #include <linux/bitops.h> 4 #include <linux/elf.h> 5 #include <linux/mm.h> 6 7 #include <linux/io.h> 8 #include <linux/sched.h> 9 #include <asm/processor.h> 10 #include <asm/apic.h> 11 #include <asm/cpu.h> 12 #include <asm/pci-direct.h> 13 14 #ifdef CONFIG_X86_64 15 # include <asm/numa_64.h> 16 # include <asm/mmconfig.h> 17 # include <asm/cacheflush.h> 18 #endif 19 20 #include "cpu.h" 21 22 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) 23 { 24 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 25 u32 gprs[8] = { 0 }; 26 int err; 27 28 WARN_ONCE((c->x86 != 0xf), "%s should only be used on K8!\n", __func__); 29 30 gprs[1] = msr; 31 gprs[7] = 0x9c5a203a; 32 33 err = rdmsr_safe_regs(gprs); 34 35 *p = gprs[0] | ((u64)gprs[2] << 32); 36 37 return err; 38 } 39 40 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) 41 { 42 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 43 u32 gprs[8] = { 0 }; 44 45 WARN_ONCE((c->x86 != 0xf), "%s should only be used on K8!\n", __func__); 46 47 gprs[0] = (u32)val; 48 gprs[1] = msr; 49 gprs[2] = val >> 32; 50 gprs[7] = 0x9c5a203a; 51 52 return wrmsr_safe_regs(gprs); 53 } 54 55 #ifdef CONFIG_X86_32 56 /* 57 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 58 * misexecution of code under Linux. Owners of such processors should 59 * contact AMD for precise details and a CPU swap. 60 * 61 * See http://www.multimania.com/poulot/k6bug.html 62 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" 63 * (Publication # 21266 Issue Date: August 1998) 64 * 65 * The following test is erm.. interesting. AMD neglected to up 66 * the chip setting when fixing the bug but they also tweaked some 67 * performance at the same time.. 68 */ 69 70 extern void vide(void); 71 __asm__(".align 4\nvide: ret"); 72 73 static void __cpuinit init_amd_k5(struct cpuinfo_x86 *c) 74 { 75 /* 76 * General Systems BIOSen alias the cpu frequency registers 77 * of the Elan at 0x000df000. Unfortuantly, one of the Linux 78 * drivers subsequently pokes it, and changes the CPU speed. 79 * Workaround : Remove the unneeded alias. 80 */ 81 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 82 #define CBAR_ENB (0x80000000) 83 #define CBAR_KEY (0X000000CB) 84 if (c->x86_model == 9 || c->x86_model == 10) { 85 if (inl(CBAR) & CBAR_ENB) 86 outl(0 | CBAR_KEY, CBAR); 87 } 88 } 89 90 91 static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c) 92 { 93 u32 l, h; 94 int mbytes = num_physpages >> (20-PAGE_SHIFT); 95 96 if (c->x86_model < 6) { 97 /* Based on AMD doc 20734R - June 2000 */ 98 if (c->x86_model == 0) { 99 clear_cpu_cap(c, X86_FEATURE_APIC); 100 set_cpu_cap(c, X86_FEATURE_PGE); 101 } 102 return; 103 } 104 105 if (c->x86_model == 6 && c->x86_mask == 1) { 106 const int K6_BUG_LOOP = 1000000; 107 int n; 108 void (*f_vide)(void); 109 unsigned long d, d2; 110 111 printk(KERN_INFO "AMD K6 stepping B detected - "); 112 113 /* 114 * It looks like AMD fixed the 2.6.2 bug and improved indirect 115 * calls at the same time. 116 */ 117 118 n = K6_BUG_LOOP; 119 f_vide = vide; 120 rdtscl(d); 121 while (n--) 122 f_vide(); 123 rdtscl(d2); 124 d = d2-d; 125 126 if (d > 20*K6_BUG_LOOP) 127 printk(KERN_CONT 128 "system stability may be impaired when more than 32 MB are used.\n"); 129 else 130 printk(KERN_CONT "probably OK (after B9730xxxx).\n"); 131 } 132 133 /* K6 with old style WHCR */ 134 if (c->x86_model < 8 || 135 (c->x86_model == 8 && c->x86_mask < 8)) { 136 /* We can only write allocate on the low 508Mb */ 137 if (mbytes > 508) 138 mbytes = 508; 139 140 rdmsr(MSR_K6_WHCR, l, h); 141 if ((l&0x0000FFFF) == 0) { 142 unsigned long flags; 143 l = (1<<0)|((mbytes/4)<<1); 144 local_irq_save(flags); 145 wbinvd(); 146 wrmsr(MSR_K6_WHCR, l, h); 147 local_irq_restore(flags); 148 printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n", 149 mbytes); 150 } 151 return; 152 } 153 154 if ((c->x86_model == 8 && c->x86_mask > 7) || 155 c->x86_model == 9 || c->x86_model == 13) { 156 /* The more serious chips .. */ 157 158 if (mbytes > 4092) 159 mbytes = 4092; 160 161 rdmsr(MSR_K6_WHCR, l, h); 162 if ((l&0xFFFF0000) == 0) { 163 unsigned long flags; 164 l = ((mbytes>>2)<<22)|(1<<16); 165 local_irq_save(flags); 166 wbinvd(); 167 wrmsr(MSR_K6_WHCR, l, h); 168 local_irq_restore(flags); 169 printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n", 170 mbytes); 171 } 172 173 return; 174 } 175 176 if (c->x86_model == 10) { 177 /* AMD Geode LX is model 10 */ 178 /* placeholder for any needed mods */ 179 return; 180 } 181 } 182 183 static void __cpuinit amd_k7_smp_check(struct cpuinfo_x86 *c) 184 { 185 /* calling is from identify_secondary_cpu() ? */ 186 if (!c->cpu_index) 187 return; 188 189 /* 190 * Certain Athlons might work (for various values of 'work') in SMP 191 * but they are not certified as MP capable. 192 */ 193 /* Athlon 660/661 is valid. */ 194 if ((c->x86_model == 6) && ((c->x86_mask == 0) || 195 (c->x86_mask == 1))) 196 goto valid_k7; 197 198 /* Duron 670 is valid */ 199 if ((c->x86_model == 7) && (c->x86_mask == 0)) 200 goto valid_k7; 201 202 /* 203 * Athlon 662, Duron 671, and Athlon >model 7 have capability 204 * bit. It's worth noting that the A5 stepping (662) of some 205 * Athlon XP's have the MP bit set. 206 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for 207 * more. 208 */ 209 if (((c->x86_model == 6) && (c->x86_mask >= 2)) || 210 ((c->x86_model == 7) && (c->x86_mask >= 1)) || 211 (c->x86_model > 7)) 212 if (cpu_has_mp) 213 goto valid_k7; 214 215 /* If we get here, not a certified SMP capable AMD system. */ 216 217 /* 218 * Don't taint if we are running SMP kernel on a single non-MP 219 * approved Athlon 220 */ 221 WARN_ONCE(1, "WARNING: This combination of AMD" 222 " processors is not suitable for SMP.\n"); 223 if (!test_taint(TAINT_UNSAFE_SMP)) 224 add_taint(TAINT_UNSAFE_SMP); 225 226 valid_k7: 227 ; 228 } 229 230 static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c) 231 { 232 u32 l, h; 233 234 /* 235 * Bit 15 of Athlon specific MSR 15, needs to be 0 236 * to enable SSE on Palomino/Morgan/Barton CPU's. 237 * If the BIOS didn't enable it already, enable it here. 238 */ 239 if (c->x86_model >= 6 && c->x86_model <= 10) { 240 if (!cpu_has(c, X86_FEATURE_XMM)) { 241 printk(KERN_INFO "Enabling disabled K7/SSE Support.\n"); 242 rdmsr(MSR_K7_HWCR, l, h); 243 l &= ~0x00008000; 244 wrmsr(MSR_K7_HWCR, l, h); 245 set_cpu_cap(c, X86_FEATURE_XMM); 246 } 247 } 248 249 /* 250 * It's been determined by AMD that Athlons since model 8 stepping 1 251 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 252 * As per AMD technical note 27212 0.2 253 */ 254 if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) { 255 rdmsr(MSR_K7_CLK_CTL, l, h); 256 if ((l & 0xfff00000) != 0x20000000) { 257 printk(KERN_INFO 258 "CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", 259 l, ((l & 0x000fffff)|0x20000000)); 260 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 261 } 262 } 263 264 set_cpu_cap(c, X86_FEATURE_K7); 265 266 amd_k7_smp_check(c); 267 } 268 #endif 269 270 #ifdef CONFIG_NUMA 271 /* 272 * To workaround broken NUMA config. Read the comment in 273 * srat_detect_node(). 274 */ 275 static int __cpuinit nearby_node(int apicid) 276 { 277 int i, node; 278 279 for (i = apicid - 1; i >= 0; i--) { 280 node = __apicid_to_node[i]; 281 if (node != NUMA_NO_NODE && node_online(node)) 282 return node; 283 } 284 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 285 node = __apicid_to_node[i]; 286 if (node != NUMA_NO_NODE && node_online(node)) 287 return node; 288 } 289 return first_node(node_online_map); /* Shouldn't happen */ 290 } 291 #endif 292 293 /* 294 * Fixup core topology information for 295 * (1) AMD multi-node processors 296 * Assumption: Number of cores in each internal node is the same. 297 * (2) AMD processors supporting compute units 298 */ 299 #ifdef CONFIG_X86_HT 300 static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c) 301 { 302 u32 nodes, cores_per_cu = 1; 303 u8 node_id; 304 int cpu = smp_processor_id(); 305 306 /* get information required for multi-node processors */ 307 if (cpu_has_topoext) { 308 u32 eax, ebx, ecx, edx; 309 310 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); 311 nodes = ((ecx >> 8) & 7) + 1; 312 node_id = ecx & 7; 313 314 /* get compute unit information */ 315 smp_num_siblings = ((ebx >> 8) & 3) + 1; 316 c->compute_unit_id = ebx & 0xff; 317 cores_per_cu += ((ebx >> 8) & 3); 318 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { 319 u64 value; 320 321 rdmsrl(MSR_FAM10H_NODE_ID, value); 322 nodes = ((value >> 3) & 7) + 1; 323 node_id = value & 7; 324 } else 325 return; 326 327 /* fixup multi-node processor information */ 328 if (nodes > 1) { 329 u32 cores_per_node; 330 u32 cus_per_node; 331 332 set_cpu_cap(c, X86_FEATURE_AMD_DCM); 333 cores_per_node = c->x86_max_cores / nodes; 334 cus_per_node = cores_per_node / cores_per_cu; 335 336 /* store NodeID, use llc_shared_map to store sibling info */ 337 per_cpu(cpu_llc_id, cpu) = node_id; 338 339 /* core id has to be in the [0 .. cores_per_node - 1] range */ 340 c->cpu_core_id %= cores_per_node; 341 c->compute_unit_id %= cus_per_node; 342 } 343 } 344 #endif 345 346 /* 347 * On a AMD dual core setup the lower bits of the APIC id distingush the cores. 348 * Assumes number of cores is a power of two. 349 */ 350 static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c) 351 { 352 #ifdef CONFIG_X86_HT 353 unsigned bits; 354 int cpu = smp_processor_id(); 355 356 bits = c->x86_coreid_bits; 357 /* Low order bits define the core id (index of core in socket) */ 358 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); 359 /* Convert the initial APIC ID into the socket ID */ 360 c->phys_proc_id = c->initial_apicid >> bits; 361 /* use socket ID also for last level cache */ 362 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; 363 amd_get_topology(c); 364 #endif 365 } 366 367 int amd_get_nb_id(int cpu) 368 { 369 int id = 0; 370 #ifdef CONFIG_SMP 371 id = per_cpu(cpu_llc_id, cpu); 372 #endif 373 return id; 374 } 375 EXPORT_SYMBOL_GPL(amd_get_nb_id); 376 377 static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c) 378 { 379 #ifdef CONFIG_NUMA 380 int cpu = smp_processor_id(); 381 int node; 382 unsigned apicid = c->apicid; 383 384 node = numa_cpu_node(cpu); 385 if (node == NUMA_NO_NODE) 386 node = per_cpu(cpu_llc_id, cpu); 387 388 /* 389 * On multi-fabric platform (e.g. Numascale NumaChip) a 390 * platform-specific handler needs to be called to fixup some 391 * IDs of the CPU. 392 */ 393 if (x86_cpuinit.fixup_cpu_id) 394 x86_cpuinit.fixup_cpu_id(c, node); 395 396 if (!node_online(node)) { 397 /* 398 * Two possibilities here: 399 * 400 * - The CPU is missing memory and no node was created. In 401 * that case try picking one from a nearby CPU. 402 * 403 * - The APIC IDs differ from the HyperTransport node IDs 404 * which the K8 northbridge parsing fills in. Assume 405 * they are all increased by a constant offset, but in 406 * the same order as the HT nodeids. If that doesn't 407 * result in a usable node fall back to the path for the 408 * previous case. 409 * 410 * This workaround operates directly on the mapping between 411 * APIC ID and NUMA node, assuming certain relationship 412 * between APIC ID, HT node ID and NUMA topology. As going 413 * through CPU mapping may alter the outcome, directly 414 * access __apicid_to_node[]. 415 */ 416 int ht_nodeid = c->initial_apicid; 417 418 if (ht_nodeid >= 0 && 419 __apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 420 node = __apicid_to_node[ht_nodeid]; 421 /* Pick a nearby node */ 422 if (!node_online(node)) 423 node = nearby_node(apicid); 424 } 425 numa_set_node(cpu, node); 426 #endif 427 } 428 429 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c) 430 { 431 #ifdef CONFIG_X86_HT 432 unsigned bits, ecx; 433 434 /* Multi core CPU? */ 435 if (c->extended_cpuid_level < 0x80000008) 436 return; 437 438 ecx = cpuid_ecx(0x80000008); 439 440 c->x86_max_cores = (ecx & 0xff) + 1; 441 442 /* CPU telling us the core id bits shift? */ 443 bits = (ecx >> 12) & 0xF; 444 445 /* Otherwise recompute */ 446 if (bits == 0) { 447 while ((1 << bits) < c->x86_max_cores) 448 bits++; 449 } 450 451 c->x86_coreid_bits = bits; 452 #endif 453 } 454 455 static void __cpuinit bsp_init_amd(struct cpuinfo_x86 *c) 456 { 457 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 458 459 if (c->x86 > 0x10 || 460 (c->x86 == 0x10 && c->x86_model >= 0x2)) { 461 u64 val; 462 463 rdmsrl(MSR_K7_HWCR, val); 464 if (!(val & BIT(24))) 465 printk(KERN_WARNING FW_BUG "TSC doesn't count " 466 "with P0 frequency!\n"); 467 } 468 } 469 470 if (c->x86 == 0x15) { 471 unsigned long upperbit; 472 u32 cpuid, assoc; 473 474 cpuid = cpuid_edx(0x80000005); 475 assoc = cpuid >> 16 & 0xff; 476 upperbit = ((cpuid >> 24) << 10) / assoc; 477 478 va_align.mask = (upperbit - 1) & PAGE_MASK; 479 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; 480 } 481 } 482 483 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c) 484 { 485 early_init_amd_mc(c); 486 487 /* 488 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 489 * with P/T states and does not stop in deep C-states 490 */ 491 if (c->x86_power & (1 << 8)) { 492 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 493 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 494 if (!check_tsc_unstable()) 495 sched_clock_stable = 1; 496 } 497 498 #ifdef CONFIG_X86_64 499 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 500 #else 501 /* Set MTRR capability flag if appropriate */ 502 if (c->x86 == 5) 503 if (c->x86_model == 13 || c->x86_model == 9 || 504 (c->x86_model == 8 && c->x86_mask >= 8)) 505 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 506 #endif 507 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 508 /* check CPU config space for extended APIC ID */ 509 if (cpu_has_apic && c->x86 >= 0xf) { 510 unsigned int val; 511 val = read_pci_config(0, 24, 0, 0x68); 512 if ((val & ((1 << 17) | (1 << 18))) == ((1 << 17) | (1 << 18))) 513 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 514 } 515 #endif 516 } 517 518 static void __cpuinit init_amd(struct cpuinfo_x86 *c) 519 { 520 u32 dummy; 521 522 #ifdef CONFIG_SMP 523 unsigned long long value; 524 525 /* 526 * Disable TLB flush filter by setting HWCR.FFDIS on K8 527 * bit 6 of msr C001_0015 528 * 529 * Errata 63 for SH-B3 steppings 530 * Errata 122 for all steppings (F+ have it disabled by default) 531 */ 532 if (c->x86 == 0xf) { 533 rdmsrl(MSR_K7_HWCR, value); 534 value |= 1 << 6; 535 wrmsrl(MSR_K7_HWCR, value); 536 } 537 #endif 538 539 early_init_amd(c); 540 541 /* 542 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 543 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 544 */ 545 clear_cpu_cap(c, 0*32+31); 546 547 #ifdef CONFIG_X86_64 548 /* On C+ stepping K8 rep microcode works well for copy/memset */ 549 if (c->x86 == 0xf) { 550 u32 level; 551 552 level = cpuid_eax(1); 553 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) 554 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 555 556 /* 557 * Some BIOSes incorrectly force this feature, but only K8 558 * revision D (model = 0x14) and later actually support it. 559 * (AMD Erratum #110, docId: 25759). 560 */ 561 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { 562 u64 val; 563 564 clear_cpu_cap(c, X86_FEATURE_LAHF_LM); 565 if (!rdmsrl_amd_safe(0xc001100d, &val)) { 566 val &= ~(1ULL << 32); 567 wrmsrl_amd_safe(0xc001100d, val); 568 } 569 } 570 571 } 572 if (c->x86 >= 0x10) 573 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 574 575 /* get apicid instead of initial apic id from cpuid */ 576 c->apicid = hard_smp_processor_id(); 577 #else 578 579 /* 580 * FIXME: We should handle the K5 here. Set up the write 581 * range and also turn on MSR 83 bits 4 and 31 (write alloc, 582 * no bus pipeline) 583 */ 584 585 switch (c->x86) { 586 case 4: 587 init_amd_k5(c); 588 break; 589 case 5: 590 init_amd_k6(c); 591 break; 592 case 6: /* An Athlon/Duron */ 593 init_amd_k7(c); 594 break; 595 } 596 597 /* K6s reports MCEs but don't actually have all the MSRs */ 598 if (c->x86 < 6) 599 clear_cpu_cap(c, X86_FEATURE_MCE); 600 #endif 601 602 /* Enable workaround for FXSAVE leak */ 603 if (c->x86 >= 6) 604 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK); 605 606 if (!c->x86_model_id[0]) { 607 switch (c->x86) { 608 case 0xf: 609 /* Should distinguish Models here, but this is only 610 a fallback anyways. */ 611 strcpy(c->x86_model_id, "Hammer"); 612 break; 613 } 614 } 615 616 /* re-enable TopologyExtensions if switched off by BIOS */ 617 if ((c->x86 == 0x15) && 618 (c->x86_model >= 0x10) && (c->x86_model <= 0x1f) && 619 !cpu_has(c, X86_FEATURE_TOPOEXT)) { 620 u64 val; 621 622 if (!rdmsrl_safe(0xc0011005, &val)) { 623 val |= 1ULL << 54; 624 wrmsrl_safe(0xc0011005, val); 625 rdmsrl(0xc0011005, val); 626 if (val & (1ULL << 54)) { 627 set_cpu_cap(c, X86_FEATURE_TOPOEXT); 628 printk(KERN_INFO FW_INFO "CPU: Re-enabling " 629 "disabled Topology Extensions Support\n"); 630 } 631 } 632 } 633 634 /* 635 * The way access filter has a performance penalty on some workloads. 636 * Disable it on the affected CPUs. 637 */ 638 if ((c->x86 == 0x15) && 639 (c->x86_model >= 0x02) && (c->x86_model < 0x20)) { 640 u64 val; 641 642 if (!rdmsrl_safe(0xc0011021, &val) && !(val & 0x1E)) { 643 val |= 0x1E; 644 wrmsrl_safe(0xc0011021, val); 645 } 646 } 647 648 cpu_detect_cache_sizes(c); 649 650 /* Multi core CPU? */ 651 if (c->extended_cpuid_level >= 0x80000008) { 652 amd_detect_cmp(c); 653 srat_detect_node(c); 654 } 655 656 #ifdef CONFIG_X86_32 657 detect_ht(c); 658 #endif 659 660 init_amd_cacheinfo(c); 661 662 if (c->x86 >= 0xf) 663 set_cpu_cap(c, X86_FEATURE_K8); 664 665 if (cpu_has_xmm2) { 666 /* MFENCE stops RDTSC speculation */ 667 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); 668 } 669 670 #ifdef CONFIG_X86_64 671 if (c->x86 == 0x10) { 672 /* do this for boot cpu */ 673 if (c == &boot_cpu_data) 674 check_enable_amd_mmconf_dmi(); 675 676 fam10h_check_enable_mmcfg(); 677 } 678 679 if (c == &boot_cpu_data && c->x86 >= 0xf) { 680 unsigned long long tseg; 681 682 /* 683 * Split up direct mapping around the TSEG SMM area. 684 * Don't do it for gbpages because there seems very little 685 * benefit in doing so. 686 */ 687 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { 688 printk(KERN_DEBUG "tseg: %010llx\n", tseg); 689 if ((tseg>>PMD_SHIFT) < 690 (max_low_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) || 691 ((tseg>>PMD_SHIFT) < 692 (max_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) && 693 (tseg>>PMD_SHIFT) >= (1ULL<<(32 - PMD_SHIFT)))) 694 set_memory_4k((unsigned long)__va(tseg), 1); 695 } 696 } 697 #endif 698 699 /* 700 * Family 0x12 and above processors have APIC timer 701 * running in deep C states. 702 */ 703 if (c->x86 > 0x11) 704 set_cpu_cap(c, X86_FEATURE_ARAT); 705 706 /* 707 * Disable GART TLB Walk Errors on Fam10h. We do this here 708 * because this is always needed when GART is enabled, even in a 709 * kernel which has no MCE support built in. 710 */ 711 if (c->x86 == 0x10) { 712 /* 713 * BIOS should disable GartTlbWlk Errors themself. If 714 * it doesn't do it here as suggested by the BKDG. 715 * 716 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 717 */ 718 u64 mask; 719 int err; 720 721 err = rdmsrl_safe(MSR_AMD64_MCx_MASK(4), &mask); 722 if (err == 0) { 723 mask |= (1 << 10); 724 wrmsrl_safe(MSR_AMD64_MCx_MASK(4), mask); 725 } 726 } 727 728 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); 729 } 730 731 #ifdef CONFIG_X86_32 732 static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, 733 unsigned int size) 734 { 735 /* AMD errata T13 (order #21922) */ 736 if ((c->x86 == 6)) { 737 /* Duron Rev A0 */ 738 if (c->x86_model == 3 && c->x86_mask == 0) 739 size = 64; 740 /* Tbird rev A1/A2 */ 741 if (c->x86_model == 4 && 742 (c->x86_mask == 0 || c->x86_mask == 1)) 743 size = 256; 744 } 745 return size; 746 } 747 #endif 748 749 static void __cpuinit cpu_set_tlb_flushall_shift(struct cpuinfo_x86 *c) 750 { 751 tlb_flushall_shift = 5; 752 753 if (c->x86 <= 0x11) 754 tlb_flushall_shift = 4; 755 } 756 757 static void __cpuinit cpu_detect_tlb_amd(struct cpuinfo_x86 *c) 758 { 759 u32 ebx, eax, ecx, edx; 760 u16 mask = 0xfff; 761 762 if (c->x86 < 0xf) 763 return; 764 765 if (c->extended_cpuid_level < 0x80000006) 766 return; 767 768 cpuid(0x80000006, &eax, &ebx, &ecx, &edx); 769 770 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask; 771 tlb_lli_4k[ENTRIES] = ebx & mask; 772 773 /* 774 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB 775 * characteristics from the CPUID function 0x80000005 instead. 776 */ 777 if (c->x86 == 0xf) { 778 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 779 mask = 0xff; 780 } 781 782 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 783 if (!((eax >> 16) & mask)) { 784 u32 a, b, c, d; 785 786 cpuid(0x80000005, &a, &b, &c, &d); 787 tlb_lld_2m[ENTRIES] = (a >> 16) & 0xff; 788 } else { 789 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask; 790 } 791 792 /* a 4M entry uses two 2M entries */ 793 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1; 794 795 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 796 if (!(eax & mask)) { 797 /* Erratum 658 */ 798 if (c->x86 == 0x15 && c->x86_model <= 0x1f) { 799 tlb_lli_2m[ENTRIES] = 1024; 800 } else { 801 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 802 tlb_lli_2m[ENTRIES] = eax & 0xff; 803 } 804 } else 805 tlb_lli_2m[ENTRIES] = eax & mask; 806 807 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; 808 809 cpu_set_tlb_flushall_shift(c); 810 } 811 812 static const struct cpu_dev __cpuinitconst amd_cpu_dev = { 813 .c_vendor = "AMD", 814 .c_ident = { "AuthenticAMD" }, 815 #ifdef CONFIG_X86_32 816 .c_models = { 817 { .vendor = X86_VENDOR_AMD, .family = 4, .model_names = 818 { 819 [3] = "486 DX/2", 820 [7] = "486 DX/2-WB", 821 [8] = "486 DX/4", 822 [9] = "486 DX/4-WB", 823 [14] = "Am5x86-WT", 824 [15] = "Am5x86-WB" 825 } 826 }, 827 }, 828 .c_size_cache = amd_size_cache, 829 #endif 830 .c_early_init = early_init_amd, 831 .c_detect_tlb = cpu_detect_tlb_amd, 832 .c_bsp_init = bsp_init_amd, 833 .c_init = init_amd, 834 .c_x86_vendor = X86_VENDOR_AMD, 835 }; 836 837 cpu_dev_register(amd_cpu_dev); 838 839 /* 840 * AMD errata checking 841 * 842 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or 843 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that 844 * have an OSVW id assigned, which it takes as first argument. Both take a 845 * variable number of family-specific model-stepping ranges created by 846 * AMD_MODEL_RANGE(). Each erratum also has to be declared as extern const 847 * int[] in arch/x86/include/asm/processor.h. 848 * 849 * Example: 850 * 851 * const int amd_erratum_319[] = 852 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), 853 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), 854 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); 855 */ 856 857 const int amd_erratum_400[] = 858 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), 859 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); 860 EXPORT_SYMBOL_GPL(amd_erratum_400); 861 862 const int amd_erratum_383[] = 863 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); 864 EXPORT_SYMBOL_GPL(amd_erratum_383); 865 866 bool cpu_has_amd_erratum(const int *erratum) 867 { 868 struct cpuinfo_x86 *cpu = __this_cpu_ptr(&cpu_info); 869 int osvw_id = *erratum++; 870 u32 range; 871 u32 ms; 872 873 /* 874 * If called early enough that current_cpu_data hasn't been initialized 875 * yet, fall back to boot_cpu_data. 876 */ 877 if (cpu->x86 == 0) 878 cpu = &boot_cpu_data; 879 880 if (cpu->x86_vendor != X86_VENDOR_AMD) 881 return false; 882 883 if (osvw_id >= 0 && osvw_id < 65536 && 884 cpu_has(cpu, X86_FEATURE_OSVW)) { 885 u64 osvw_len; 886 887 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); 888 if (osvw_id < osvw_len) { 889 u64 osvw_bits; 890 891 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), 892 osvw_bits); 893 return osvw_bits & (1ULL << (osvw_id & 0x3f)); 894 } 895 } 896 897 /* OSVW unavailable or ID unknown, match family-model-stepping range */ 898 ms = (cpu->x86_model << 4) | cpu->x86_mask; 899 while ((range = *erratum++)) 900 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && 901 (ms >= AMD_MODEL_RANGE_START(range)) && 902 (ms <= AMD_MODEL_RANGE_END(range))) 903 return true; 904 905 return false; 906 } 907 908 EXPORT_SYMBOL_GPL(cpu_has_amd_erratum); 909