1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * SGI UV APIC functions (note: not an Intel compatible APIC) 7 * 8 * (C) Copyright 2020 Hewlett Packard Enterprise Development LP 9 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved. 10 */ 11 #include <linux/crash_dump.h> 12 #include <linux/cpuhotplug.h> 13 #include <linux/cpumask.h> 14 #include <linux/proc_fs.h> 15 #include <linux/memory.h> 16 #include <linux/export.h> 17 #include <linux/pci.h> 18 #include <linux/acpi.h> 19 #include <linux/efi.h> 20 21 #include <asm/e820/api.h> 22 #include <asm/uv/uv_mmrs.h> 23 #include <asm/uv/uv_hub.h> 24 #include <asm/uv/bios.h> 25 #include <asm/uv/uv.h> 26 #include <asm/apic.h> 27 28 #include "local.h" 29 30 static enum uv_system_type uv_system_type; 31 static int uv_hubbed_system; 32 static int uv_hubless_system; 33 static u64 gru_start_paddr, gru_end_paddr; 34 static union uvh_apicid uvh_apicid; 35 static int uv_node_id; 36 37 /* Unpack AT/OEM/TABLE ID's to be NULL terminated strings */ 38 static u8 uv_archtype[UV_AT_SIZE + 1]; 39 static u8 oem_id[ACPI_OEM_ID_SIZE + 1]; 40 static u8 oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1]; 41 42 /* Information derived from CPUID and some UV MMRs */ 43 static struct { 44 unsigned int apicid_shift; 45 unsigned int apicid_mask; 46 unsigned int socketid_shift; /* aka pnode_shift for UV2/3 */ 47 unsigned int pnode_mask; 48 unsigned int nasid_shift; 49 unsigned int gpa_shift; 50 unsigned int gnode_shift; 51 unsigned int m_skt; 52 unsigned int n_skt; 53 } uv_cpuid; 54 55 static int uv_min_hub_revision_id; 56 57 static struct apic apic_x2apic_uv_x; 58 static struct uv_hub_info_s uv_hub_info_node0; 59 60 /* Set this to use hardware error handler instead of kernel panic: */ 61 static int disable_uv_undefined_panic = 1; 62 63 unsigned long uv_undefined(char *str) 64 { 65 if (likely(!disable_uv_undefined_panic)) 66 panic("UV: error: undefined MMR: %s\n", str); 67 else 68 pr_crit("UV: error: undefined MMR: %s\n", str); 69 70 /* Cause a machine fault: */ 71 return ~0ul; 72 } 73 EXPORT_SYMBOL(uv_undefined); 74 75 static unsigned long __init uv_early_read_mmr(unsigned long addr) 76 { 77 unsigned long val, *mmr; 78 79 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr)); 80 val = *mmr; 81 early_iounmap(mmr, sizeof(*mmr)); 82 83 return val; 84 } 85 86 static inline bool is_GRU_range(u64 start, u64 end) 87 { 88 if (!gru_start_paddr) 89 return false; 90 91 return start >= gru_start_paddr && end <= gru_end_paddr; 92 } 93 94 static bool uv_is_untracked_pat_range(u64 start, u64 end) 95 { 96 return is_ISA_range(start, end) || is_GRU_range(start, end); 97 } 98 99 static void __init early_get_pnodeid(void) 100 { 101 int pnode; 102 103 uv_cpuid.m_skt = 0; 104 if (UVH_RH10_GAM_ADDR_MAP_CONFIG) { 105 union uvh_rh10_gam_addr_map_config_u m_n_config; 106 107 m_n_config.v = uv_early_read_mmr(UVH_RH10_GAM_ADDR_MAP_CONFIG); 108 uv_cpuid.n_skt = m_n_config.s.n_skt; 109 uv_cpuid.nasid_shift = 0; 110 } else if (UVH_RH_GAM_ADDR_MAP_CONFIG) { 111 union uvh_rh_gam_addr_map_config_u m_n_config; 112 113 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_ADDR_MAP_CONFIG); 114 uv_cpuid.n_skt = m_n_config.s.n_skt; 115 if (is_uv(UV3)) 116 uv_cpuid.m_skt = m_n_config.s3.m_skt; 117 if (is_uv(UV2)) 118 uv_cpuid.m_skt = m_n_config.s2.m_skt; 119 uv_cpuid.nasid_shift = 1; 120 } else { 121 unsigned long GAM_ADDR_MAP_CONFIG = 0; 122 123 WARN(GAM_ADDR_MAP_CONFIG == 0, 124 "UV: WARN: GAM_ADDR_MAP_CONFIG is not available\n"); 125 uv_cpuid.n_skt = 0; 126 uv_cpuid.nasid_shift = 0; 127 } 128 129 if (is_uv(UV4|UVY)) 130 uv_cpuid.gnode_shift = 2; /* min partition is 4 sockets */ 131 132 uv_cpuid.pnode_mask = (1 << uv_cpuid.n_skt) - 1; 133 pnode = (uv_node_id >> uv_cpuid.nasid_shift) & uv_cpuid.pnode_mask; 134 uv_cpuid.gpa_shift = 46; /* Default unless changed */ 135 136 pr_info("UV: n_skt:%d pnmsk:%x pn:%x\n", 137 uv_cpuid.n_skt, uv_cpuid.pnode_mask, pnode); 138 } 139 140 /* Running on a UV Hubbed system, determine which UV Hub Type it is */ 141 static int __init early_set_hub_type(void) 142 { 143 union uvh_node_id_u node_id; 144 145 /* 146 * The NODE_ID MMR is always at offset 0. 147 * Contains the chip part # + revision. 148 * Node_id field started with 15 bits, 149 * ... now 7 but upper 8 are masked to 0. 150 * All blades/nodes have the same part # and hub revision. 151 */ 152 node_id.v = uv_early_read_mmr(UVH_NODE_ID); 153 uv_node_id = node_id.sx.node_id; 154 155 switch (node_id.s.part_number) { 156 157 case UV5_HUB_PART_NUMBER: 158 uv_min_hub_revision_id = node_id.s.revision 159 + UV5_HUB_REVISION_BASE; 160 uv_hub_type_set(UV5); 161 break; 162 163 /* UV4/4A only have a revision difference */ 164 case UV4_HUB_PART_NUMBER: 165 uv_min_hub_revision_id = node_id.s.revision 166 + UV4_HUB_REVISION_BASE - 1; 167 uv_hub_type_set(UV4); 168 if (uv_min_hub_revision_id == UV4A_HUB_REVISION_BASE) 169 uv_hub_type_set(UV4|UV4A); 170 break; 171 172 case UV3_HUB_PART_NUMBER: 173 case UV3_HUB_PART_NUMBER_X: 174 uv_min_hub_revision_id = node_id.s.revision 175 + UV3_HUB_REVISION_BASE; 176 uv_hub_type_set(UV3); 177 break; 178 179 case UV2_HUB_PART_NUMBER: 180 case UV2_HUB_PART_NUMBER_X: 181 uv_min_hub_revision_id = node_id.s.revision 182 + UV2_HUB_REVISION_BASE - 1; 183 uv_hub_type_set(UV2); 184 break; 185 186 default: 187 return 0; 188 } 189 190 pr_info("UV: part#:%x rev:%d rev_id:%d UVtype:0x%x\n", 191 node_id.s.part_number, node_id.s.revision, 192 uv_min_hub_revision_id, is_uv(~0)); 193 194 return 1; 195 } 196 197 static void __init uv_tsc_check_sync(void) 198 { 199 u64 mmr; 200 int sync_state; 201 int mmr_shift; 202 char *state; 203 204 /* UV5 guarantees synced TSCs; do not zero TSC_ADJUST */ 205 if (!is_uv(UV2|UV3|UV4)) { 206 mark_tsc_async_resets("UV5+"); 207 return; 208 } 209 210 /* UV2,3,4, UV BIOS TSC sync state available */ 211 mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR); 212 mmr_shift = 213 is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT; 214 sync_state = (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK; 215 216 /* Check if TSC is valid for all sockets */ 217 switch (sync_state) { 218 case UVH_TSC_SYNC_VALID: 219 state = "in sync"; 220 mark_tsc_async_resets("UV BIOS"); 221 break; 222 223 /* If BIOS state unknown, don't do anything */ 224 case UVH_TSC_SYNC_UNKNOWN: 225 state = "unknown"; 226 break; 227 228 /* Otherwise, BIOS indicates problem with TSC */ 229 default: 230 state = "unstable"; 231 mark_tsc_unstable("UV BIOS"); 232 break; 233 } 234 pr_info("UV: TSC sync state from BIOS:0%d(%s)\n", sync_state, state); 235 } 236 237 /* Selector for (4|4A|5) structs */ 238 #define uvxy_field(sname, field, undef) ( \ 239 is_uv(UV4A) ? sname.s4a.field : \ 240 is_uv(UV4) ? sname.s4.field : \ 241 is_uv(UV3) ? sname.s3.field : \ 242 undef) 243 244 static void __init early_get_apic_socketid_shift(void) 245 { 246 unsigned int sid_shift = topology_get_domain_shift(TOPO_PKG_DOMAIN); 247 248 if (is_uv2_hub() || is_uv3_hub()) 249 uvh_apicid.v = uv_early_read_mmr(UVH_APICID); 250 251 if (sid_shift) { 252 uv_cpuid.apicid_shift = 0; 253 uv_cpuid.apicid_mask = (~(-1 << sid_shift)); 254 uv_cpuid.socketid_shift = sid_shift; 255 } else { 256 pr_info("UV: CPU does not have valid CPUID.11\n"); 257 } 258 259 pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, uv_cpuid.apicid_mask); 260 pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shift, uv_cpuid.pnode_mask); 261 } 262 263 static void __init uv_stringify(int len, char *to, char *from) 264 { 265 strscpy(to, from, len); 266 267 /* Trim trailing spaces */ 268 (void)strim(to); 269 } 270 271 /* Find UV arch type entry in UVsystab */ 272 static unsigned long __init early_find_archtype(struct uv_systab *st) 273 { 274 int i; 275 276 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) { 277 unsigned long ptr = st->entry[i].offset; 278 279 if (!ptr) 280 continue; 281 ptr += (unsigned long)st; 282 if (st->entry[i].type == UV_SYSTAB_TYPE_ARCH_TYPE) 283 return ptr; 284 } 285 return 0; 286 } 287 288 /* Validate UV arch type field in UVsystab */ 289 static int __init decode_arch_type(unsigned long ptr) 290 { 291 struct uv_arch_type_entry *uv_ate = (struct uv_arch_type_entry *)ptr; 292 int n = strlen(uv_ate->archtype); 293 294 if (n > 0 && n < sizeof(uv_ate->archtype)) { 295 pr_info("UV: UVarchtype received from BIOS\n"); 296 uv_stringify(sizeof(uv_archtype), uv_archtype, uv_ate->archtype); 297 return 1; 298 } 299 return 0; 300 } 301 302 /* Determine if UV arch type entry might exist in UVsystab */ 303 static int __init early_get_arch_type(void) 304 { 305 unsigned long uvst_physaddr, uvst_size, ptr; 306 struct uv_systab *st; 307 u32 rev; 308 int ret; 309 310 uvst_physaddr = get_uv_systab_phys(0); 311 if (!uvst_physaddr) 312 return 0; 313 314 st = early_memremap_ro(uvst_physaddr, sizeof(struct uv_systab)); 315 if (!st) { 316 pr_err("UV: Cannot access UVsystab, remap failed\n"); 317 return 0; 318 } 319 320 rev = st->revision; 321 if (rev < UV_SYSTAB_VERSION_UV5) { 322 early_memunmap(st, sizeof(struct uv_systab)); 323 return 0; 324 } 325 326 uvst_size = st->size; 327 early_memunmap(st, sizeof(struct uv_systab)); 328 st = early_memremap_ro(uvst_physaddr, uvst_size); 329 if (!st) { 330 pr_err("UV: Cannot access UVarchtype, remap failed\n"); 331 return 0; 332 } 333 334 ptr = early_find_archtype(st); 335 if (!ptr) { 336 early_memunmap(st, uvst_size); 337 return 0; 338 } 339 340 ret = decode_arch_type(ptr); 341 early_memunmap(st, uvst_size); 342 return ret; 343 } 344 345 /* UV system found, check which APIC MODE BIOS already selected */ 346 static void __init early_set_apic_mode(void) 347 { 348 if (x2apic_enabled()) 349 uv_system_type = UV_X2APIC; 350 else 351 uv_system_type = UV_LEGACY_APIC; 352 } 353 354 static int __init uv_set_system_type(char *_oem_id, char *_oem_table_id) 355 { 356 /* Save OEM_ID passed from ACPI MADT */ 357 uv_stringify(sizeof(oem_id), oem_id, _oem_id); 358 359 /* Check if BIOS sent us a UVarchtype */ 360 if (!early_get_arch_type()) 361 362 /* If not use OEM ID for UVarchtype */ 363 uv_stringify(sizeof(uv_archtype), uv_archtype, oem_id); 364 365 /* Check if not hubbed */ 366 if (strncmp(uv_archtype, "SGI", 3) != 0) { 367 368 /* (Not hubbed), check if not hubless */ 369 if (strncmp(uv_archtype, "NSGI", 4) != 0) 370 371 /* (Not hubless), not a UV */ 372 return 0; 373 374 /* Is UV hubless system */ 375 uv_hubless_system = 0x01; 376 377 /* UV5 Hubless */ 378 if (strncmp(uv_archtype, "NSGI5", 5) == 0) 379 uv_hubless_system |= 0x20; 380 381 /* UV4 Hubless: CH */ 382 else if (strncmp(uv_archtype, "NSGI4", 5) == 0) 383 uv_hubless_system |= 0x10; 384 385 /* UV3 Hubless: UV300/MC990X w/o hub */ 386 else 387 uv_hubless_system |= 0x8; 388 389 /* Copy OEM Table ID */ 390 uv_stringify(sizeof(oem_table_id), oem_table_id, _oem_table_id); 391 392 pr_info("UV: OEM IDs %s/%s, SystemType %d, HUBLESS ID %x\n", 393 oem_id, oem_table_id, uv_system_type, uv_hubless_system); 394 395 return 0; 396 } 397 398 if (numa_off) { 399 pr_err("UV: NUMA is off, disabling UV support\n"); 400 return 0; 401 } 402 403 /* Set hubbed type if true */ 404 uv_hub_info->hub_revision = 405 !strncmp(uv_archtype, "SGI5", 4) ? UV5_HUB_REVISION_BASE : 406 !strncmp(uv_archtype, "SGI4", 4) ? UV4_HUB_REVISION_BASE : 407 !strncmp(uv_archtype, "SGI3", 4) ? UV3_HUB_REVISION_BASE : 408 !strcmp(uv_archtype, "SGI2") ? UV2_HUB_REVISION_BASE : 0; 409 410 switch (uv_hub_info->hub_revision) { 411 case UV5_HUB_REVISION_BASE: 412 uv_hubbed_system = 0x21; 413 uv_hub_type_set(UV5); 414 break; 415 416 case UV4_HUB_REVISION_BASE: 417 uv_hubbed_system = 0x11; 418 uv_hub_type_set(UV4); 419 break; 420 421 case UV3_HUB_REVISION_BASE: 422 uv_hubbed_system = 0x9; 423 uv_hub_type_set(UV3); 424 break; 425 426 case UV2_HUB_REVISION_BASE: 427 uv_hubbed_system = 0x5; 428 uv_hub_type_set(UV2); 429 break; 430 431 default: 432 return 0; 433 } 434 435 /* Get UV hub chip part number & revision */ 436 early_set_hub_type(); 437 438 /* Other UV setup functions */ 439 early_set_apic_mode(); 440 early_get_pnodeid(); 441 early_get_apic_socketid_shift(); 442 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range; 443 x86_platform.nmi_init = uv_nmi_init; 444 uv_tsc_check_sync(); 445 446 return 1; 447 } 448 449 /* Called early to probe for the correct APIC driver */ 450 static int __init uv_acpi_madt_oem_check(char *_oem_id, char *_oem_table_id) 451 { 452 /* Set up early hub info fields for Node 0 */ 453 uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0; 454 455 /* If not UV, return. */ 456 if (uv_set_system_type(_oem_id, _oem_table_id) == 0) 457 return 0; 458 459 /* Save for display of the OEM Table ID */ 460 uv_stringify(sizeof(oem_table_id), oem_table_id, _oem_table_id); 461 462 pr_info("UV: OEM IDs %s/%s, System/UVType %d/0x%x, HUB RevID %d\n", 463 oem_id, oem_table_id, uv_system_type, is_uv(UV_ANY), 464 uv_min_hub_revision_id); 465 466 return 0; 467 } 468 469 enum uv_system_type get_uv_system_type(void) 470 { 471 return uv_system_type; 472 } 473 474 int uv_get_hubless_system(void) 475 { 476 return uv_hubless_system; 477 } 478 EXPORT_SYMBOL_GPL(uv_get_hubless_system); 479 480 ssize_t uv_get_archtype(char *buf, int len) 481 { 482 return scnprintf(buf, len, "%s/%s", uv_archtype, oem_table_id); 483 } 484 EXPORT_SYMBOL_GPL(uv_get_archtype); 485 486 int is_uv_system(void) 487 { 488 return uv_system_type != UV_NONE; 489 } 490 EXPORT_SYMBOL_GPL(is_uv_system); 491 492 int is_uv_hubbed(int uvtype) 493 { 494 return (uv_hubbed_system & uvtype); 495 } 496 EXPORT_SYMBOL_GPL(is_uv_hubbed); 497 498 static int is_uv_hubless(int uvtype) 499 { 500 return (uv_hubless_system & uvtype); 501 } 502 503 void **__uv_hub_info_list; 504 EXPORT_SYMBOL_GPL(__uv_hub_info_list); 505 506 DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info); 507 EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info); 508 509 short uv_possible_blades; 510 EXPORT_SYMBOL_GPL(uv_possible_blades); 511 512 unsigned long sn_rtc_cycles_per_second; 513 EXPORT_SYMBOL(sn_rtc_cycles_per_second); 514 515 /* The following values are used for the per node hub info struct */ 516 static __initdata unsigned short _min_socket, _max_socket; 517 static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len; 518 static __initdata struct uv_gam_range_entry *uv_gre_table; 519 static __initdata struct uv_gam_parameters *uv_gp_table; 520 static __initdata unsigned short *_socket_to_node; 521 static __initdata unsigned short *_socket_to_pnode; 522 static __initdata unsigned short *_pnode_to_socket; 523 static __initdata unsigned short *_node_to_socket; 524 525 static __initdata struct uv_gam_range_s *_gr_table; 526 527 #define SOCK_EMPTY ((unsigned short)~0) 528 529 /* Default UV memory block size is 2GB */ 530 static unsigned long mem_block_size __initdata = (2UL << 30); 531 532 /* Kernel parameter to specify UV mem block size */ 533 static int __init parse_mem_block_size(char *ptr) 534 { 535 unsigned long size = memparse(ptr, NULL); 536 537 /* Size will be rounded down by set_block_size() below */ 538 mem_block_size = size; 539 return 0; 540 } 541 early_param("uv_memblksize", parse_mem_block_size); 542 543 static __init int adj_blksize(u32 lgre) 544 { 545 unsigned long base = (unsigned long)lgre << UV_GAM_RANGE_SHFT; 546 unsigned long size; 547 548 for (size = mem_block_size; size > MIN_MEMORY_BLOCK_SIZE; size >>= 1) 549 if (IS_ALIGNED(base, size)) 550 break; 551 552 if (size >= mem_block_size) 553 return 0; 554 555 mem_block_size = size; 556 return 1; 557 } 558 559 static __init void set_block_size(void) 560 { 561 unsigned int order = ffs(mem_block_size); 562 563 if (order) { 564 /* adjust for ffs return of 1..64 */ 565 set_memory_block_size_order(order - 1); 566 pr_info("UV: mem_block_size set to 0x%lx\n", mem_block_size); 567 } else { 568 /* bad or zero value, default to 1UL << 31 (2GB) */ 569 pr_err("UV: mem_block_size error with 0x%lx\n", mem_block_size); 570 set_memory_block_size_order(31); 571 } 572 } 573 574 /* Build GAM range lookup table: */ 575 static __init void build_uv_gr_table(void) 576 { 577 struct uv_gam_range_entry *gre = uv_gre_table; 578 struct uv_gam_range_s *grt; 579 unsigned long last_limit = 0, ram_limit = 0; 580 int bytes, i, sid, lsid = -1, indx = 0, lindx = -1; 581 582 if (!gre) 583 return; 584 585 bytes = _gr_table_len * sizeof(struct uv_gam_range_s); 586 grt = kzalloc(bytes, GFP_KERNEL); 587 if (WARN_ON_ONCE(!grt)) 588 return; 589 _gr_table = grt; 590 591 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { 592 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) { 593 if (!ram_limit) { 594 /* Mark hole between RAM/non-RAM: */ 595 ram_limit = last_limit; 596 last_limit = gre->limit; 597 lsid++; 598 continue; 599 } 600 last_limit = gre->limit; 601 pr_info("UV: extra hole in GAM RE table @%d\n", (int)(gre - uv_gre_table)); 602 continue; 603 } 604 if (_max_socket < gre->sockid) { 605 pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n", gre->sockid, _max_socket, (int)(gre - uv_gre_table)); 606 continue; 607 } 608 sid = gre->sockid - _min_socket; 609 if (lsid < sid) { 610 /* New range: */ 611 grt = &_gr_table[indx]; 612 grt->base = lindx; 613 grt->nasid = gre->nasid; 614 grt->limit = last_limit = gre->limit; 615 lsid = sid; 616 lindx = indx++; 617 continue; 618 } 619 /* Update range: */ 620 if (lsid == sid && !ram_limit) { 621 /* .. if contiguous: */ 622 if (grt->limit == last_limit) { 623 grt->limit = last_limit = gre->limit; 624 continue; 625 } 626 } 627 /* Non-contiguous RAM range: */ 628 if (!ram_limit) { 629 grt++; 630 grt->base = lindx; 631 grt->nasid = gre->nasid; 632 grt->limit = last_limit = gre->limit; 633 continue; 634 } 635 /* Non-contiguous/non-RAM: */ 636 grt++; 637 /* base is this entry */ 638 grt->base = grt - _gr_table; 639 grt->nasid = gre->nasid; 640 grt->limit = last_limit = gre->limit; 641 lsid++; 642 } 643 644 /* Shorten table if possible */ 645 grt++; 646 i = grt - _gr_table; 647 if (i < _gr_table_len) { 648 void *ret; 649 650 bytes = i * sizeof(struct uv_gam_range_s); 651 ret = krealloc(_gr_table, bytes, GFP_KERNEL); 652 if (ret) { 653 _gr_table = ret; 654 _gr_table_len = i; 655 } 656 } 657 658 /* Display resultant GAM range table: */ 659 for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) { 660 unsigned long start, end; 661 int gb = grt->base; 662 663 start = gb < 0 ? 0 : (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT; 664 end = (unsigned long)grt->limit << UV_GAM_RANGE_SHFT; 665 666 pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n", i, grt->nasid, start, end, gb); 667 } 668 } 669 670 static int uv_wakeup_secondary(u32 phys_apicid, unsigned long start_rip) 671 { 672 unsigned long val; 673 int pnode; 674 675 pnode = uv_apicid_to_pnode(phys_apicid); 676 677 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 678 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | 679 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | 680 APIC_DM_INIT; 681 682 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 683 684 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 685 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | 686 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | 687 APIC_DM_STARTUP; 688 689 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 690 691 return 0; 692 } 693 694 static void uv_send_IPI_one(int cpu, int vector) 695 { 696 unsigned long apicid = per_cpu(x86_cpu_to_apicid, cpu); 697 int pnode = uv_apicid_to_pnode(apicid); 698 unsigned long dmode, val; 699 700 if (vector == NMI_VECTOR) 701 dmode = APIC_DELIVERY_MODE_NMI; 702 else 703 dmode = APIC_DELIVERY_MODE_FIXED; 704 705 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 706 (apicid << UVH_IPI_INT_APIC_ID_SHFT) | 707 (dmode << UVH_IPI_INT_DELIVERY_MODE_SHFT) | 708 (vector << UVH_IPI_INT_VECTOR_SHFT); 709 710 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 711 } 712 713 static void uv_send_IPI_mask(const struct cpumask *mask, int vector) 714 { 715 unsigned int cpu; 716 717 for_each_cpu(cpu, mask) 718 uv_send_IPI_one(cpu, vector); 719 } 720 721 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) 722 { 723 unsigned int this_cpu = smp_processor_id(); 724 unsigned int cpu; 725 726 for_each_cpu(cpu, mask) { 727 if (cpu != this_cpu) 728 uv_send_IPI_one(cpu, vector); 729 } 730 } 731 732 static void uv_send_IPI_allbutself(int vector) 733 { 734 unsigned int this_cpu = smp_processor_id(); 735 unsigned int cpu; 736 737 for_each_online_cpu(cpu) { 738 if (cpu != this_cpu) 739 uv_send_IPI_one(cpu, vector); 740 } 741 } 742 743 static void uv_send_IPI_all(int vector) 744 { 745 uv_send_IPI_mask(cpu_online_mask, vector); 746 } 747 748 static u32 set_apic_id(u32 id) 749 { 750 return id; 751 } 752 753 static int uv_probe(void) 754 { 755 return apic == &apic_x2apic_uv_x; 756 } 757 758 static struct apic apic_x2apic_uv_x __ro_after_init = { 759 760 .name = "UV large system", 761 .probe = uv_probe, 762 .acpi_madt_oem_check = uv_acpi_madt_oem_check, 763 764 .dest_mode_logical = false, 765 766 .disable_esr = 0, 767 768 .cpu_present_to_apicid = default_cpu_present_to_apicid, 769 770 .max_apic_id = UINT_MAX, 771 .get_apic_id = x2apic_get_apic_id, 772 .set_apic_id = set_apic_id, 773 774 .calc_dest_apicid = apic_default_calc_apicid, 775 776 .send_IPI = uv_send_IPI_one, 777 .send_IPI_mask = uv_send_IPI_mask, 778 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself, 779 .send_IPI_allbutself = uv_send_IPI_allbutself, 780 .send_IPI_all = uv_send_IPI_all, 781 .send_IPI_self = x2apic_send_IPI_self, 782 783 .wakeup_secondary_cpu = uv_wakeup_secondary, 784 785 .read = native_apic_msr_read, 786 .write = native_apic_msr_write, 787 .eoi = native_apic_msr_eoi, 788 .icr_read = native_x2apic_icr_read, 789 .icr_write = native_x2apic_icr_write, 790 }; 791 792 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3 793 #define DEST_SHIFT UVXH_RH_GAM_ALIAS_0_REDIRECT_CONFIG_DEST_BASE_SHFT 794 795 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size) 796 { 797 union uvh_rh_gam_alias_2_overlay_config_u alias; 798 union uvh_rh_gam_alias_2_redirect_config_u redirect; 799 unsigned long m_redirect; 800 unsigned long m_overlay; 801 int i; 802 803 for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) { 804 switch (i) { 805 case 0: 806 m_redirect = UVH_RH_GAM_ALIAS_0_REDIRECT_CONFIG; 807 m_overlay = UVH_RH_GAM_ALIAS_0_OVERLAY_CONFIG; 808 break; 809 case 1: 810 m_redirect = UVH_RH_GAM_ALIAS_1_REDIRECT_CONFIG; 811 m_overlay = UVH_RH_GAM_ALIAS_1_OVERLAY_CONFIG; 812 break; 813 case 2: 814 m_redirect = UVH_RH_GAM_ALIAS_2_REDIRECT_CONFIG; 815 m_overlay = UVH_RH_GAM_ALIAS_2_OVERLAY_CONFIG; 816 break; 817 } 818 alias.v = uv_read_local_mmr(m_overlay); 819 if (alias.s.enable && alias.s.base == 0) { 820 *size = (1UL << alias.s.m_alias); 821 redirect.v = uv_read_local_mmr(m_redirect); 822 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT; 823 return; 824 } 825 } 826 *base = *size = 0; 827 } 828 829 enum map_type {map_wb, map_uc}; 830 static const char * const mt[] = { "WB", "UC" }; 831 832 static __init void map_high(char *id, unsigned long base, int pshift, int bshift, int max_pnode, enum map_type map_type) 833 { 834 unsigned long bytes, paddr; 835 836 paddr = base << pshift; 837 bytes = (1UL << bshift) * (max_pnode + 1); 838 if (!paddr) { 839 pr_info("UV: Map %s_HI base address NULL\n", id); 840 return; 841 } 842 if (map_type == map_uc) 843 init_extra_mapping_uc(paddr, bytes); 844 else 845 init_extra_mapping_wb(paddr, bytes); 846 847 pr_info("UV: Map %s_HI 0x%lx - 0x%lx %s (%d segments)\n", 848 id, paddr, paddr + bytes, mt[map_type], max_pnode + 1); 849 } 850 851 static __init void map_gru_high(int max_pnode) 852 { 853 union uvh_rh_gam_gru_overlay_config_u gru; 854 unsigned long mask, base; 855 int shift; 856 857 if (UVH_RH_GAM_GRU_OVERLAY_CONFIG) { 858 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG); 859 shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT; 860 mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK; 861 } else if (UVH_RH10_GAM_GRU_OVERLAY_CONFIG) { 862 gru.v = uv_read_local_mmr(UVH_RH10_GAM_GRU_OVERLAY_CONFIG); 863 shift = UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT; 864 mask = UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_MASK; 865 } else { 866 pr_err("UV: GRU unavailable (no MMR)\n"); 867 return; 868 } 869 870 if (!gru.s.enable) { 871 pr_info("UV: GRU disabled (by BIOS)\n"); 872 return; 873 } 874 875 base = (gru.v & mask) >> shift; 876 map_high("GRU", base, shift, shift, max_pnode, map_wb); 877 gru_start_paddr = ((u64)base << shift); 878 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1); 879 } 880 881 static __init void map_mmr_high(int max_pnode) 882 { 883 unsigned long base; 884 int shift; 885 bool enable; 886 887 if (UVH_RH10_GAM_MMR_OVERLAY_CONFIG) { 888 union uvh_rh10_gam_mmr_overlay_config_u mmr; 889 890 mmr.v = uv_read_local_mmr(UVH_RH10_GAM_MMR_OVERLAY_CONFIG); 891 enable = mmr.s.enable; 892 base = mmr.s.base; 893 shift = UVH_RH10_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT; 894 } else if (UVH_RH_GAM_MMR_OVERLAY_CONFIG) { 895 union uvh_rh_gam_mmr_overlay_config_u mmr; 896 897 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG); 898 enable = mmr.s.enable; 899 base = mmr.s.base; 900 shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT; 901 } else { 902 pr_err("UV:%s:RH_GAM_MMR_OVERLAY_CONFIG MMR undefined?\n", 903 __func__); 904 return; 905 } 906 907 if (enable) 908 map_high("MMR", base, shift, shift, max_pnode, map_uc); 909 else 910 pr_info("UV: MMR disabled\n"); 911 } 912 913 /* Arch specific ENUM cases */ 914 enum mmioh_arch { 915 UV2_MMIOH = -1, 916 UVY_MMIOH0, UVY_MMIOH1, 917 UVX_MMIOH0, UVX_MMIOH1, 918 }; 919 920 /* Calculate and Map MMIOH Regions */ 921 static void __init calc_mmioh_map(enum mmioh_arch index, 922 int min_pnode, int max_pnode, 923 int shift, unsigned long base, int m_io, int n_io) 924 { 925 unsigned long mmr, nasid_mask; 926 int nasid, min_nasid, max_nasid, lnasid, mapped; 927 int i, fi, li, n, max_io; 928 char id[8]; 929 930 /* One (UV2) mapping */ 931 if (index == UV2_MMIOH) { 932 strscpy(id, "MMIOH", sizeof(id)); 933 max_io = max_pnode; 934 mapped = 0; 935 goto map_exit; 936 } 937 938 /* small and large MMIOH mappings */ 939 switch (index) { 940 case UVY_MMIOH0: 941 mmr = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0; 942 nasid_mask = UVYH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK; 943 n = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH; 944 min_nasid = min_pnode; 945 max_nasid = max_pnode; 946 mapped = 1; 947 break; 948 case UVY_MMIOH1: 949 mmr = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1; 950 nasid_mask = UVYH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK; 951 n = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH; 952 min_nasid = min_pnode; 953 max_nasid = max_pnode; 954 mapped = 1; 955 break; 956 case UVX_MMIOH0: 957 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0; 958 nasid_mask = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK; 959 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH; 960 min_nasid = min_pnode * 2; 961 max_nasid = max_pnode * 2; 962 mapped = 1; 963 break; 964 case UVX_MMIOH1: 965 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1; 966 nasid_mask = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK; 967 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH; 968 min_nasid = min_pnode * 2; 969 max_nasid = max_pnode * 2; 970 mapped = 1; 971 break; 972 default: 973 pr_err("UV:%s:Invalid mapping type:%d\n", __func__, index); 974 return; 975 } 976 977 /* enum values chosen so (index mod 2) is MMIOH 0/1 (low/high) */ 978 snprintf(id, sizeof(id), "MMIOH%d", index%2); 979 980 max_io = lnasid = fi = li = -1; 981 for (i = 0; i < n; i++) { 982 unsigned long m_redirect = mmr + i * 8; 983 unsigned long redirect = uv_read_local_mmr(m_redirect); 984 985 nasid = redirect & nasid_mask; 986 if (i == 0) 987 pr_info("UV: %s redirect base 0x%lx(@0x%lx) 0x%04x\n", 988 id, redirect, m_redirect, nasid); 989 990 /* Invalid NASID check */ 991 if (nasid < min_nasid || max_nasid < nasid) { 992 /* Not an error: unused table entries get "poison" values */ 993 pr_debug("UV:%s:Invalid NASID(%x):%x (range:%x..%x)\n", 994 __func__, index, nasid, min_nasid, max_nasid); 995 nasid = -1; 996 } 997 998 if (nasid == lnasid) { 999 li = i; 1000 /* Last entry check: */ 1001 if (i != n-1) 1002 continue; 1003 } 1004 1005 /* Check if we have a cached (or last) redirect to print: */ 1006 if (lnasid != -1 || (i == n-1 && nasid != -1)) { 1007 unsigned long addr1, addr2; 1008 int f, l; 1009 1010 if (lnasid == -1) { 1011 f = l = i; 1012 lnasid = nasid; 1013 } else { 1014 f = fi; 1015 l = li; 1016 } 1017 addr1 = (base << shift) + f * (1ULL << m_io); 1018 addr2 = (base << shift) + (l + 1) * (1ULL << m_io); 1019 pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n", 1020 id, fi, li, lnasid, addr1, addr2); 1021 if (max_io < l) 1022 max_io = l; 1023 } 1024 fi = li = i; 1025 lnasid = nasid; 1026 } 1027 1028 map_exit: 1029 pr_info("UV: %s base:0x%lx shift:%d m_io:%d max_io:%d max_pnode:0x%x\n", 1030 id, base, shift, m_io, max_io, max_pnode); 1031 1032 if (max_io >= 0 && !mapped) 1033 map_high(id, base, shift, m_io, max_io, map_uc); 1034 } 1035 1036 static __init void map_mmioh_high(int min_pnode, int max_pnode) 1037 { 1038 /* UVY flavor */ 1039 if (UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0) { 1040 union uvh_rh10_gam_mmioh_overlay_config0_u mmioh0; 1041 union uvh_rh10_gam_mmioh_overlay_config1_u mmioh1; 1042 1043 mmioh0.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0); 1044 if (unlikely(mmioh0.s.enable == 0)) 1045 pr_info("UV: MMIOH0 disabled\n"); 1046 else 1047 calc_mmioh_map(UVY_MMIOH0, min_pnode, max_pnode, 1048 UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT, 1049 mmioh0.s.base, mmioh0.s.m_io, mmioh0.s.n_io); 1050 1051 mmioh1.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1); 1052 if (unlikely(mmioh1.s.enable == 0)) 1053 pr_info("UV: MMIOH1 disabled\n"); 1054 else 1055 calc_mmioh_map(UVY_MMIOH1, min_pnode, max_pnode, 1056 UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT, 1057 mmioh1.s.base, mmioh1.s.m_io, mmioh1.s.n_io); 1058 return; 1059 } 1060 /* UVX flavor */ 1061 if (UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0) { 1062 union uvh_rh_gam_mmioh_overlay_config0_u mmioh0; 1063 union uvh_rh_gam_mmioh_overlay_config1_u mmioh1; 1064 1065 mmioh0.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0); 1066 if (unlikely(mmioh0.s.enable == 0)) 1067 pr_info("UV: MMIOH0 disabled\n"); 1068 else { 1069 unsigned long base = uvxy_field(mmioh0, base, 0); 1070 int m_io = uvxy_field(mmioh0, m_io, 0); 1071 int n_io = uvxy_field(mmioh0, n_io, 0); 1072 1073 calc_mmioh_map(UVX_MMIOH0, min_pnode, max_pnode, 1074 UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT, 1075 base, m_io, n_io); 1076 } 1077 1078 mmioh1.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1); 1079 if (unlikely(mmioh1.s.enable == 0)) 1080 pr_info("UV: MMIOH1 disabled\n"); 1081 else { 1082 unsigned long base = uvxy_field(mmioh1, base, 0); 1083 int m_io = uvxy_field(mmioh1, m_io, 0); 1084 int n_io = uvxy_field(mmioh1, n_io, 0); 1085 1086 calc_mmioh_map(UVX_MMIOH1, min_pnode, max_pnode, 1087 UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT, 1088 base, m_io, n_io); 1089 } 1090 return; 1091 } 1092 1093 /* UV2 flavor */ 1094 if (UVH_RH_GAM_MMIOH_OVERLAY_CONFIG) { 1095 union uvh_rh_gam_mmioh_overlay_config_u mmioh; 1096 1097 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG); 1098 if (unlikely(mmioh.s2.enable == 0)) 1099 pr_info("UV: MMIOH disabled\n"); 1100 else 1101 calc_mmioh_map(UV2_MMIOH, min_pnode, max_pnode, 1102 UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_BASE_SHFT, 1103 mmioh.s2.base, mmioh.s2.m_io, mmioh.s2.n_io); 1104 return; 1105 } 1106 } 1107 1108 static __init void map_low_mmrs(void) 1109 { 1110 if (UV_GLOBAL_MMR32_BASE) 1111 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE); 1112 1113 if (UV_LOCAL_MMR_BASE) 1114 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE); 1115 } 1116 1117 static __init void uv_rtc_init(void) 1118 { 1119 long status; 1120 u64 ticks_per_sec; 1121 1122 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec); 1123 1124 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) { 1125 pr_warn("UV: unable to determine platform RTC clock frequency, guessing.\n"); 1126 1127 /* BIOS gives wrong value for clock frequency, so guess: */ 1128 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL; 1129 } else { 1130 sn_rtc_cycles_per_second = ticks_per_sec; 1131 } 1132 } 1133 1134 /* Direct Legacy VGA I/O traffic to designated IOH */ 1135 static int uv_set_vga_state(struct pci_dev *pdev, bool decode, unsigned int command_bits, u32 flags) 1136 { 1137 int domain, bus, rc; 1138 1139 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) 1140 return 0; 1141 1142 if ((command_bits & PCI_COMMAND_IO) == 0) 1143 return 0; 1144 1145 domain = pci_domain_nr(pdev->bus); 1146 bus = pdev->bus->number; 1147 1148 rc = uv_bios_set_legacy_vga_target(decode, domain, bus); 1149 1150 return rc; 1151 } 1152 1153 /* 1154 * Called on each CPU to initialize the per_cpu UV data area. 1155 * FIXME: hotplug not supported yet 1156 */ 1157 void uv_cpu_init(void) 1158 { 1159 /* CPU 0 initialization will be done via uv_system_init. */ 1160 if (smp_processor_id() == 0) 1161 return; 1162 1163 uv_hub_info->nr_online_cpus++; 1164 } 1165 1166 struct mn { 1167 unsigned char m_val; 1168 unsigned char n_val; 1169 unsigned char m_shift; 1170 unsigned char n_lshift; 1171 }; 1172 1173 /* Initialize caller's MN struct and fill in values */ 1174 static void get_mn(struct mn *mnp) 1175 { 1176 memset(mnp, 0, sizeof(*mnp)); 1177 mnp->n_val = uv_cpuid.n_skt; 1178 if (is_uv(UV4|UVY)) { 1179 mnp->m_val = 0; 1180 mnp->n_lshift = 0; 1181 } else if (is_uv3_hub()) { 1182 union uvyh_gr0_gam_gr_config_u m_gr_config; 1183 1184 mnp->m_val = uv_cpuid.m_skt; 1185 m_gr_config.v = uv_read_local_mmr(UVH_GR0_GAM_GR_CONFIG); 1186 mnp->n_lshift = m_gr_config.s3.m_skt; 1187 } else if (is_uv2_hub()) { 1188 mnp->m_val = uv_cpuid.m_skt; 1189 mnp->n_lshift = mnp->m_val == 40 ? 40 : 39; 1190 } 1191 mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0; 1192 } 1193 1194 static void __init uv_init_hub_info(struct uv_hub_info_s *hi) 1195 { 1196 struct mn mn; 1197 1198 get_mn(&mn); 1199 hi->gpa_mask = mn.m_val ? 1200 (1UL << (mn.m_val + mn.n_val)) - 1 : 1201 (1UL << uv_cpuid.gpa_shift) - 1; 1202 1203 hi->m_val = mn.m_val; 1204 hi->n_val = mn.n_val; 1205 hi->m_shift = mn.m_shift; 1206 hi->n_lshift = mn.n_lshift ? mn.n_lshift : 0; 1207 hi->hub_revision = uv_hub_info->hub_revision; 1208 hi->hub_type = uv_hub_info->hub_type; 1209 hi->pnode_mask = uv_cpuid.pnode_mask; 1210 hi->nasid_shift = uv_cpuid.nasid_shift; 1211 hi->min_pnode = _min_pnode; 1212 hi->min_socket = _min_socket; 1213 hi->node_to_socket = _node_to_socket; 1214 hi->pnode_to_socket = _pnode_to_socket; 1215 hi->socket_to_node = _socket_to_node; 1216 hi->socket_to_pnode = _socket_to_pnode; 1217 hi->gr_table_len = _gr_table_len; 1218 hi->gr_table = _gr_table; 1219 1220 uv_cpuid.gnode_shift = max_t(unsigned int, uv_cpuid.gnode_shift, mn.n_val); 1221 hi->gnode_extra = (uv_node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1; 1222 if (mn.m_val) 1223 hi->gnode_upper = (u64)hi->gnode_extra << mn.m_val; 1224 1225 if (uv_gp_table) { 1226 hi->global_mmr_base = uv_gp_table->mmr_base; 1227 hi->global_mmr_shift = uv_gp_table->mmr_shift; 1228 hi->global_gru_base = uv_gp_table->gru_base; 1229 hi->global_gru_shift = uv_gp_table->gru_shift; 1230 hi->gpa_shift = uv_gp_table->gpa_shift; 1231 hi->gpa_mask = (1UL << hi->gpa_shift) - 1; 1232 } else { 1233 hi->global_mmr_base = 1234 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG) & 1235 ~UV_MMR_ENABLE; 1236 hi->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT; 1237 } 1238 1239 get_lowmem_redirect(&hi->lowmem_remap_base, &hi->lowmem_remap_top); 1240 1241 hi->apic_pnode_shift = uv_cpuid.socketid_shift; 1242 1243 /* Show system specific info: */ 1244 pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", hi->n_val, hi->m_val, hi->m_shift, hi->n_lshift); 1245 pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n", hi->gpa_mask, hi->gpa_shift, hi->pnode_mask, hi->apic_pnode_shift); 1246 pr_info("UV: mmr_base/shift:0x%lx/%ld\n", hi->global_mmr_base, hi->global_mmr_shift); 1247 if (hi->global_gru_base) 1248 pr_info("UV: gru_base/shift:0x%lx/%ld\n", 1249 hi->global_gru_base, hi->global_gru_shift); 1250 1251 pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n", hi->gnode_upper, hi->gnode_extra); 1252 } 1253 1254 static void __init decode_gam_params(unsigned long ptr) 1255 { 1256 uv_gp_table = (struct uv_gam_parameters *)ptr; 1257 1258 pr_info("UV: GAM Params...\n"); 1259 pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n", 1260 uv_gp_table->mmr_base, uv_gp_table->mmr_shift, 1261 uv_gp_table->gru_base, uv_gp_table->gru_shift, 1262 uv_gp_table->gpa_shift); 1263 } 1264 1265 static void __init decode_gam_rng_tbl(unsigned long ptr) 1266 { 1267 struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr; 1268 unsigned long lgre = 0, gend = 0; 1269 int index = 0; 1270 int sock_min = INT_MAX, pnode_min = INT_MAX; 1271 int sock_max = -1, pnode_max = -1; 1272 1273 uv_gre_table = gre; 1274 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { 1275 unsigned long size = ((unsigned long)(gre->limit - lgre) 1276 << UV_GAM_RANGE_SHFT); 1277 int order = 0; 1278 char suffix[] = " KMGTPE"; 1279 int flag = ' '; 1280 1281 while (size > 9999 && order < sizeof(suffix)) { 1282 size /= 1024; 1283 order++; 1284 } 1285 1286 /* adjust max block size to current range start */ 1287 if (gre->type == 1 || gre->type == 2) 1288 if (adj_blksize(lgre)) 1289 flag = '*'; 1290 1291 if (!index) { 1292 pr_info("UV: GAM Range Table...\n"); 1293 pr_info("UV: # %20s %14s %6s %4s %5s %3s %2s\n", "Range", "", "Size", "Type", "NASID", "SID", "PN"); 1294 } 1295 pr_info("UV: %2d: 0x%014lx-0x%014lx%c %5lu%c %3d %04x %02x %02x\n", 1296 index++, 1297 (unsigned long)lgre << UV_GAM_RANGE_SHFT, 1298 (unsigned long)gre->limit << UV_GAM_RANGE_SHFT, 1299 flag, size, suffix[order], 1300 gre->type, gre->nasid, gre->sockid, gre->pnode); 1301 1302 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) 1303 gend = (unsigned long)gre->limit << UV_GAM_RANGE_SHFT; 1304 1305 /* update to next range start */ 1306 lgre = gre->limit; 1307 if (sock_min > gre->sockid) 1308 sock_min = gre->sockid; 1309 if (sock_max < gre->sockid) 1310 sock_max = gre->sockid; 1311 if (pnode_min > gre->pnode) 1312 pnode_min = gre->pnode; 1313 if (pnode_max < gre->pnode) 1314 pnode_max = gre->pnode; 1315 } 1316 _min_socket = sock_min; 1317 _max_socket = sock_max; 1318 _min_pnode = pnode_min; 1319 _max_pnode = pnode_max; 1320 _gr_table_len = index; 1321 1322 pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x), pnodes(min:%x,max:%x), gap_end(%d)\n", 1323 index, _min_socket, _max_socket, _min_pnode, _max_pnode, fls64(gend)); 1324 } 1325 1326 /* Walk through UVsystab decoding the fields */ 1327 static int __init decode_uv_systab(void) 1328 { 1329 struct uv_systab *st; 1330 int i; 1331 1332 /* Get mapped UVsystab pointer */ 1333 st = uv_systab; 1334 1335 /* If UVsystab is version 1, there is no extended UVsystab */ 1336 if (st && st->revision == UV_SYSTAB_VERSION_1) 1337 return 0; 1338 1339 if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) { 1340 int rev = st ? st->revision : 0; 1341 1342 pr_err("UV: BIOS UVsystab mismatch, (%x < %x)\n", 1343 rev, UV_SYSTAB_VERSION_UV4_LATEST); 1344 pr_err("UV: Does not support UV, switch to non-UV x86_64\n"); 1345 uv_system_type = UV_NONE; 1346 1347 return -EINVAL; 1348 } 1349 1350 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) { 1351 unsigned long ptr = st->entry[i].offset; 1352 1353 if (!ptr) 1354 continue; 1355 1356 /* point to payload */ 1357 ptr += (unsigned long)st; 1358 1359 switch (st->entry[i].type) { 1360 case UV_SYSTAB_TYPE_GAM_PARAMS: 1361 decode_gam_params(ptr); 1362 break; 1363 1364 case UV_SYSTAB_TYPE_GAM_RNG_TBL: 1365 decode_gam_rng_tbl(ptr); 1366 break; 1367 1368 case UV_SYSTAB_TYPE_ARCH_TYPE: 1369 /* already processed in early startup */ 1370 break; 1371 1372 default: 1373 pr_err("UV:%s:Unrecognized UV_SYSTAB_TYPE:%d, skipped\n", 1374 __func__, st->entry[i].type); 1375 break; 1376 } 1377 } 1378 return 0; 1379 } 1380 1381 /* 1382 * Given a bitmask 'bits' representing presnt blades, numbered 1383 * starting at 'base', masking off unused high bits of blade number 1384 * with 'mask', update the minimum and maximum blade numbers that we 1385 * have found. (Masking with 'mask' necessary because of BIOS 1386 * treatment of system partitioning when creating this table we are 1387 * interpreting.) 1388 */ 1389 static inline void blade_update_min_max(unsigned long bits, int base, int mask, int *min, int *max) 1390 { 1391 int first, last; 1392 1393 if (!bits) 1394 return; 1395 first = (base + __ffs(bits)) & mask; 1396 last = (base + __fls(bits)) & mask; 1397 1398 if (*min > first) 1399 *min = first; 1400 if (*max < last) 1401 *max = last; 1402 } 1403 1404 /* Set up physical blade translations from UVH_NODE_PRESENT_TABLE */ 1405 static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info) 1406 { 1407 unsigned long np; 1408 int i, uv_pb = 0; 1409 int sock_min = INT_MAX, sock_max = -1, s_mask; 1410 1411 s_mask = (1 << uv_cpuid.n_skt) - 1; 1412 1413 if (UVH_NODE_PRESENT_TABLE) { 1414 pr_info("UV: NODE_PRESENT_DEPTH = %d\n", 1415 UVH_NODE_PRESENT_TABLE_DEPTH); 1416 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) { 1417 np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8); 1418 pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np); 1419 blade_update_min_max(np, i * 64, s_mask, &sock_min, &sock_max); 1420 } 1421 } 1422 if (UVH_NODE_PRESENT_0) { 1423 np = uv_read_local_mmr(UVH_NODE_PRESENT_0); 1424 pr_info("UV: NODE_PRESENT_0 = 0x%016lx\n", np); 1425 blade_update_min_max(np, 0, s_mask, &sock_min, &sock_max); 1426 } 1427 if (UVH_NODE_PRESENT_1) { 1428 np = uv_read_local_mmr(UVH_NODE_PRESENT_1); 1429 pr_info("UV: NODE_PRESENT_1 = 0x%016lx\n", np); 1430 blade_update_min_max(np, 64, s_mask, &sock_min, &sock_max); 1431 } 1432 1433 /* Only update if we actually found some bits indicating blades present */ 1434 if (sock_max >= sock_min) { 1435 _min_socket = sock_min; 1436 _max_socket = sock_max; 1437 uv_pb = sock_max - sock_min + 1; 1438 } 1439 if (uv_possible_blades != uv_pb) 1440 uv_possible_blades = uv_pb; 1441 1442 pr_info("UV: number nodes/possible blades %d (%d - %d)\n", 1443 uv_pb, sock_min, sock_max); 1444 } 1445 1446 static int __init alloc_conv_table(int num_elem, unsigned short **table) 1447 { 1448 int i; 1449 size_t bytes; 1450 1451 bytes = num_elem * sizeof(*table[0]); 1452 *table = kmalloc(bytes, GFP_KERNEL); 1453 if (WARN_ON_ONCE(!*table)) 1454 return -ENOMEM; 1455 for (i = 0; i < num_elem; i++) 1456 ((unsigned short *)*table)[i] = SOCK_EMPTY; 1457 return 0; 1458 } 1459 1460 /* Remove conversion table if it's 1:1 */ 1461 #define FREE_1_TO_1_TABLE(tbl, min, max, max2) free_1_to_1_table(&tbl, #tbl, min, max, max2) 1462 1463 static void __init free_1_to_1_table(unsigned short **tp, char *tname, int min, int max, int max2) 1464 { 1465 int i; 1466 unsigned short *table = *tp; 1467 1468 if (table == NULL) 1469 return; 1470 if (max != max2) 1471 return; 1472 for (i = 0; i < max; i++) { 1473 if (i != table[i]) 1474 return; 1475 } 1476 kfree(table); 1477 *tp = NULL; 1478 pr_info("UV: %s is 1:1, conversion table removed\n", tname); 1479 } 1480 1481 /* 1482 * Build Socket Tables 1483 * If the number of nodes is >1 per socket, socket to node table will 1484 * contain lowest node number on that socket. 1485 */ 1486 static void __init build_socket_tables(void) 1487 { 1488 struct uv_gam_range_entry *gre = uv_gre_table; 1489 int nums, numn, nump; 1490 int i, lnid, apicid; 1491 int minsock = _min_socket; 1492 int maxsock = _max_socket; 1493 int minpnode = _min_pnode; 1494 int maxpnode = _max_pnode; 1495 1496 if (!gre) { 1497 if (is_uv2_hub() || is_uv3_hub()) { 1498 pr_info("UV: No UVsystab socket table, ignoring\n"); 1499 return; 1500 } 1501 pr_err("UV: Error: UVsystab address translations not available!\n"); 1502 WARN_ON_ONCE(!gre); 1503 return; 1504 } 1505 1506 numn = num_possible_nodes(); 1507 nump = maxpnode - minpnode + 1; 1508 nums = maxsock - minsock + 1; 1509 1510 /* Allocate and clear tables */ 1511 if ((alloc_conv_table(nump, &_pnode_to_socket) < 0) 1512 || (alloc_conv_table(nums, &_socket_to_pnode) < 0) 1513 || (alloc_conv_table(numn, &_node_to_socket) < 0) 1514 || (alloc_conv_table(nums, &_socket_to_node) < 0)) { 1515 kfree(_pnode_to_socket); 1516 kfree(_socket_to_pnode); 1517 kfree(_node_to_socket); 1518 return; 1519 } 1520 1521 /* Fill in pnode/node/addr conversion list values: */ 1522 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { 1523 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) 1524 continue; 1525 i = gre->sockid - minsock; 1526 if (_socket_to_pnode[i] == SOCK_EMPTY) 1527 _socket_to_pnode[i] = gre->pnode; 1528 1529 i = gre->pnode - minpnode; 1530 if (_pnode_to_socket[i] == SOCK_EMPTY) 1531 _pnode_to_socket[i] = gre->sockid; 1532 1533 pr_info("UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n", 1534 gre->sockid, gre->type, gre->nasid, 1535 _socket_to_pnode[gre->sockid - minsock], 1536 _pnode_to_socket[gre->pnode - minpnode]); 1537 } 1538 1539 /* Set socket -> node values: */ 1540 lnid = NUMA_NO_NODE; 1541 for (apicid = 0; apicid < ARRAY_SIZE(__apicid_to_node); apicid++) { 1542 int nid = __apicid_to_node[apicid]; 1543 int sockid; 1544 1545 if ((nid == NUMA_NO_NODE) || (lnid == nid)) 1546 continue; 1547 lnid = nid; 1548 1549 sockid = apicid >> uv_cpuid.socketid_shift; 1550 1551 if (_socket_to_node[sockid - minsock] == SOCK_EMPTY) 1552 _socket_to_node[sockid - minsock] = nid; 1553 1554 if (_node_to_socket[nid] == SOCK_EMPTY) 1555 _node_to_socket[nid] = sockid; 1556 1557 pr_info("UV: sid:%02x: apicid:%04x socket:%02d node:%03x s2n:%03x\n", 1558 sockid, 1559 apicid, 1560 _node_to_socket[nid], 1561 nid, 1562 _socket_to_node[sockid - minsock]); 1563 } 1564 1565 /* 1566 * If e.g. socket id == pnode for all pnodes, 1567 * system runs faster by removing corresponding conversion table. 1568 */ 1569 FREE_1_TO_1_TABLE(_socket_to_node, _min_socket, nums, numn); 1570 FREE_1_TO_1_TABLE(_node_to_socket, _min_socket, nums, numn); 1571 FREE_1_TO_1_TABLE(_socket_to_pnode, _min_pnode, nums, nump); 1572 FREE_1_TO_1_TABLE(_pnode_to_socket, _min_pnode, nums, nump); 1573 } 1574 1575 /* Check which reboot to use */ 1576 static void check_efi_reboot(void) 1577 { 1578 /* If EFI reboot not available, use ACPI reboot */ 1579 if (!efi_enabled(EFI_BOOT)) 1580 reboot_type = BOOT_ACPI; 1581 } 1582 1583 /* 1584 * User proc fs file handling now deprecated. 1585 * Recommend using /sys/firmware/sgi_uv/... instead. 1586 */ 1587 static int __maybe_unused proc_hubbed_show(struct seq_file *file, void *data) 1588 { 1589 pr_notice_once("%s: using deprecated /proc/sgi_uv/hubbed, use /sys/firmware/sgi_uv/hub_type\n", 1590 current->comm); 1591 seq_printf(file, "0x%x\n", uv_hubbed_system); 1592 return 0; 1593 } 1594 1595 static int __maybe_unused proc_hubless_show(struct seq_file *file, void *data) 1596 { 1597 pr_notice_once("%s: using deprecated /proc/sgi_uv/hubless, use /sys/firmware/sgi_uv/hubless\n", 1598 current->comm); 1599 seq_printf(file, "0x%x\n", uv_hubless_system); 1600 return 0; 1601 } 1602 1603 static int __maybe_unused proc_archtype_show(struct seq_file *file, void *data) 1604 { 1605 pr_notice_once("%s: using deprecated /proc/sgi_uv/archtype, use /sys/firmware/sgi_uv/archtype\n", 1606 current->comm); 1607 seq_printf(file, "%s/%s\n", uv_archtype, oem_table_id); 1608 return 0; 1609 } 1610 1611 static __init void uv_setup_proc_files(int hubless) 1612 { 1613 struct proc_dir_entry *pde; 1614 1615 pde = proc_mkdir(UV_PROC_NODE, NULL); 1616 proc_create_single("archtype", 0, pde, proc_archtype_show); 1617 if (hubless) 1618 proc_create_single("hubless", 0, pde, proc_hubless_show); 1619 else 1620 proc_create_single("hubbed", 0, pde, proc_hubbed_show); 1621 } 1622 1623 /* Initialize UV hubless systems */ 1624 static __init int uv_system_init_hubless(void) 1625 { 1626 int rc; 1627 1628 /* Setup PCH NMI handler */ 1629 uv_nmi_setup_hubless(); 1630 1631 /* Init kernel/BIOS interface */ 1632 rc = uv_bios_init(); 1633 if (rc < 0) 1634 return rc; 1635 1636 /* Process UVsystab */ 1637 rc = decode_uv_systab(); 1638 if (rc < 0) 1639 return rc; 1640 1641 /* Set section block size for current node memory */ 1642 set_block_size(); 1643 1644 /* Create user access node */ 1645 if (rc >= 0) 1646 uv_setup_proc_files(1); 1647 1648 check_efi_reboot(); 1649 1650 return rc; 1651 } 1652 1653 static void __init uv_system_init_hub(void) 1654 { 1655 struct uv_hub_info_s hub_info = {0}; 1656 int bytes, cpu, nodeid, bid; 1657 unsigned short min_pnode = USHRT_MAX, max_pnode = 0; 1658 char *hub = is_uv5_hub() ? "UV500" : 1659 is_uv4_hub() ? "UV400" : 1660 is_uv3_hub() ? "UV300" : 1661 is_uv2_hub() ? "UV2000/3000" : NULL; 1662 struct uv_hub_info_s **uv_hub_info_list_blade; 1663 1664 if (!hub) { 1665 pr_err("UV: Unknown/unsupported UV hub\n"); 1666 return; 1667 } 1668 pr_info("UV: Found %s hub\n", hub); 1669 1670 map_low_mmrs(); 1671 1672 /* Get uv_systab for decoding, setup UV BIOS calls */ 1673 uv_bios_init(); 1674 1675 /* If there's an UVsystab problem then abort UV init: */ 1676 if (decode_uv_systab() < 0) { 1677 pr_err("UV: Mangled UVsystab format\n"); 1678 return; 1679 } 1680 1681 build_socket_tables(); 1682 build_uv_gr_table(); 1683 set_block_size(); 1684 uv_init_hub_info(&hub_info); 1685 /* If UV2 or UV3 may need to get # blades from HW */ 1686 if (is_uv(UV2|UV3) && !uv_gre_table) 1687 boot_init_possible_blades(&hub_info); 1688 else 1689 /* min/max sockets set in decode_gam_rng_tbl */ 1690 uv_possible_blades = (_max_socket - _min_socket) + 1; 1691 1692 /* uv_num_possible_blades() is really the hub count: */ 1693 pr_info("UV: Found %d hubs, %d nodes, %d CPUs\n", uv_num_possible_blades(), num_possible_nodes(), num_possible_cpus()); 1694 1695 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, &sn_region_size, &system_serial_number); 1696 hub_info.coherency_domain_number = sn_coherency_id; 1697 uv_rtc_init(); 1698 1699 /* 1700 * __uv_hub_info_list[] is indexed by node, but there is only 1701 * one hub_info structure per blade. First, allocate one 1702 * structure per blade. Further down we create a per-node 1703 * table (__uv_hub_info_list[]) pointing to hub_info 1704 * structures for the correct blade. 1705 */ 1706 1707 bytes = sizeof(void *) * uv_num_possible_blades(); 1708 uv_hub_info_list_blade = kzalloc(bytes, GFP_KERNEL); 1709 if (WARN_ON_ONCE(!uv_hub_info_list_blade)) 1710 return; 1711 1712 bytes = sizeof(struct uv_hub_info_s); 1713 for_each_possible_blade(bid) { 1714 struct uv_hub_info_s *new_hub; 1715 1716 /* Allocate & fill new per hub info list */ 1717 new_hub = (bid == 0) ? &uv_hub_info_node0 1718 : kzalloc_node(bytes, GFP_KERNEL, uv_blade_to_node(bid)); 1719 if (WARN_ON_ONCE(!new_hub)) { 1720 /* do not kfree() bid 0, which is statically allocated */ 1721 while (--bid > 0) 1722 kfree(uv_hub_info_list_blade[bid]); 1723 kfree(uv_hub_info_list_blade); 1724 return; 1725 } 1726 1727 uv_hub_info_list_blade[bid] = new_hub; 1728 *new_hub = hub_info; 1729 1730 /* Use information from GAM table if available: */ 1731 if (uv_gre_table) 1732 new_hub->pnode = uv_blade_to_pnode(bid); 1733 else /* Or fill in during CPU loop: */ 1734 new_hub->pnode = 0xffff; 1735 1736 new_hub->numa_blade_id = bid; 1737 new_hub->memory_nid = NUMA_NO_NODE; 1738 new_hub->nr_possible_cpus = 0; 1739 new_hub->nr_online_cpus = 0; 1740 } 1741 1742 /* 1743 * Now populate __uv_hub_info_list[] for each node with the 1744 * pointer to the struct for the blade it resides on. 1745 */ 1746 1747 bytes = sizeof(void *) * num_possible_nodes(); 1748 __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL); 1749 if (WARN_ON_ONCE(!__uv_hub_info_list)) { 1750 for_each_possible_blade(bid) 1751 /* bid 0 is statically allocated */ 1752 if (bid != 0) 1753 kfree(uv_hub_info_list_blade[bid]); 1754 kfree(uv_hub_info_list_blade); 1755 return; 1756 } 1757 1758 for_each_node(nodeid) 1759 __uv_hub_info_list[nodeid] = uv_hub_info_list_blade[uv_node_to_blade_id(nodeid)]; 1760 1761 /* Initialize per CPU info: */ 1762 for_each_possible_cpu(cpu) { 1763 int apicid = per_cpu(x86_cpu_to_apicid, cpu); 1764 unsigned short bid; 1765 unsigned short pnode; 1766 1767 pnode = uv_apicid_to_pnode(apicid); 1768 bid = uv_pnode_to_socket(pnode) - _min_socket; 1769 1770 uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list_blade[bid]; 1771 uv_cpu_info_per(cpu)->blade_cpu_id = uv_cpu_hub_info(cpu)->nr_possible_cpus++; 1772 if (uv_cpu_hub_info(cpu)->memory_nid == NUMA_NO_NODE) 1773 uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu); 1774 1775 if (uv_cpu_hub_info(cpu)->pnode == 0xffff) 1776 uv_cpu_hub_info(cpu)->pnode = pnode; 1777 } 1778 1779 for_each_possible_blade(bid) { 1780 unsigned short pnode = uv_hub_info_list_blade[bid]->pnode; 1781 1782 if (pnode == 0xffff) 1783 continue; 1784 1785 min_pnode = min(pnode, min_pnode); 1786 max_pnode = max(pnode, max_pnode); 1787 pr_info("UV: HUB:%2d pn:%02x nrcpus:%d\n", 1788 bid, 1789 uv_hub_info_list_blade[bid]->pnode, 1790 uv_hub_info_list_blade[bid]->nr_possible_cpus); 1791 } 1792 1793 pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode); 1794 map_gru_high(max_pnode); 1795 map_mmr_high(max_pnode); 1796 map_mmioh_high(min_pnode, max_pnode); 1797 1798 kfree(uv_hub_info_list_blade); 1799 uv_hub_info_list_blade = NULL; 1800 1801 uv_nmi_setup(); 1802 uv_cpu_init(); 1803 uv_setup_proc_files(0); 1804 1805 /* Register Legacy VGA I/O redirection handler: */ 1806 pci_register_set_vga_state(uv_set_vga_state); 1807 1808 check_efi_reboot(); 1809 } 1810 1811 /* 1812 * There is a different code path needed to initialize a UV system that does 1813 * not have a "UV HUB" (referred to as "hubless"). 1814 */ 1815 void __init uv_system_init(void) 1816 { 1817 if (likely(!is_uv_system() && !is_uv_hubless(1))) 1818 return; 1819 1820 if (is_uv_system()) 1821 uv_system_init_hub(); 1822 else 1823 uv_system_init_hubless(); 1824 } 1825 1826 apic_driver(apic_x2apic_uv_x); 1827