1 /* 2 * Local APIC related interfaces to support IOAPIC, MSI, etc. 3 * 4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo 5 * Moved from arch/x86/kernel/apic/io_apic.c. 6 * Jiang Liu <jiang.liu@linux.intel.com> 7 * Enable support of hierarchical irqdomains 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 #include <linux/interrupt.h> 14 #include <linux/seq_file.h> 15 #include <linux/init.h> 16 #include <linux/compiler.h> 17 #include <linux/slab.h> 18 #include <asm/irqdomain.h> 19 #include <asm/hw_irq.h> 20 #include <asm/apic.h> 21 #include <asm/i8259.h> 22 #include <asm/desc.h> 23 #include <asm/irq_remapping.h> 24 25 #include <asm/trace/irq_vectors.h> 26 27 struct apic_chip_data { 28 struct irq_cfg hw_irq_cfg; 29 unsigned int vector; 30 unsigned int prev_vector; 31 unsigned int cpu; 32 unsigned int prev_cpu; 33 unsigned int irq; 34 struct hlist_node clist; 35 unsigned int move_in_progress : 1, 36 is_managed : 1, 37 can_reserve : 1, 38 has_reserved : 1; 39 }; 40 41 struct irq_domain *x86_vector_domain; 42 EXPORT_SYMBOL_GPL(x86_vector_domain); 43 static DEFINE_RAW_SPINLOCK(vector_lock); 44 static cpumask_var_t vector_searchmask; 45 static struct irq_chip lapic_controller; 46 static struct irq_matrix *vector_matrix; 47 #ifdef CONFIG_SMP 48 static DEFINE_PER_CPU(struct hlist_head, cleanup_list); 49 #endif 50 51 void lock_vector_lock(void) 52 { 53 /* Used to the online set of cpus does not change 54 * during assign_irq_vector. 55 */ 56 raw_spin_lock(&vector_lock); 57 } 58 59 void unlock_vector_lock(void) 60 { 61 raw_spin_unlock(&vector_lock); 62 } 63 64 void init_irq_alloc_info(struct irq_alloc_info *info, 65 const struct cpumask *mask) 66 { 67 memset(info, 0, sizeof(*info)); 68 info->mask = mask; 69 } 70 71 void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src) 72 { 73 if (src) 74 *dst = *src; 75 else 76 memset(dst, 0, sizeof(*dst)); 77 } 78 79 static struct apic_chip_data *apic_chip_data(struct irq_data *irqd) 80 { 81 if (!irqd) 82 return NULL; 83 84 while (irqd->parent_data) 85 irqd = irqd->parent_data; 86 87 return irqd->chip_data; 88 } 89 90 struct irq_cfg *irqd_cfg(struct irq_data *irqd) 91 { 92 struct apic_chip_data *apicd = apic_chip_data(irqd); 93 94 return apicd ? &apicd->hw_irq_cfg : NULL; 95 } 96 EXPORT_SYMBOL_GPL(irqd_cfg); 97 98 struct irq_cfg *irq_cfg(unsigned int irq) 99 { 100 return irqd_cfg(irq_get_irq_data(irq)); 101 } 102 103 static struct apic_chip_data *alloc_apic_chip_data(int node) 104 { 105 struct apic_chip_data *apicd; 106 107 apicd = kzalloc_node(sizeof(*apicd), GFP_KERNEL, node); 108 if (apicd) 109 INIT_HLIST_NODE(&apicd->clist); 110 return apicd; 111 } 112 113 static void free_apic_chip_data(struct apic_chip_data *apicd) 114 { 115 kfree(apicd); 116 } 117 118 static void apic_update_irq_cfg(struct irq_data *irqd, unsigned int vector, 119 unsigned int cpu) 120 { 121 struct apic_chip_data *apicd = apic_chip_data(irqd); 122 123 lockdep_assert_held(&vector_lock); 124 125 apicd->hw_irq_cfg.vector = vector; 126 apicd->hw_irq_cfg.dest_apicid = apic->calc_dest_apicid(cpu); 127 irq_data_update_effective_affinity(irqd, cpumask_of(cpu)); 128 trace_vector_config(irqd->irq, vector, cpu, 129 apicd->hw_irq_cfg.dest_apicid); 130 } 131 132 static void apic_update_vector(struct irq_data *irqd, unsigned int newvec, 133 unsigned int newcpu) 134 { 135 struct apic_chip_data *apicd = apic_chip_data(irqd); 136 struct irq_desc *desc = irq_data_to_desc(irqd); 137 bool managed = irqd_affinity_is_managed(irqd); 138 139 lockdep_assert_held(&vector_lock); 140 141 trace_vector_update(irqd->irq, newvec, newcpu, apicd->vector, 142 apicd->cpu); 143 144 /* 145 * If there is no vector associated or if the associated vector is 146 * the shutdown vector, which is associated to make PCI/MSI 147 * shutdown mode work, then there is nothing to release. Clear out 148 * prev_vector for this and the offlined target case. 149 */ 150 apicd->prev_vector = 0; 151 if (!apicd->vector || apicd->vector == MANAGED_IRQ_SHUTDOWN_VECTOR) 152 goto setnew; 153 /* 154 * If the target CPU of the previous vector is online, then mark 155 * the vector as move in progress and store it for cleanup when the 156 * first interrupt on the new vector arrives. If the target CPU is 157 * offline then the regular release mechanism via the cleanup 158 * vector is not possible and the vector can be immediately freed 159 * in the underlying matrix allocator. 160 */ 161 if (cpu_online(apicd->cpu)) { 162 apicd->move_in_progress = true; 163 apicd->prev_vector = apicd->vector; 164 apicd->prev_cpu = apicd->cpu; 165 } else { 166 irq_matrix_free(vector_matrix, apicd->cpu, apicd->vector, 167 managed); 168 } 169 170 setnew: 171 apicd->vector = newvec; 172 apicd->cpu = newcpu; 173 BUG_ON(!IS_ERR_OR_NULL(per_cpu(vector_irq, newcpu)[newvec])); 174 per_cpu(vector_irq, newcpu)[newvec] = desc; 175 } 176 177 static void vector_assign_managed_shutdown(struct irq_data *irqd) 178 { 179 unsigned int cpu = cpumask_first(cpu_online_mask); 180 181 apic_update_irq_cfg(irqd, MANAGED_IRQ_SHUTDOWN_VECTOR, cpu); 182 } 183 184 static int reserve_managed_vector(struct irq_data *irqd) 185 { 186 const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd); 187 struct apic_chip_data *apicd = apic_chip_data(irqd); 188 unsigned long flags; 189 int ret; 190 191 raw_spin_lock_irqsave(&vector_lock, flags); 192 apicd->is_managed = true; 193 ret = irq_matrix_reserve_managed(vector_matrix, affmsk); 194 raw_spin_unlock_irqrestore(&vector_lock, flags); 195 trace_vector_reserve_managed(irqd->irq, ret); 196 return ret; 197 } 198 199 static void reserve_irq_vector_locked(struct irq_data *irqd) 200 { 201 struct apic_chip_data *apicd = apic_chip_data(irqd); 202 203 irq_matrix_reserve(vector_matrix); 204 apicd->can_reserve = true; 205 apicd->has_reserved = true; 206 irqd_set_can_reserve(irqd); 207 trace_vector_reserve(irqd->irq, 0); 208 vector_assign_managed_shutdown(irqd); 209 } 210 211 static int reserve_irq_vector(struct irq_data *irqd) 212 { 213 unsigned long flags; 214 215 raw_spin_lock_irqsave(&vector_lock, flags); 216 reserve_irq_vector_locked(irqd); 217 raw_spin_unlock_irqrestore(&vector_lock, flags); 218 return 0; 219 } 220 221 static int allocate_vector(struct irq_data *irqd, const struct cpumask *dest) 222 { 223 struct apic_chip_data *apicd = apic_chip_data(irqd); 224 bool resvd = apicd->has_reserved; 225 unsigned int cpu = apicd->cpu; 226 int vector = apicd->vector; 227 228 lockdep_assert_held(&vector_lock); 229 230 /* 231 * If the current target CPU is online and in the new requested 232 * affinity mask, there is no point in moving the interrupt from 233 * one CPU to another. 234 */ 235 if (vector && cpu_online(cpu) && cpumask_test_cpu(cpu, dest)) 236 return 0; 237 238 /* 239 * Careful here. @apicd might either have move_in_progress set or 240 * be enqueued for cleanup. Assigning a new vector would either 241 * leave a stale vector on some CPU around or in case of a pending 242 * cleanup corrupt the hlist. 243 */ 244 if (apicd->move_in_progress || !hlist_unhashed(&apicd->clist)) 245 return -EBUSY; 246 247 vector = irq_matrix_alloc(vector_matrix, dest, resvd, &cpu); 248 if (vector > 0) 249 apic_update_vector(irqd, vector, cpu); 250 trace_vector_alloc(irqd->irq, vector, resvd, vector); 251 return vector; 252 } 253 254 static int assign_vector_locked(struct irq_data *irqd, 255 const struct cpumask *dest) 256 { 257 struct apic_chip_data *apicd = apic_chip_data(irqd); 258 int vector = allocate_vector(irqd, dest); 259 260 if (vector < 0) 261 return vector; 262 263 apic_update_irq_cfg(irqd, apicd->vector, apicd->cpu); 264 return 0; 265 } 266 267 static int assign_irq_vector(struct irq_data *irqd, const struct cpumask *dest) 268 { 269 unsigned long flags; 270 int ret; 271 272 raw_spin_lock_irqsave(&vector_lock, flags); 273 cpumask_and(vector_searchmask, dest, cpu_online_mask); 274 ret = assign_vector_locked(irqd, vector_searchmask); 275 raw_spin_unlock_irqrestore(&vector_lock, flags); 276 return ret; 277 } 278 279 static int assign_irq_vector_any_locked(struct irq_data *irqd) 280 { 281 /* Get the affinity mask - either irq_default_affinity or (user) set */ 282 const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd); 283 int node = irq_data_get_node(irqd); 284 285 if (node == NUMA_NO_NODE) 286 goto all; 287 /* Try the intersection of @affmsk and node mask */ 288 cpumask_and(vector_searchmask, cpumask_of_node(node), affmsk); 289 if (!assign_vector_locked(irqd, vector_searchmask)) 290 return 0; 291 /* Try the node mask */ 292 if (!assign_vector_locked(irqd, cpumask_of_node(node))) 293 return 0; 294 all: 295 /* Try the full affinity mask */ 296 cpumask_and(vector_searchmask, affmsk, cpu_online_mask); 297 if (!assign_vector_locked(irqd, vector_searchmask)) 298 return 0; 299 /* Try the full online mask */ 300 return assign_vector_locked(irqd, cpu_online_mask); 301 } 302 303 static int 304 assign_irq_vector_policy(struct irq_data *irqd, struct irq_alloc_info *info) 305 { 306 if (irqd_affinity_is_managed(irqd)) 307 return reserve_managed_vector(irqd); 308 if (info->mask) 309 return assign_irq_vector(irqd, info->mask); 310 /* 311 * Make only a global reservation with no guarantee. A real vector 312 * is associated at activation time. 313 */ 314 return reserve_irq_vector(irqd); 315 } 316 317 static int 318 assign_managed_vector(struct irq_data *irqd, const struct cpumask *dest) 319 { 320 const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd); 321 struct apic_chip_data *apicd = apic_chip_data(irqd); 322 int vector, cpu; 323 324 cpumask_and(vector_searchmask, vector_searchmask, affmsk); 325 cpu = cpumask_first(vector_searchmask); 326 if (cpu >= nr_cpu_ids) 327 return -EINVAL; 328 /* set_affinity might call here for nothing */ 329 if (apicd->vector && cpumask_test_cpu(apicd->cpu, vector_searchmask)) 330 return 0; 331 vector = irq_matrix_alloc_managed(vector_matrix, cpu); 332 trace_vector_alloc_managed(irqd->irq, vector, vector); 333 if (vector < 0) 334 return vector; 335 apic_update_vector(irqd, vector, cpu); 336 apic_update_irq_cfg(irqd, vector, cpu); 337 return 0; 338 } 339 340 static void clear_irq_vector(struct irq_data *irqd) 341 { 342 struct apic_chip_data *apicd = apic_chip_data(irqd); 343 bool managed = irqd_affinity_is_managed(irqd); 344 unsigned int vector = apicd->vector; 345 346 lockdep_assert_held(&vector_lock); 347 348 if (!vector) 349 return; 350 351 trace_vector_clear(irqd->irq, vector, apicd->cpu, apicd->prev_vector, 352 apicd->prev_cpu); 353 354 per_cpu(vector_irq, apicd->cpu)[vector] = VECTOR_UNUSED; 355 irq_matrix_free(vector_matrix, apicd->cpu, vector, managed); 356 apicd->vector = 0; 357 358 /* Clean up move in progress */ 359 vector = apicd->prev_vector; 360 if (!vector) 361 return; 362 363 per_cpu(vector_irq, apicd->prev_cpu)[vector] = VECTOR_UNUSED; 364 irq_matrix_free(vector_matrix, apicd->prev_cpu, vector, managed); 365 apicd->prev_vector = 0; 366 apicd->move_in_progress = 0; 367 hlist_del_init(&apicd->clist); 368 } 369 370 static void x86_vector_deactivate(struct irq_domain *dom, struct irq_data *irqd) 371 { 372 struct apic_chip_data *apicd = apic_chip_data(irqd); 373 unsigned long flags; 374 375 trace_vector_deactivate(irqd->irq, apicd->is_managed, 376 apicd->can_reserve, false); 377 378 /* Regular fixed assigned interrupt */ 379 if (!apicd->is_managed && !apicd->can_reserve) 380 return; 381 /* If the interrupt has a global reservation, nothing to do */ 382 if (apicd->has_reserved) 383 return; 384 385 raw_spin_lock_irqsave(&vector_lock, flags); 386 clear_irq_vector(irqd); 387 if (apicd->can_reserve) 388 reserve_irq_vector_locked(irqd); 389 else 390 vector_assign_managed_shutdown(irqd); 391 raw_spin_unlock_irqrestore(&vector_lock, flags); 392 } 393 394 static int activate_reserved(struct irq_data *irqd) 395 { 396 struct apic_chip_data *apicd = apic_chip_data(irqd); 397 int ret; 398 399 ret = assign_irq_vector_any_locked(irqd); 400 if (!ret) { 401 apicd->has_reserved = false; 402 /* 403 * Core might have disabled reservation mode after 404 * allocating the irq descriptor. Ideally this should 405 * happen before allocation time, but that would require 406 * completely convoluted ways of transporting that 407 * information. 408 */ 409 if (!irqd_can_reserve(irqd)) 410 apicd->can_reserve = false; 411 } 412 return ret; 413 } 414 415 static int activate_managed(struct irq_data *irqd) 416 { 417 const struct cpumask *dest = irq_data_get_affinity_mask(irqd); 418 int ret; 419 420 cpumask_and(vector_searchmask, dest, cpu_online_mask); 421 if (WARN_ON_ONCE(cpumask_empty(vector_searchmask))) { 422 /* Something in the core code broke! Survive gracefully */ 423 pr_err("Managed startup for irq %u, but no CPU\n", irqd->irq); 424 return EINVAL; 425 } 426 427 ret = assign_managed_vector(irqd, vector_searchmask); 428 /* 429 * This should not happen. The vector reservation got buggered. Handle 430 * it gracefully. 431 */ 432 if (WARN_ON_ONCE(ret < 0)) { 433 pr_err("Managed startup irq %u, no vector available\n", 434 irqd->irq); 435 } 436 return ret; 437 } 438 439 static int x86_vector_activate(struct irq_domain *dom, struct irq_data *irqd, 440 bool reserve) 441 { 442 struct apic_chip_data *apicd = apic_chip_data(irqd); 443 unsigned long flags; 444 int ret = 0; 445 446 trace_vector_activate(irqd->irq, apicd->is_managed, 447 apicd->can_reserve, reserve); 448 449 /* Nothing to do for fixed assigned vectors */ 450 if (!apicd->can_reserve && !apicd->is_managed) 451 return 0; 452 453 raw_spin_lock_irqsave(&vector_lock, flags); 454 if (reserve || irqd_is_managed_and_shutdown(irqd)) 455 vector_assign_managed_shutdown(irqd); 456 else if (apicd->is_managed) 457 ret = activate_managed(irqd); 458 else if (apicd->has_reserved) 459 ret = activate_reserved(irqd); 460 raw_spin_unlock_irqrestore(&vector_lock, flags); 461 return ret; 462 } 463 464 static void vector_free_reserved_and_managed(struct irq_data *irqd) 465 { 466 const struct cpumask *dest = irq_data_get_affinity_mask(irqd); 467 struct apic_chip_data *apicd = apic_chip_data(irqd); 468 469 trace_vector_teardown(irqd->irq, apicd->is_managed, 470 apicd->has_reserved); 471 472 if (apicd->has_reserved) 473 irq_matrix_remove_reserved(vector_matrix); 474 if (apicd->is_managed) 475 irq_matrix_remove_managed(vector_matrix, dest); 476 } 477 478 static void x86_vector_free_irqs(struct irq_domain *domain, 479 unsigned int virq, unsigned int nr_irqs) 480 { 481 struct apic_chip_data *apicd; 482 struct irq_data *irqd; 483 unsigned long flags; 484 int i; 485 486 for (i = 0; i < nr_irqs; i++) { 487 irqd = irq_domain_get_irq_data(x86_vector_domain, virq + i); 488 if (irqd && irqd->chip_data) { 489 raw_spin_lock_irqsave(&vector_lock, flags); 490 clear_irq_vector(irqd); 491 vector_free_reserved_and_managed(irqd); 492 apicd = irqd->chip_data; 493 irq_domain_reset_irq_data(irqd); 494 raw_spin_unlock_irqrestore(&vector_lock, flags); 495 free_apic_chip_data(apicd); 496 } 497 } 498 } 499 500 static bool vector_configure_legacy(unsigned int virq, struct irq_data *irqd, 501 struct apic_chip_data *apicd) 502 { 503 unsigned long flags; 504 bool realloc = false; 505 506 apicd->vector = ISA_IRQ_VECTOR(virq); 507 apicd->cpu = 0; 508 509 raw_spin_lock_irqsave(&vector_lock, flags); 510 /* 511 * If the interrupt is activated, then it must stay at this vector 512 * position. That's usually the timer interrupt (0). 513 */ 514 if (irqd_is_activated(irqd)) { 515 trace_vector_setup(virq, true, 0); 516 apic_update_irq_cfg(irqd, apicd->vector, apicd->cpu); 517 } else { 518 /* Release the vector */ 519 apicd->can_reserve = true; 520 irqd_set_can_reserve(irqd); 521 clear_irq_vector(irqd); 522 realloc = true; 523 } 524 raw_spin_unlock_irqrestore(&vector_lock, flags); 525 return realloc; 526 } 527 528 static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, 529 unsigned int nr_irqs, void *arg) 530 { 531 struct irq_alloc_info *info = arg; 532 struct apic_chip_data *apicd; 533 struct irq_data *irqd; 534 int i, err, node; 535 536 if (disable_apic) 537 return -ENXIO; 538 539 /* Currently vector allocator can't guarantee contiguous allocations */ 540 if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1) 541 return -ENOSYS; 542 543 for (i = 0; i < nr_irqs; i++) { 544 irqd = irq_domain_get_irq_data(domain, virq + i); 545 BUG_ON(!irqd); 546 node = irq_data_get_node(irqd); 547 WARN_ON_ONCE(irqd->chip_data); 548 apicd = alloc_apic_chip_data(node); 549 if (!apicd) { 550 err = -ENOMEM; 551 goto error; 552 } 553 554 apicd->irq = virq + i; 555 irqd->chip = &lapic_controller; 556 irqd->chip_data = apicd; 557 irqd->hwirq = virq + i; 558 irqd_set_single_target(irqd); 559 /* 560 * Legacy vectors are already assigned when the IOAPIC 561 * takes them over. They stay on the same vector. This is 562 * required for check_timer() to work correctly as it might 563 * switch back to legacy mode. Only update the hardware 564 * config. 565 */ 566 if (info->flags & X86_IRQ_ALLOC_LEGACY) { 567 if (!vector_configure_legacy(virq + i, irqd, apicd)) 568 continue; 569 } 570 571 err = assign_irq_vector_policy(irqd, info); 572 trace_vector_setup(virq + i, false, err); 573 if (err) { 574 irqd->chip_data = NULL; 575 free_apic_chip_data(apicd); 576 goto error; 577 } 578 } 579 580 return 0; 581 582 error: 583 x86_vector_free_irqs(domain, virq, i); 584 return err; 585 } 586 587 #ifdef CONFIG_GENERIC_IRQ_DEBUGFS 588 static void x86_vector_debug_show(struct seq_file *m, struct irq_domain *d, 589 struct irq_data *irqd, int ind) 590 { 591 struct apic_chip_data apicd; 592 unsigned long flags; 593 int irq; 594 595 if (!irqd) { 596 irq_matrix_debug_show(m, vector_matrix, ind); 597 return; 598 } 599 600 irq = irqd->irq; 601 if (irq < nr_legacy_irqs() && !test_bit(irq, &io_apic_irqs)) { 602 seq_printf(m, "%*sVector: %5d\n", ind, "", ISA_IRQ_VECTOR(irq)); 603 seq_printf(m, "%*sTarget: Legacy PIC all CPUs\n", ind, ""); 604 return; 605 } 606 607 if (!irqd->chip_data) { 608 seq_printf(m, "%*sVector: Not assigned\n", ind, ""); 609 return; 610 } 611 612 raw_spin_lock_irqsave(&vector_lock, flags); 613 memcpy(&apicd, irqd->chip_data, sizeof(apicd)); 614 raw_spin_unlock_irqrestore(&vector_lock, flags); 615 616 seq_printf(m, "%*sVector: %5u\n", ind, "", apicd.vector); 617 seq_printf(m, "%*sTarget: %5u\n", ind, "", apicd.cpu); 618 if (apicd.prev_vector) { 619 seq_printf(m, "%*sPrevious vector: %5u\n", ind, "", apicd.prev_vector); 620 seq_printf(m, "%*sPrevious target: %5u\n", ind, "", apicd.prev_cpu); 621 } 622 seq_printf(m, "%*smove_in_progress: %u\n", ind, "", apicd.move_in_progress ? 1 : 0); 623 seq_printf(m, "%*sis_managed: %u\n", ind, "", apicd.is_managed ? 1 : 0); 624 seq_printf(m, "%*scan_reserve: %u\n", ind, "", apicd.can_reserve ? 1 : 0); 625 seq_printf(m, "%*shas_reserved: %u\n", ind, "", apicd.has_reserved ? 1 : 0); 626 seq_printf(m, "%*scleanup_pending: %u\n", ind, "", !hlist_unhashed(&apicd.clist)); 627 } 628 #endif 629 630 static const struct irq_domain_ops x86_vector_domain_ops = { 631 .alloc = x86_vector_alloc_irqs, 632 .free = x86_vector_free_irqs, 633 .activate = x86_vector_activate, 634 .deactivate = x86_vector_deactivate, 635 #ifdef CONFIG_GENERIC_IRQ_DEBUGFS 636 .debug_show = x86_vector_debug_show, 637 #endif 638 }; 639 640 int __init arch_probe_nr_irqs(void) 641 { 642 int nr; 643 644 if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) 645 nr_irqs = NR_VECTORS * nr_cpu_ids; 646 647 nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids; 648 #if defined(CONFIG_PCI_MSI) 649 /* 650 * for MSI and HT dyn irq 651 */ 652 if (gsi_top <= NR_IRQS_LEGACY) 653 nr += 8 * nr_cpu_ids; 654 else 655 nr += gsi_top * 16; 656 #endif 657 if (nr < nr_irqs) 658 nr_irqs = nr; 659 660 /* 661 * We don't know if PIC is present at this point so we need to do 662 * probe() to get the right number of legacy IRQs. 663 */ 664 return legacy_pic->probe(); 665 } 666 667 void lapic_assign_legacy_vector(unsigned int irq, bool replace) 668 { 669 /* 670 * Use assign system here so it wont get accounted as allocated 671 * and moveable in the cpu hotplug check and it prevents managed 672 * irq reservation from touching it. 673 */ 674 irq_matrix_assign_system(vector_matrix, ISA_IRQ_VECTOR(irq), replace); 675 } 676 677 void __init lapic_assign_system_vectors(void) 678 { 679 unsigned int i, vector = 0; 680 681 for_each_set_bit_from(vector, system_vectors, NR_VECTORS) 682 irq_matrix_assign_system(vector_matrix, vector, false); 683 684 if (nr_legacy_irqs() > 1) 685 lapic_assign_legacy_vector(PIC_CASCADE_IR, false); 686 687 /* System vectors are reserved, online it */ 688 irq_matrix_online(vector_matrix); 689 690 /* Mark the preallocated legacy interrupts */ 691 for (i = 0; i < nr_legacy_irqs(); i++) { 692 if (i != PIC_CASCADE_IR) 693 irq_matrix_assign(vector_matrix, ISA_IRQ_VECTOR(i)); 694 } 695 } 696 697 int __init arch_early_irq_init(void) 698 { 699 struct fwnode_handle *fn; 700 701 fn = irq_domain_alloc_named_fwnode("VECTOR"); 702 BUG_ON(!fn); 703 x86_vector_domain = irq_domain_create_tree(fn, &x86_vector_domain_ops, 704 NULL); 705 BUG_ON(x86_vector_domain == NULL); 706 irq_domain_free_fwnode(fn); 707 irq_set_default_host(x86_vector_domain); 708 709 arch_init_msi_domain(x86_vector_domain); 710 711 BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL)); 712 713 /* 714 * Allocate the vector matrix allocator data structure and limit the 715 * search area. 716 */ 717 vector_matrix = irq_alloc_matrix(NR_VECTORS, FIRST_EXTERNAL_VECTOR, 718 FIRST_SYSTEM_VECTOR); 719 BUG_ON(!vector_matrix); 720 721 return arch_early_ioapic_init(); 722 } 723 724 #ifdef CONFIG_SMP 725 726 static struct irq_desc *__setup_vector_irq(int vector) 727 { 728 int isairq = vector - ISA_IRQ_VECTOR(0); 729 730 /* Check whether the irq is in the legacy space */ 731 if (isairq < 0 || isairq >= nr_legacy_irqs()) 732 return VECTOR_UNUSED; 733 /* Check whether the irq is handled by the IOAPIC */ 734 if (test_bit(isairq, &io_apic_irqs)) 735 return VECTOR_UNUSED; 736 return irq_to_desc(isairq); 737 } 738 739 /* Online the local APIC infrastructure and initialize the vectors */ 740 void lapic_online(void) 741 { 742 unsigned int vector; 743 744 lockdep_assert_held(&vector_lock); 745 746 /* Online the vector matrix array for this CPU */ 747 irq_matrix_online(vector_matrix); 748 749 /* 750 * The interrupt affinity logic never targets interrupts to offline 751 * CPUs. The exception are the legacy PIC interrupts. In general 752 * they are only targeted to CPU0, but depending on the platform 753 * they can be distributed to any online CPU in hardware. The 754 * kernel has no influence on that. So all active legacy vectors 755 * must be installed on all CPUs. All non legacy interrupts can be 756 * cleared. 757 */ 758 for (vector = 0; vector < NR_VECTORS; vector++) 759 this_cpu_write(vector_irq[vector], __setup_vector_irq(vector)); 760 } 761 762 void lapic_offline(void) 763 { 764 lock_vector_lock(); 765 irq_matrix_offline(vector_matrix); 766 unlock_vector_lock(); 767 } 768 769 static int apic_set_affinity(struct irq_data *irqd, 770 const struct cpumask *dest, bool force) 771 { 772 struct apic_chip_data *apicd = apic_chip_data(irqd); 773 int err; 774 775 /* 776 * Core code can call here for inactive interrupts. For inactive 777 * interrupts which use managed or reservation mode there is no 778 * point in going through the vector assignment right now as the 779 * activation will assign a vector which fits the destination 780 * cpumask. Let the core code store the destination mask and be 781 * done with it. 782 */ 783 if (!irqd_is_activated(irqd) && 784 (apicd->is_managed || apicd->can_reserve)) 785 return IRQ_SET_MASK_OK; 786 787 raw_spin_lock(&vector_lock); 788 cpumask_and(vector_searchmask, dest, cpu_online_mask); 789 if (irqd_affinity_is_managed(irqd)) 790 err = assign_managed_vector(irqd, vector_searchmask); 791 else 792 err = assign_vector_locked(irqd, vector_searchmask); 793 raw_spin_unlock(&vector_lock); 794 return err ? err : IRQ_SET_MASK_OK; 795 } 796 797 #else 798 # define apic_set_affinity NULL 799 #endif 800 801 static int apic_retrigger_irq(struct irq_data *irqd) 802 { 803 struct apic_chip_data *apicd = apic_chip_data(irqd); 804 unsigned long flags; 805 806 raw_spin_lock_irqsave(&vector_lock, flags); 807 apic->send_IPI(apicd->cpu, apicd->vector); 808 raw_spin_unlock_irqrestore(&vector_lock, flags); 809 810 return 1; 811 } 812 813 void apic_ack_irq(struct irq_data *irqd) 814 { 815 irq_move_irq(irqd); 816 ack_APIC_irq(); 817 } 818 819 void apic_ack_edge(struct irq_data *irqd) 820 { 821 irq_complete_move(irqd_cfg(irqd)); 822 apic_ack_irq(irqd); 823 } 824 825 static struct irq_chip lapic_controller = { 826 .name = "APIC", 827 .irq_ack = apic_ack_edge, 828 .irq_set_affinity = apic_set_affinity, 829 .irq_retrigger = apic_retrigger_irq, 830 }; 831 832 #ifdef CONFIG_SMP 833 834 static void free_moved_vector(struct apic_chip_data *apicd) 835 { 836 unsigned int vector = apicd->prev_vector; 837 unsigned int cpu = apicd->prev_cpu; 838 bool managed = apicd->is_managed; 839 840 /* 841 * This should never happen. Managed interrupts are not 842 * migrated except on CPU down, which does not involve the 843 * cleanup vector. But try to keep the accounting correct 844 * nevertheless. 845 */ 846 WARN_ON_ONCE(managed); 847 848 trace_vector_free_moved(apicd->irq, cpu, vector, managed); 849 irq_matrix_free(vector_matrix, cpu, vector, managed); 850 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; 851 hlist_del_init(&apicd->clist); 852 apicd->prev_vector = 0; 853 apicd->move_in_progress = 0; 854 } 855 856 asmlinkage __visible void __irq_entry smp_irq_move_cleanup_interrupt(void) 857 { 858 struct hlist_head *clhead = this_cpu_ptr(&cleanup_list); 859 struct apic_chip_data *apicd; 860 struct hlist_node *tmp; 861 862 entering_ack_irq(); 863 /* Prevent vectors vanishing under us */ 864 raw_spin_lock(&vector_lock); 865 866 hlist_for_each_entry_safe(apicd, tmp, clhead, clist) { 867 unsigned int irr, vector = apicd->prev_vector; 868 869 /* 870 * Paranoia: Check if the vector that needs to be cleaned 871 * up is registered at the APICs IRR. If so, then this is 872 * not the best time to clean it up. Clean it up in the 873 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR 874 * to this CPU. IRQ_MOVE_CLEANUP_VECTOR is the lowest 875 * priority external vector, so on return from this 876 * interrupt the device interrupt will happen first. 877 */ 878 irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); 879 if (irr & (1U << (vector % 32))) { 880 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); 881 continue; 882 } 883 free_moved_vector(apicd); 884 } 885 886 raw_spin_unlock(&vector_lock); 887 exiting_irq(); 888 } 889 890 static void __send_cleanup_vector(struct apic_chip_data *apicd) 891 { 892 unsigned int cpu; 893 894 raw_spin_lock(&vector_lock); 895 apicd->move_in_progress = 0; 896 cpu = apicd->prev_cpu; 897 if (cpu_online(cpu)) { 898 hlist_add_head(&apicd->clist, per_cpu_ptr(&cleanup_list, cpu)); 899 apic->send_IPI(cpu, IRQ_MOVE_CLEANUP_VECTOR); 900 } else { 901 apicd->prev_vector = 0; 902 } 903 raw_spin_unlock(&vector_lock); 904 } 905 906 void send_cleanup_vector(struct irq_cfg *cfg) 907 { 908 struct apic_chip_data *apicd; 909 910 apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg); 911 if (apicd->move_in_progress) 912 __send_cleanup_vector(apicd); 913 } 914 915 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) 916 { 917 struct apic_chip_data *apicd; 918 919 apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg); 920 if (likely(!apicd->move_in_progress)) 921 return; 922 923 if (vector == apicd->vector && apicd->cpu == smp_processor_id()) 924 __send_cleanup_vector(apicd); 925 } 926 927 void irq_complete_move(struct irq_cfg *cfg) 928 { 929 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); 930 } 931 932 /* 933 * Called from fixup_irqs() with @desc->lock held and interrupts disabled. 934 */ 935 void irq_force_complete_move(struct irq_desc *desc) 936 { 937 struct apic_chip_data *apicd; 938 struct irq_data *irqd; 939 unsigned int vector; 940 941 /* 942 * The function is called for all descriptors regardless of which 943 * irqdomain they belong to. For example if an IRQ is provided by 944 * an irq_chip as part of a GPIO driver, the chip data for that 945 * descriptor is specific to the irq_chip in question. 946 * 947 * Check first that the chip_data is what we expect 948 * (apic_chip_data) before touching it any further. 949 */ 950 irqd = irq_domain_get_irq_data(x86_vector_domain, 951 irq_desc_get_irq(desc)); 952 if (!irqd) 953 return; 954 955 raw_spin_lock(&vector_lock); 956 apicd = apic_chip_data(irqd); 957 if (!apicd) 958 goto unlock; 959 960 /* 961 * If prev_vector is empty, no action required. 962 */ 963 vector = apicd->prev_vector; 964 if (!vector) 965 goto unlock; 966 967 /* 968 * This is tricky. If the cleanup of the old vector has not been 969 * done yet, then the following setaffinity call will fail with 970 * -EBUSY. This can leave the interrupt in a stale state. 971 * 972 * All CPUs are stuck in stop machine with interrupts disabled so 973 * calling __irq_complete_move() would be completely pointless. 974 * 975 * 1) The interrupt is in move_in_progress state. That means that we 976 * have not seen an interrupt since the io_apic was reprogrammed to 977 * the new vector. 978 * 979 * 2) The interrupt has fired on the new vector, but the cleanup IPIs 980 * have not been processed yet. 981 */ 982 if (apicd->move_in_progress) { 983 /* 984 * In theory there is a race: 985 * 986 * set_ioapic(new_vector) <-- Interrupt is raised before update 987 * is effective, i.e. it's raised on 988 * the old vector. 989 * 990 * So if the target cpu cannot handle that interrupt before 991 * the old vector is cleaned up, we get a spurious interrupt 992 * and in the worst case the ioapic irq line becomes stale. 993 * 994 * But in case of cpu hotplug this should be a non issue 995 * because if the affinity update happens right before all 996 * cpus rendevouz in stop machine, there is no way that the 997 * interrupt can be blocked on the target cpu because all cpus 998 * loops first with interrupts enabled in stop machine, so the 999 * old vector is not yet cleaned up when the interrupt fires. 1000 * 1001 * So the only way to run into this issue is if the delivery 1002 * of the interrupt on the apic/system bus would be delayed 1003 * beyond the point where the target cpu disables interrupts 1004 * in stop machine. I doubt that it can happen, but at least 1005 * there is a theroretical chance. Virtualization might be 1006 * able to expose this, but AFAICT the IOAPIC emulation is not 1007 * as stupid as the real hardware. 1008 * 1009 * Anyway, there is nothing we can do about that at this point 1010 * w/o refactoring the whole fixup_irq() business completely. 1011 * We print at least the irq number and the old vector number, 1012 * so we have the necessary information when a problem in that 1013 * area arises. 1014 */ 1015 pr_warn("IRQ fixup: irq %d move in progress, old vector %d\n", 1016 irqd->irq, vector); 1017 } 1018 free_moved_vector(apicd); 1019 unlock: 1020 raw_spin_unlock(&vector_lock); 1021 } 1022 1023 #ifdef CONFIG_HOTPLUG_CPU 1024 /* 1025 * Note, this is not accurate accounting, but at least good enough to 1026 * prevent that the actual interrupt move will run out of vectors. 1027 */ 1028 int lapic_can_unplug_cpu(void) 1029 { 1030 unsigned int rsvd, avl, tomove, cpu = smp_processor_id(); 1031 int ret = 0; 1032 1033 raw_spin_lock(&vector_lock); 1034 tomove = irq_matrix_allocated(vector_matrix); 1035 avl = irq_matrix_available(vector_matrix, true); 1036 if (avl < tomove) { 1037 pr_warn("CPU %u has %u vectors, %u available. Cannot disable CPU\n", 1038 cpu, tomove, avl); 1039 ret = -ENOSPC; 1040 goto out; 1041 } 1042 rsvd = irq_matrix_reserved(vector_matrix); 1043 if (avl < rsvd) { 1044 pr_warn("Reserved vectors %u > available %u. IRQ request may fail\n", 1045 rsvd, avl); 1046 } 1047 out: 1048 raw_spin_unlock(&vector_lock); 1049 return ret; 1050 } 1051 #endif /* HOTPLUG_CPU */ 1052 #endif /* SMP */ 1053 1054 static void __init print_APIC_field(int base) 1055 { 1056 int i; 1057 1058 printk(KERN_DEBUG); 1059 1060 for (i = 0; i < 8; i++) 1061 pr_cont("%08x", apic_read(base + i*0x10)); 1062 1063 pr_cont("\n"); 1064 } 1065 1066 static void __init print_local_APIC(void *dummy) 1067 { 1068 unsigned int i, v, ver, maxlvt; 1069 u64 icr; 1070 1071 pr_debug("printing local APIC contents on CPU#%d/%d:\n", 1072 smp_processor_id(), hard_smp_processor_id()); 1073 v = apic_read(APIC_ID); 1074 pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id()); 1075 v = apic_read(APIC_LVR); 1076 pr_info("... APIC VERSION: %08x\n", v); 1077 ver = GET_APIC_VERSION(v); 1078 maxlvt = lapic_get_maxlvt(); 1079 1080 v = apic_read(APIC_TASKPRI); 1081 pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); 1082 1083 /* !82489DX */ 1084 if (APIC_INTEGRATED(ver)) { 1085 if (!APIC_XAPIC(ver)) { 1086 v = apic_read(APIC_ARBPRI); 1087 pr_debug("... APIC ARBPRI: %08x (%02x)\n", 1088 v, v & APIC_ARBPRI_MASK); 1089 } 1090 v = apic_read(APIC_PROCPRI); 1091 pr_debug("... APIC PROCPRI: %08x\n", v); 1092 } 1093 1094 /* 1095 * Remote read supported only in the 82489DX and local APIC for 1096 * Pentium processors. 1097 */ 1098 if (!APIC_INTEGRATED(ver) || maxlvt == 3) { 1099 v = apic_read(APIC_RRR); 1100 pr_debug("... APIC RRR: %08x\n", v); 1101 } 1102 1103 v = apic_read(APIC_LDR); 1104 pr_debug("... APIC LDR: %08x\n", v); 1105 if (!x2apic_enabled()) { 1106 v = apic_read(APIC_DFR); 1107 pr_debug("... APIC DFR: %08x\n", v); 1108 } 1109 v = apic_read(APIC_SPIV); 1110 pr_debug("... APIC SPIV: %08x\n", v); 1111 1112 pr_debug("... APIC ISR field:\n"); 1113 print_APIC_field(APIC_ISR); 1114 pr_debug("... APIC TMR field:\n"); 1115 print_APIC_field(APIC_TMR); 1116 pr_debug("... APIC IRR field:\n"); 1117 print_APIC_field(APIC_IRR); 1118 1119 /* !82489DX */ 1120 if (APIC_INTEGRATED(ver)) { 1121 /* Due to the Pentium erratum 3AP. */ 1122 if (maxlvt > 3) 1123 apic_write(APIC_ESR, 0); 1124 1125 v = apic_read(APIC_ESR); 1126 pr_debug("... APIC ESR: %08x\n", v); 1127 } 1128 1129 icr = apic_icr_read(); 1130 pr_debug("... APIC ICR: %08x\n", (u32)icr); 1131 pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32)); 1132 1133 v = apic_read(APIC_LVTT); 1134 pr_debug("... APIC LVTT: %08x\n", v); 1135 1136 if (maxlvt > 3) { 1137 /* PC is LVT#4. */ 1138 v = apic_read(APIC_LVTPC); 1139 pr_debug("... APIC LVTPC: %08x\n", v); 1140 } 1141 v = apic_read(APIC_LVT0); 1142 pr_debug("... APIC LVT0: %08x\n", v); 1143 v = apic_read(APIC_LVT1); 1144 pr_debug("... APIC LVT1: %08x\n", v); 1145 1146 if (maxlvt > 2) { 1147 /* ERR is LVT#3. */ 1148 v = apic_read(APIC_LVTERR); 1149 pr_debug("... APIC LVTERR: %08x\n", v); 1150 } 1151 1152 v = apic_read(APIC_TMICT); 1153 pr_debug("... APIC TMICT: %08x\n", v); 1154 v = apic_read(APIC_TMCCT); 1155 pr_debug("... APIC TMCCT: %08x\n", v); 1156 v = apic_read(APIC_TDCR); 1157 pr_debug("... APIC TDCR: %08x\n", v); 1158 1159 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { 1160 v = apic_read(APIC_EFEAT); 1161 maxlvt = (v >> 16) & 0xff; 1162 pr_debug("... APIC EFEAT: %08x\n", v); 1163 v = apic_read(APIC_ECTRL); 1164 pr_debug("... APIC ECTRL: %08x\n", v); 1165 for (i = 0; i < maxlvt; i++) { 1166 v = apic_read(APIC_EILVTn(i)); 1167 pr_debug("... APIC EILVT%d: %08x\n", i, v); 1168 } 1169 } 1170 pr_cont("\n"); 1171 } 1172 1173 static void __init print_local_APICs(int maxcpu) 1174 { 1175 int cpu; 1176 1177 if (!maxcpu) 1178 return; 1179 1180 preempt_disable(); 1181 for_each_online_cpu(cpu) { 1182 if (cpu >= maxcpu) 1183 break; 1184 smp_call_function_single(cpu, print_local_APIC, NULL, 1); 1185 } 1186 preempt_enable(); 1187 } 1188 1189 static void __init print_PIC(void) 1190 { 1191 unsigned int v; 1192 unsigned long flags; 1193 1194 if (!nr_legacy_irqs()) 1195 return; 1196 1197 pr_debug("\nprinting PIC contents\n"); 1198 1199 raw_spin_lock_irqsave(&i8259A_lock, flags); 1200 1201 v = inb(0xa1) << 8 | inb(0x21); 1202 pr_debug("... PIC IMR: %04x\n", v); 1203 1204 v = inb(0xa0) << 8 | inb(0x20); 1205 pr_debug("... PIC IRR: %04x\n", v); 1206 1207 outb(0x0b, 0xa0); 1208 outb(0x0b, 0x20); 1209 v = inb(0xa0) << 8 | inb(0x20); 1210 outb(0x0a, 0xa0); 1211 outb(0x0a, 0x20); 1212 1213 raw_spin_unlock_irqrestore(&i8259A_lock, flags); 1214 1215 pr_debug("... PIC ISR: %04x\n", v); 1216 1217 v = inb(0x4d1) << 8 | inb(0x4d0); 1218 pr_debug("... PIC ELCR: %04x\n", v); 1219 } 1220 1221 static int show_lapic __initdata = 1; 1222 static __init int setup_show_lapic(char *arg) 1223 { 1224 int num = -1; 1225 1226 if (strcmp(arg, "all") == 0) { 1227 show_lapic = CONFIG_NR_CPUS; 1228 } else { 1229 get_option(&arg, &num); 1230 if (num >= 0) 1231 show_lapic = num; 1232 } 1233 1234 return 1; 1235 } 1236 __setup("show_lapic=", setup_show_lapic); 1237 1238 static int __init print_ICs(void) 1239 { 1240 if (apic_verbosity == APIC_QUIET) 1241 return 0; 1242 1243 print_PIC(); 1244 1245 /* don't print out if apic is not there */ 1246 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) 1247 return 0; 1248 1249 print_local_APICs(show_lapic); 1250 print_IO_APICs(); 1251 1252 return 0; 1253 } 1254 1255 late_initcall(print_ICs); 1256