xref: /linux/arch/x86/kernel/apic/msi.c (revision b6ebbac51bedf9e98e837688bc838f400196da5e) 
1 /*
2  * Support of MSI, HPET and DMAR interrupts.
3  *
4  * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5  *	Moved from arch/x86/kernel/apic/io_apic.c.
6  * Jiang Liu <jiang.liu@linux.intel.com>
7  *	Convert to hierarchical irqdomain
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  */
13 #include <linux/mm.h>
14 #include <linux/interrupt.h>
15 #include <linux/pci.h>
16 #include <linux/dmar.h>
17 #include <linux/hpet.h>
18 #include <linux/msi.h>
19 #include <asm/irqdomain.h>
20 #include <asm/msidef.h>
21 #include <asm/hpet.h>
22 #include <asm/hw_irq.h>
23 #include <asm/apic.h>
24 #include <asm/irq_remapping.h>
25 
26 static struct irq_domain *msi_default_domain;
27 
28 static void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
29 {
30 	struct irq_cfg *cfg = irqd_cfg(data);
31 
32 	msg->address_hi = MSI_ADDR_BASE_HI;
33 
34 	if (x2apic_enabled())
35 		msg->address_hi |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid);
36 
37 	msg->address_lo =
38 		MSI_ADDR_BASE_LO |
39 		((apic->irq_dest_mode == 0) ?
40 			MSI_ADDR_DEST_MODE_PHYSICAL :
41 			MSI_ADDR_DEST_MODE_LOGICAL) |
42 		((apic->irq_delivery_mode != dest_LowestPrio) ?
43 			MSI_ADDR_REDIRECTION_CPU :
44 			MSI_ADDR_REDIRECTION_LOWPRI) |
45 		MSI_ADDR_DEST_ID(cfg->dest_apicid);
46 
47 	msg->data =
48 		MSI_DATA_TRIGGER_EDGE |
49 		MSI_DATA_LEVEL_ASSERT |
50 		((apic->irq_delivery_mode != dest_LowestPrio) ?
51 			MSI_DATA_DELIVERY_FIXED :
52 			MSI_DATA_DELIVERY_LOWPRI) |
53 		MSI_DATA_VECTOR(cfg->vector);
54 }
55 
56 /*
57  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
58  * which implement the MSI or MSI-X Capability Structure.
59  */
60 static struct irq_chip pci_msi_controller = {
61 	.name			= "PCI-MSI",
62 	.irq_unmask		= pci_msi_unmask_irq,
63 	.irq_mask		= pci_msi_mask_irq,
64 	.irq_ack		= irq_chip_ack_parent,
65 	.irq_retrigger		= irq_chip_retrigger_hierarchy,
66 	.irq_compose_msi_msg	= irq_msi_compose_msg,
67 	.flags			= IRQCHIP_SKIP_SET_WAKE,
68 };
69 
70 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
71 {
72 	struct irq_domain *domain;
73 	struct irq_alloc_info info;
74 
75 	init_irq_alloc_info(&info, NULL);
76 	info.type = X86_IRQ_ALLOC_TYPE_MSI;
77 	info.msi_dev = dev;
78 
79 	domain = irq_remapping_get_irq_domain(&info);
80 	if (domain == NULL)
81 		domain = msi_default_domain;
82 	if (domain == NULL)
83 		return -ENOSYS;
84 
85 	return pci_msi_domain_alloc_irqs(domain, dev, nvec, type);
86 }
87 
88 void native_teardown_msi_irq(unsigned int irq)
89 {
90 	irq_domain_free_irqs(irq, 1);
91 }
92 
93 static irq_hw_number_t pci_msi_get_hwirq(struct msi_domain_info *info,
94 					 msi_alloc_info_t *arg)
95 {
96 	return arg->msi_hwirq;
97 }
98 
99 int pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec,
100 		    msi_alloc_info_t *arg)
101 {
102 	struct pci_dev *pdev = to_pci_dev(dev);
103 	struct msi_desc *desc = first_pci_msi_entry(pdev);
104 
105 	init_irq_alloc_info(arg, NULL);
106 	arg->msi_dev = pdev;
107 	if (desc->msi_attrib.is_msix) {
108 		arg->type = X86_IRQ_ALLOC_TYPE_MSIX;
109 	} else {
110 		arg->type = X86_IRQ_ALLOC_TYPE_MSI;
111 		arg->flags |= X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
112 	}
113 
114 	return 0;
115 }
116 EXPORT_SYMBOL_GPL(pci_msi_prepare);
117 
118 void pci_msi_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc)
119 {
120 	arg->msi_hwirq = pci_msi_domain_calc_hwirq(arg->msi_dev, desc);
121 }
122 EXPORT_SYMBOL_GPL(pci_msi_set_desc);
123 
124 static struct msi_domain_ops pci_msi_domain_ops = {
125 	.get_hwirq	= pci_msi_get_hwirq,
126 	.msi_prepare	= pci_msi_prepare,
127 	.set_desc	= pci_msi_set_desc,
128 };
129 
130 static struct msi_domain_info pci_msi_domain_info = {
131 	.flags		= MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
132 			  MSI_FLAG_PCI_MSIX,
133 	.ops		= &pci_msi_domain_ops,
134 	.chip		= &pci_msi_controller,
135 	.handler	= handle_edge_irq,
136 	.handler_name	= "edge",
137 };
138 
139 void arch_init_msi_domain(struct irq_domain *parent)
140 {
141 	if (disable_apic)
142 		return;
143 
144 	msi_default_domain = pci_msi_create_irq_domain(NULL,
145 					&pci_msi_domain_info, parent);
146 	if (!msi_default_domain)
147 		pr_warn("failed to initialize irqdomain for MSI/MSI-x.\n");
148 }
149 
150 #ifdef CONFIG_IRQ_REMAP
151 static struct irq_chip pci_msi_ir_controller = {
152 	.name			= "IR-PCI-MSI",
153 	.irq_unmask		= pci_msi_unmask_irq,
154 	.irq_mask		= pci_msi_mask_irq,
155 	.irq_ack		= irq_chip_ack_parent,
156 	.irq_retrigger		= irq_chip_retrigger_hierarchy,
157 	.irq_set_vcpu_affinity	= irq_chip_set_vcpu_affinity_parent,
158 	.flags			= IRQCHIP_SKIP_SET_WAKE,
159 };
160 
161 static struct msi_domain_info pci_msi_ir_domain_info = {
162 	.flags		= MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
163 			  MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX,
164 	.ops		= &pci_msi_domain_ops,
165 	.chip		= &pci_msi_ir_controller,
166 	.handler	= handle_edge_irq,
167 	.handler_name	= "edge",
168 };
169 
170 struct irq_domain *arch_create_msi_irq_domain(struct irq_domain *parent)
171 {
172 	return pci_msi_create_irq_domain(NULL, &pci_msi_ir_domain_info, parent);
173 }
174 #endif
175 
176 #ifdef CONFIG_DMAR_TABLE
177 static void dmar_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
178 {
179 	dmar_msi_write(data->irq, msg);
180 }
181 
182 static struct irq_chip dmar_msi_controller = {
183 	.name			= "DMAR-MSI",
184 	.irq_unmask		= dmar_msi_unmask,
185 	.irq_mask		= dmar_msi_mask,
186 	.irq_ack		= irq_chip_ack_parent,
187 	.irq_set_affinity	= msi_domain_set_affinity,
188 	.irq_retrigger		= irq_chip_retrigger_hierarchy,
189 	.irq_compose_msi_msg	= irq_msi_compose_msg,
190 	.irq_write_msi_msg	= dmar_msi_write_msg,
191 	.flags			= IRQCHIP_SKIP_SET_WAKE,
192 };
193 
194 static irq_hw_number_t dmar_msi_get_hwirq(struct msi_domain_info *info,
195 					  msi_alloc_info_t *arg)
196 {
197 	return arg->dmar_id;
198 }
199 
200 static int dmar_msi_init(struct irq_domain *domain,
201 			 struct msi_domain_info *info, unsigned int virq,
202 			 irq_hw_number_t hwirq, msi_alloc_info_t *arg)
203 {
204 	irq_domain_set_info(domain, virq, arg->dmar_id, info->chip, NULL,
205 			    handle_edge_irq, arg->dmar_data, "edge");
206 
207 	return 0;
208 }
209 
210 static struct msi_domain_ops dmar_msi_domain_ops = {
211 	.get_hwirq	= dmar_msi_get_hwirq,
212 	.msi_init	= dmar_msi_init,
213 };
214 
215 static struct msi_domain_info dmar_msi_domain_info = {
216 	.ops		= &dmar_msi_domain_ops,
217 	.chip		= &dmar_msi_controller,
218 };
219 
220 static struct irq_domain *dmar_get_irq_domain(void)
221 {
222 	static struct irq_domain *dmar_domain;
223 	static DEFINE_MUTEX(dmar_lock);
224 
225 	mutex_lock(&dmar_lock);
226 	if (dmar_domain == NULL)
227 		dmar_domain = msi_create_irq_domain(NULL, &dmar_msi_domain_info,
228 						    x86_vector_domain);
229 	mutex_unlock(&dmar_lock);
230 
231 	return dmar_domain;
232 }
233 
234 int dmar_alloc_hwirq(int id, int node, void *arg)
235 {
236 	struct irq_domain *domain = dmar_get_irq_domain();
237 	struct irq_alloc_info info;
238 
239 	if (!domain)
240 		return -1;
241 
242 	init_irq_alloc_info(&info, NULL);
243 	info.type = X86_IRQ_ALLOC_TYPE_DMAR;
244 	info.dmar_id = id;
245 	info.dmar_data = arg;
246 
247 	return irq_domain_alloc_irqs(domain, 1, node, &info);
248 }
249 
250 void dmar_free_hwirq(int irq)
251 {
252 	irq_domain_free_irqs(irq, 1);
253 }
254 #endif
255 
256 /*
257  * MSI message composition
258  */
259 #ifdef CONFIG_HPET_TIMER
260 static inline int hpet_dev_id(struct irq_domain *domain)
261 {
262 	struct msi_domain_info *info = msi_get_domain_info(domain);
263 
264 	return (int)(long)info->data;
265 }
266 
267 static void hpet_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
268 {
269 	hpet_msi_write(irq_data_get_irq_handler_data(data), msg);
270 }
271 
272 static struct irq_chip hpet_msi_controller = {
273 	.name = "HPET-MSI",
274 	.irq_unmask = hpet_msi_unmask,
275 	.irq_mask = hpet_msi_mask,
276 	.irq_ack = irq_chip_ack_parent,
277 	.irq_set_affinity = msi_domain_set_affinity,
278 	.irq_retrigger = irq_chip_retrigger_hierarchy,
279 	.irq_compose_msi_msg = irq_msi_compose_msg,
280 	.irq_write_msi_msg = hpet_msi_write_msg,
281 	.flags = IRQCHIP_SKIP_SET_WAKE,
282 };
283 
284 static irq_hw_number_t hpet_msi_get_hwirq(struct msi_domain_info *info,
285 					  msi_alloc_info_t *arg)
286 {
287 	return arg->hpet_index;
288 }
289 
290 static int hpet_msi_init(struct irq_domain *domain,
291 			 struct msi_domain_info *info, unsigned int virq,
292 			 irq_hw_number_t hwirq, msi_alloc_info_t *arg)
293 {
294 	irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
295 	irq_domain_set_info(domain, virq, arg->hpet_index, info->chip, NULL,
296 			    handle_edge_irq, arg->hpet_data, "edge");
297 
298 	return 0;
299 }
300 
301 static void hpet_msi_free(struct irq_domain *domain,
302 			  struct msi_domain_info *info, unsigned int virq)
303 {
304 	irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT);
305 }
306 
307 static struct msi_domain_ops hpet_msi_domain_ops = {
308 	.get_hwirq	= hpet_msi_get_hwirq,
309 	.msi_init	= hpet_msi_init,
310 	.msi_free	= hpet_msi_free,
311 };
312 
313 static struct msi_domain_info hpet_msi_domain_info = {
314 	.ops		= &hpet_msi_domain_ops,
315 	.chip		= &hpet_msi_controller,
316 };
317 
318 struct irq_domain *hpet_create_irq_domain(int hpet_id)
319 {
320 	struct irq_domain *parent;
321 	struct irq_alloc_info info;
322 	struct msi_domain_info *domain_info;
323 
324 	if (x86_vector_domain == NULL)
325 		return NULL;
326 
327 	domain_info = kzalloc(sizeof(*domain_info), GFP_KERNEL);
328 	if (!domain_info)
329 		return NULL;
330 
331 	*domain_info = hpet_msi_domain_info;
332 	domain_info->data = (void *)(long)hpet_id;
333 
334 	init_irq_alloc_info(&info, NULL);
335 	info.type = X86_IRQ_ALLOC_TYPE_HPET;
336 	info.hpet_id = hpet_id;
337 	parent = irq_remapping_get_ir_irq_domain(&info);
338 	if (parent == NULL)
339 		parent = x86_vector_domain;
340 	else
341 		hpet_msi_controller.name = "IR-HPET-MSI";
342 
343 	return msi_create_irq_domain(NULL, domain_info, parent);
344 }
345 
346 int hpet_assign_irq(struct irq_domain *domain, struct hpet_dev *dev,
347 		    int dev_num)
348 {
349 	struct irq_alloc_info info;
350 
351 	init_irq_alloc_info(&info, NULL);
352 	info.type = X86_IRQ_ALLOC_TYPE_HPET;
353 	info.hpet_data = dev;
354 	info.hpet_id = hpet_dev_id(domain);
355 	info.hpet_index = dev_num;
356 
357 	return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, &info);
358 }
359 #endif
360