xref: /linux/arch/x86/kernel/apic/io_apic.c (revision bfd5bb6f90af092aa345b15cd78143956a13c2a8)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  *	Intel IO-APIC support for multi-Pentium hosts.
4  *
5  *	Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6  *
7  *	Many thanks to Stig Venaas for trying out countless experimental
8  *	patches and reporting/debugging problems patiently!
9  *
10  *	(c) 1999, Multiple IO-APIC support, developed by
11  *	Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
12  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
13  *	further tested and cleaned up by Zach Brown <zab@redhat.com>
14  *	and Ingo Molnar <mingo@redhat.com>
15  *
16  *	Fixes
17  *	Maciej W. Rozycki	:	Bits for genuine 82489DX APICs;
18  *					thanks to Eric Gilmore
19  *					and Rolf G. Tews
20  *					for testing these extensively
21  *	Paul Diefenbaugh	:	Added full ACPI support
22  *
23  * Historical information which is worth to be preserved:
24  *
25  * - SiS APIC rmw bug:
26  *
27  *	We used to have a workaround for a bug in SiS chips which
28  *	required to rewrite the index register for a read-modify-write
29  *	operation as the chip lost the index information which was
30  *	setup for the read already. We cache the data now, so that
31  *	workaround has been removed.
32  */
33 
34 #include <linux/mm.h>
35 #include <linux/interrupt.h>
36 #include <linux/init.h>
37 #include <linux/delay.h>
38 #include <linux/sched.h>
39 #include <linux/pci.h>
40 #include <linux/mc146818rtc.h>
41 #include <linux/compiler.h>
42 #include <linux/acpi.h>
43 #include <linux/export.h>
44 #include <linux/syscore_ops.h>
45 #include <linux/freezer.h>
46 #include <linux/kthread.h>
47 #include <linux/jiffies.h>	/* time_after() */
48 #include <linux/slab.h>
49 #include <linux/bootmem.h>
50 
51 #include <asm/irqdomain.h>
52 #include <asm/io.h>
53 #include <asm/smp.h>
54 #include <asm/cpu.h>
55 #include <asm/desc.h>
56 #include <asm/proto.h>
57 #include <asm/acpi.h>
58 #include <asm/dma.h>
59 #include <asm/timer.h>
60 #include <asm/i8259.h>
61 #include <asm/setup.h>
62 #include <asm/irq_remapping.h>
63 #include <asm/hw_irq.h>
64 
65 #include <asm/apic.h>
66 
67 #define	for_each_ioapic(idx)		\
68 	for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
69 #define	for_each_ioapic_reverse(idx)	\
70 	for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
71 #define	for_each_pin(idx, pin)		\
72 	for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
73 #define	for_each_ioapic_pin(idx, pin)	\
74 	for_each_ioapic((idx))		\
75 		for_each_pin((idx), (pin))
76 #define for_each_irq_pin(entry, head) \
77 	list_for_each_entry(entry, &head, list)
78 
79 static DEFINE_RAW_SPINLOCK(ioapic_lock);
80 static DEFINE_MUTEX(ioapic_mutex);
81 static unsigned int ioapic_dynirq_base;
82 static int ioapic_initialized;
83 
84 struct irq_pin_list {
85 	struct list_head list;
86 	int apic, pin;
87 };
88 
89 struct mp_chip_data {
90 	struct list_head irq_2_pin;
91 	struct IO_APIC_route_entry entry;
92 	int trigger;
93 	int polarity;
94 	u32 count;
95 	bool isa_irq;
96 };
97 
98 struct mp_ioapic_gsi {
99 	u32 gsi_base;
100 	u32 gsi_end;
101 };
102 
103 static struct ioapic {
104 	/*
105 	 * # of IRQ routing registers
106 	 */
107 	int nr_registers;
108 	/*
109 	 * Saved state during suspend/resume, or while enabling intr-remap.
110 	 */
111 	struct IO_APIC_route_entry *saved_registers;
112 	/* I/O APIC config */
113 	struct mpc_ioapic mp_config;
114 	/* IO APIC gsi routing info */
115 	struct mp_ioapic_gsi  gsi_config;
116 	struct ioapic_domain_cfg irqdomain_cfg;
117 	struct irq_domain *irqdomain;
118 	struct resource *iomem_res;
119 } ioapics[MAX_IO_APICS];
120 
121 #define mpc_ioapic_ver(ioapic_idx)	ioapics[ioapic_idx].mp_config.apicver
122 
123 int mpc_ioapic_id(int ioapic_idx)
124 {
125 	return ioapics[ioapic_idx].mp_config.apicid;
126 }
127 
128 unsigned int mpc_ioapic_addr(int ioapic_idx)
129 {
130 	return ioapics[ioapic_idx].mp_config.apicaddr;
131 }
132 
133 static inline struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
134 {
135 	return &ioapics[ioapic_idx].gsi_config;
136 }
137 
138 static inline int mp_ioapic_pin_count(int ioapic)
139 {
140 	struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
141 
142 	return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
143 }
144 
145 static inline u32 mp_pin_to_gsi(int ioapic, int pin)
146 {
147 	return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin;
148 }
149 
150 static inline bool mp_is_legacy_irq(int irq)
151 {
152 	return irq >= 0 && irq < nr_legacy_irqs();
153 }
154 
155 /*
156  * Initialize all legacy IRQs and all pins on the first IOAPIC
157  * if we have legacy interrupt controller. Kernel boot option "pirq="
158  * may rely on non-legacy pins on the first IOAPIC.
159  */
160 static inline int mp_init_irq_at_boot(int ioapic, int irq)
161 {
162 	if (!nr_legacy_irqs())
163 		return 0;
164 
165 	return ioapic == 0 || mp_is_legacy_irq(irq);
166 }
167 
168 static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic)
169 {
170 	return ioapics[ioapic].irqdomain;
171 }
172 
173 int nr_ioapics;
174 
175 /* The one past the highest gsi number used */
176 u32 gsi_top;
177 
178 /* MP IRQ source entries */
179 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
180 
181 /* # of MP IRQ source entries */
182 int mp_irq_entries;
183 
184 #ifdef CONFIG_EISA
185 int mp_bus_id_to_type[MAX_MP_BUSSES];
186 #endif
187 
188 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
189 
190 int skip_ioapic_setup;
191 
192 /**
193  * disable_ioapic_support() - disables ioapic support at runtime
194  */
195 void disable_ioapic_support(void)
196 {
197 #ifdef CONFIG_PCI
198 	noioapicquirk = 1;
199 	noioapicreroute = -1;
200 #endif
201 	skip_ioapic_setup = 1;
202 }
203 
204 static int __init parse_noapic(char *str)
205 {
206 	/* disable IO-APIC */
207 	disable_ioapic_support();
208 	return 0;
209 }
210 early_param("noapic", parse_noapic);
211 
212 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
213 void mp_save_irq(struct mpc_intsrc *m)
214 {
215 	int i;
216 
217 	apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
218 		" IRQ %02x, APIC ID %x, APIC INT %02x\n",
219 		m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
220 		m->srcbusirq, m->dstapic, m->dstirq);
221 
222 	for (i = 0; i < mp_irq_entries; i++) {
223 		if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
224 			return;
225 	}
226 
227 	memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
228 	if (++mp_irq_entries == MAX_IRQ_SOURCES)
229 		panic("Max # of irq sources exceeded!!\n");
230 }
231 
232 static void alloc_ioapic_saved_registers(int idx)
233 {
234 	size_t size;
235 
236 	if (ioapics[idx].saved_registers)
237 		return;
238 
239 	size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers;
240 	ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL);
241 	if (!ioapics[idx].saved_registers)
242 		pr_err("IOAPIC %d: suspend/resume impossible!\n", idx);
243 }
244 
245 static void free_ioapic_saved_registers(int idx)
246 {
247 	kfree(ioapics[idx].saved_registers);
248 	ioapics[idx].saved_registers = NULL;
249 }
250 
251 int __init arch_early_ioapic_init(void)
252 {
253 	int i;
254 
255 	if (!nr_legacy_irqs())
256 		io_apic_irqs = ~0UL;
257 
258 	for_each_ioapic(i)
259 		alloc_ioapic_saved_registers(i);
260 
261 	return 0;
262 }
263 
264 struct io_apic {
265 	unsigned int index;
266 	unsigned int unused[3];
267 	unsigned int data;
268 	unsigned int unused2[11];
269 	unsigned int eoi;
270 };
271 
272 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
273 {
274 	return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
275 		+ (mpc_ioapic_addr(idx) & ~PAGE_MASK);
276 }
277 
278 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
279 {
280 	struct io_apic __iomem *io_apic = io_apic_base(apic);
281 	writel(vector, &io_apic->eoi);
282 }
283 
284 unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
285 {
286 	struct io_apic __iomem *io_apic = io_apic_base(apic);
287 	writel(reg, &io_apic->index);
288 	return readl(&io_apic->data);
289 }
290 
291 static void io_apic_write(unsigned int apic, unsigned int reg,
292 			  unsigned int value)
293 {
294 	struct io_apic __iomem *io_apic = io_apic_base(apic);
295 
296 	writel(reg, &io_apic->index);
297 	writel(value, &io_apic->data);
298 }
299 
300 union entry_union {
301 	struct { u32 w1, w2; };
302 	struct IO_APIC_route_entry entry;
303 };
304 
305 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
306 {
307 	union entry_union eu;
308 
309 	eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
310 	eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
311 
312 	return eu.entry;
313 }
314 
315 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
316 {
317 	union entry_union eu;
318 	unsigned long flags;
319 
320 	raw_spin_lock_irqsave(&ioapic_lock, flags);
321 	eu.entry = __ioapic_read_entry(apic, pin);
322 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
323 
324 	return eu.entry;
325 }
326 
327 /*
328  * When we write a new IO APIC routing entry, we need to write the high
329  * word first! If the mask bit in the low word is clear, we will enable
330  * the interrupt, and we need to make sure the entry is fully populated
331  * before that happens.
332  */
333 static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
334 {
335 	union entry_union eu = {{0, 0}};
336 
337 	eu.entry = e;
338 	io_apic_write(apic, 0x11 + 2*pin, eu.w2);
339 	io_apic_write(apic, 0x10 + 2*pin, eu.w1);
340 }
341 
342 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
343 {
344 	unsigned long flags;
345 
346 	raw_spin_lock_irqsave(&ioapic_lock, flags);
347 	__ioapic_write_entry(apic, pin, e);
348 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
349 }
350 
351 /*
352  * When we mask an IO APIC routing entry, we need to write the low
353  * word first, in order to set the mask bit before we change the
354  * high bits!
355  */
356 static void ioapic_mask_entry(int apic, int pin)
357 {
358 	unsigned long flags;
359 	union entry_union eu = { .entry.mask = IOAPIC_MASKED };
360 
361 	raw_spin_lock_irqsave(&ioapic_lock, flags);
362 	io_apic_write(apic, 0x10 + 2*pin, eu.w1);
363 	io_apic_write(apic, 0x11 + 2*pin, eu.w2);
364 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
365 }
366 
367 /*
368  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
369  * shared ISA-space IRQs, so we have to support them. We are super
370  * fast in the common case, and fast for shared ISA-space IRQs.
371  */
372 static int __add_pin_to_irq_node(struct mp_chip_data *data,
373 				 int node, int apic, int pin)
374 {
375 	struct irq_pin_list *entry;
376 
377 	/* don't allow duplicates */
378 	for_each_irq_pin(entry, data->irq_2_pin)
379 		if (entry->apic == apic && entry->pin == pin)
380 			return 0;
381 
382 	entry = kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node);
383 	if (!entry) {
384 		pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
385 		       node, apic, pin);
386 		return -ENOMEM;
387 	}
388 	entry->apic = apic;
389 	entry->pin = pin;
390 	list_add_tail(&entry->list, &data->irq_2_pin);
391 
392 	return 0;
393 }
394 
395 static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin)
396 {
397 	struct irq_pin_list *tmp, *entry;
398 
399 	list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list)
400 		if (entry->apic == apic && entry->pin == pin) {
401 			list_del(&entry->list);
402 			kfree(entry);
403 			return;
404 		}
405 }
406 
407 static void add_pin_to_irq_node(struct mp_chip_data *data,
408 				int node, int apic, int pin)
409 {
410 	if (__add_pin_to_irq_node(data, node, apic, pin))
411 		panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
412 }
413 
414 /*
415  * Reroute an IRQ to a different pin.
416  */
417 static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int node,
418 					   int oldapic, int oldpin,
419 					   int newapic, int newpin)
420 {
421 	struct irq_pin_list *entry;
422 
423 	for_each_irq_pin(entry, data->irq_2_pin) {
424 		if (entry->apic == oldapic && entry->pin == oldpin) {
425 			entry->apic = newapic;
426 			entry->pin = newpin;
427 			/* every one is different, right? */
428 			return;
429 		}
430 	}
431 
432 	/* old apic/pin didn't exist, so just add new ones */
433 	add_pin_to_irq_node(data, node, newapic, newpin);
434 }
435 
436 static void io_apic_modify_irq(struct mp_chip_data *data,
437 			       int mask_and, int mask_or,
438 			       void (*final)(struct irq_pin_list *entry))
439 {
440 	union entry_union eu;
441 	struct irq_pin_list *entry;
442 
443 	eu.entry = data->entry;
444 	eu.w1 &= mask_and;
445 	eu.w1 |= mask_or;
446 	data->entry = eu.entry;
447 
448 	for_each_irq_pin(entry, data->irq_2_pin) {
449 		io_apic_write(entry->apic, 0x10 + 2 * entry->pin, eu.w1);
450 		if (final)
451 			final(entry);
452 	}
453 }
454 
455 static void io_apic_sync(struct irq_pin_list *entry)
456 {
457 	/*
458 	 * Synchronize the IO-APIC and the CPU by doing
459 	 * a dummy read from the IO-APIC
460 	 */
461 	struct io_apic __iomem *io_apic;
462 
463 	io_apic = io_apic_base(entry->apic);
464 	readl(&io_apic->data);
465 }
466 
467 static void mask_ioapic_irq(struct irq_data *irq_data)
468 {
469 	struct mp_chip_data *data = irq_data->chip_data;
470 	unsigned long flags;
471 
472 	raw_spin_lock_irqsave(&ioapic_lock, flags);
473 	io_apic_modify_irq(data, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
474 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
475 }
476 
477 static void __unmask_ioapic(struct mp_chip_data *data)
478 {
479 	io_apic_modify_irq(data, ~IO_APIC_REDIR_MASKED, 0, NULL);
480 }
481 
482 static void unmask_ioapic_irq(struct irq_data *irq_data)
483 {
484 	struct mp_chip_data *data = irq_data->chip_data;
485 	unsigned long flags;
486 
487 	raw_spin_lock_irqsave(&ioapic_lock, flags);
488 	__unmask_ioapic(data);
489 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
490 }
491 
492 /*
493  * IO-APIC versions below 0x20 don't support EOI register.
494  * For the record, here is the information about various versions:
495  *     0Xh     82489DX
496  *     1Xh     I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
497  *     2Xh     I/O(x)APIC which is PCI 2.2 Compliant
498  *     30h-FFh Reserved
499  *
500  * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
501  * version as 0x2. This is an error with documentation and these ICH chips
502  * use io-apic's of version 0x20.
503  *
504  * For IO-APIC's with EOI register, we use that to do an explicit EOI.
505  * Otherwise, we simulate the EOI message manually by changing the trigger
506  * mode to edge and then back to level, with RTE being masked during this.
507  */
508 static void __eoi_ioapic_pin(int apic, int pin, int vector)
509 {
510 	if (mpc_ioapic_ver(apic) >= 0x20) {
511 		io_apic_eoi(apic, vector);
512 	} else {
513 		struct IO_APIC_route_entry entry, entry1;
514 
515 		entry = entry1 = __ioapic_read_entry(apic, pin);
516 
517 		/*
518 		 * Mask the entry and change the trigger mode to edge.
519 		 */
520 		entry1.mask = IOAPIC_MASKED;
521 		entry1.trigger = IOAPIC_EDGE;
522 
523 		__ioapic_write_entry(apic, pin, entry1);
524 
525 		/*
526 		 * Restore the previous level triggered entry.
527 		 */
528 		__ioapic_write_entry(apic, pin, entry);
529 	}
530 }
531 
532 static void eoi_ioapic_pin(int vector, struct mp_chip_data *data)
533 {
534 	unsigned long flags;
535 	struct irq_pin_list *entry;
536 
537 	raw_spin_lock_irqsave(&ioapic_lock, flags);
538 	for_each_irq_pin(entry, data->irq_2_pin)
539 		__eoi_ioapic_pin(entry->apic, entry->pin, vector);
540 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
541 }
542 
543 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
544 {
545 	struct IO_APIC_route_entry entry;
546 
547 	/* Check delivery_mode to be sure we're not clearing an SMI pin */
548 	entry = ioapic_read_entry(apic, pin);
549 	if (entry.delivery_mode == dest_SMI)
550 		return;
551 
552 	/*
553 	 * Make sure the entry is masked and re-read the contents to check
554 	 * if it is a level triggered pin and if the remote-IRR is set.
555 	 */
556 	if (entry.mask == IOAPIC_UNMASKED) {
557 		entry.mask = IOAPIC_MASKED;
558 		ioapic_write_entry(apic, pin, entry);
559 		entry = ioapic_read_entry(apic, pin);
560 	}
561 
562 	if (entry.irr) {
563 		unsigned long flags;
564 
565 		/*
566 		 * Make sure the trigger mode is set to level. Explicit EOI
567 		 * doesn't clear the remote-IRR if the trigger mode is not
568 		 * set to level.
569 		 */
570 		if (entry.trigger == IOAPIC_EDGE) {
571 			entry.trigger = IOAPIC_LEVEL;
572 			ioapic_write_entry(apic, pin, entry);
573 		}
574 		raw_spin_lock_irqsave(&ioapic_lock, flags);
575 		__eoi_ioapic_pin(apic, pin, entry.vector);
576 		raw_spin_unlock_irqrestore(&ioapic_lock, flags);
577 	}
578 
579 	/*
580 	 * Clear the rest of the bits in the IO-APIC RTE except for the mask
581 	 * bit.
582 	 */
583 	ioapic_mask_entry(apic, pin);
584 	entry = ioapic_read_entry(apic, pin);
585 	if (entry.irr)
586 		pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
587 		       mpc_ioapic_id(apic), pin);
588 }
589 
590 void clear_IO_APIC (void)
591 {
592 	int apic, pin;
593 
594 	for_each_ioapic_pin(apic, pin)
595 		clear_IO_APIC_pin(apic, pin);
596 }
597 
598 #ifdef CONFIG_X86_32
599 /*
600  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
601  * specific CPU-side IRQs.
602  */
603 
604 #define MAX_PIRQS 8
605 static int pirq_entries[MAX_PIRQS] = {
606 	[0 ... MAX_PIRQS - 1] = -1
607 };
608 
609 static int __init ioapic_pirq_setup(char *str)
610 {
611 	int i, max;
612 	int ints[MAX_PIRQS+1];
613 
614 	get_options(str, ARRAY_SIZE(ints), ints);
615 
616 	apic_printk(APIC_VERBOSE, KERN_INFO
617 			"PIRQ redirection, working around broken MP-BIOS.\n");
618 	max = MAX_PIRQS;
619 	if (ints[0] < MAX_PIRQS)
620 		max = ints[0];
621 
622 	for (i = 0; i < max; i++) {
623 		apic_printk(APIC_VERBOSE, KERN_DEBUG
624 				"... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
625 		/*
626 		 * PIRQs are mapped upside down, usually.
627 		 */
628 		pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
629 	}
630 	return 1;
631 }
632 
633 __setup("pirq=", ioapic_pirq_setup);
634 #endif /* CONFIG_X86_32 */
635 
636 /*
637  * Saves all the IO-APIC RTE's
638  */
639 int save_ioapic_entries(void)
640 {
641 	int apic, pin;
642 	int err = 0;
643 
644 	for_each_ioapic(apic) {
645 		if (!ioapics[apic].saved_registers) {
646 			err = -ENOMEM;
647 			continue;
648 		}
649 
650 		for_each_pin(apic, pin)
651 			ioapics[apic].saved_registers[pin] =
652 				ioapic_read_entry(apic, pin);
653 	}
654 
655 	return err;
656 }
657 
658 /*
659  * Mask all IO APIC entries.
660  */
661 void mask_ioapic_entries(void)
662 {
663 	int apic, pin;
664 
665 	for_each_ioapic(apic) {
666 		if (!ioapics[apic].saved_registers)
667 			continue;
668 
669 		for_each_pin(apic, pin) {
670 			struct IO_APIC_route_entry entry;
671 
672 			entry = ioapics[apic].saved_registers[pin];
673 			if (entry.mask == IOAPIC_UNMASKED) {
674 				entry.mask = IOAPIC_MASKED;
675 				ioapic_write_entry(apic, pin, entry);
676 			}
677 		}
678 	}
679 }
680 
681 /*
682  * Restore IO APIC entries which was saved in the ioapic structure.
683  */
684 int restore_ioapic_entries(void)
685 {
686 	int apic, pin;
687 
688 	for_each_ioapic(apic) {
689 		if (!ioapics[apic].saved_registers)
690 			continue;
691 
692 		for_each_pin(apic, pin)
693 			ioapic_write_entry(apic, pin,
694 					   ioapics[apic].saved_registers[pin]);
695 	}
696 	return 0;
697 }
698 
699 /*
700  * Find the IRQ entry number of a certain pin.
701  */
702 static int find_irq_entry(int ioapic_idx, int pin, int type)
703 {
704 	int i;
705 
706 	for (i = 0; i < mp_irq_entries; i++)
707 		if (mp_irqs[i].irqtype == type &&
708 		    (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
709 		     mp_irqs[i].dstapic == MP_APIC_ALL) &&
710 		    mp_irqs[i].dstirq == pin)
711 			return i;
712 
713 	return -1;
714 }
715 
716 /*
717  * Find the pin to which IRQ[irq] (ISA) is connected
718  */
719 static int __init find_isa_irq_pin(int irq, int type)
720 {
721 	int i;
722 
723 	for (i = 0; i < mp_irq_entries; i++) {
724 		int lbus = mp_irqs[i].srcbus;
725 
726 		if (test_bit(lbus, mp_bus_not_pci) &&
727 		    (mp_irqs[i].irqtype == type) &&
728 		    (mp_irqs[i].srcbusirq == irq))
729 
730 			return mp_irqs[i].dstirq;
731 	}
732 	return -1;
733 }
734 
735 static int __init find_isa_irq_apic(int irq, int type)
736 {
737 	int i;
738 
739 	for (i = 0; i < mp_irq_entries; i++) {
740 		int lbus = mp_irqs[i].srcbus;
741 
742 		if (test_bit(lbus, mp_bus_not_pci) &&
743 		    (mp_irqs[i].irqtype == type) &&
744 		    (mp_irqs[i].srcbusirq == irq))
745 			break;
746 	}
747 
748 	if (i < mp_irq_entries) {
749 		int ioapic_idx;
750 
751 		for_each_ioapic(ioapic_idx)
752 			if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
753 				return ioapic_idx;
754 	}
755 
756 	return -1;
757 }
758 
759 #ifdef CONFIG_EISA
760 /*
761  * EISA Edge/Level control register, ELCR
762  */
763 static int EISA_ELCR(unsigned int irq)
764 {
765 	if (irq < nr_legacy_irqs()) {
766 		unsigned int port = 0x4d0 + (irq >> 3);
767 		return (inb(port) >> (irq & 7)) & 1;
768 	}
769 	apic_printk(APIC_VERBOSE, KERN_INFO
770 			"Broken MPtable reports ISA irq %d\n", irq);
771 	return 0;
772 }
773 
774 #endif
775 
776 /* ISA interrupts are always active high edge triggered,
777  * when listed as conforming in the MP table. */
778 
779 #define default_ISA_trigger(idx)	(IOAPIC_EDGE)
780 #define default_ISA_polarity(idx)	(IOAPIC_POL_HIGH)
781 
782 /* EISA interrupts are always polarity zero and can be edge or level
783  * trigger depending on the ELCR value.  If an interrupt is listed as
784  * EISA conforming in the MP table, that means its trigger type must
785  * be read in from the ELCR */
786 
787 #define default_EISA_trigger(idx)	(EISA_ELCR(mp_irqs[idx].srcbusirq))
788 #define default_EISA_polarity(idx)	default_ISA_polarity(idx)
789 
790 /* PCI interrupts are always active low level triggered,
791  * when listed as conforming in the MP table. */
792 
793 #define default_PCI_trigger(idx)	(IOAPIC_LEVEL)
794 #define default_PCI_polarity(idx)	(IOAPIC_POL_LOW)
795 
796 static int irq_polarity(int idx)
797 {
798 	int bus = mp_irqs[idx].srcbus;
799 
800 	/*
801 	 * Determine IRQ line polarity (high active or low active):
802 	 */
803 	switch (mp_irqs[idx].irqflag & MP_IRQPOL_MASK) {
804 	case MP_IRQPOL_DEFAULT:
805 		/* conforms to spec, ie. bus-type dependent polarity */
806 		if (test_bit(bus, mp_bus_not_pci))
807 			return default_ISA_polarity(idx);
808 		else
809 			return default_PCI_polarity(idx);
810 	case MP_IRQPOL_ACTIVE_HIGH:
811 		return IOAPIC_POL_HIGH;
812 	case MP_IRQPOL_RESERVED:
813 		pr_warn("IOAPIC: Invalid polarity: 2, defaulting to low\n");
814 	case MP_IRQPOL_ACTIVE_LOW:
815 	default: /* Pointless default required due to do gcc stupidity */
816 		return IOAPIC_POL_LOW;
817 	}
818 }
819 
820 #ifdef CONFIG_EISA
821 static int eisa_irq_trigger(int idx, int bus, int trigger)
822 {
823 	switch (mp_bus_id_to_type[bus]) {
824 	case MP_BUS_PCI:
825 	case MP_BUS_ISA:
826 		return trigger;
827 	case MP_BUS_EISA:
828 		return default_EISA_trigger(idx);
829 	}
830 	pr_warn("IOAPIC: Invalid srcbus: %d defaulting to level\n", bus);
831 	return IOAPIC_LEVEL;
832 }
833 #else
834 static inline int eisa_irq_trigger(int idx, int bus, int trigger)
835 {
836 	return trigger;
837 }
838 #endif
839 
840 static int irq_trigger(int idx)
841 {
842 	int bus = mp_irqs[idx].srcbus;
843 	int trigger;
844 
845 	/*
846 	 * Determine IRQ trigger mode (edge or level sensitive):
847 	 */
848 	switch (mp_irqs[idx].irqflag & MP_IRQTRIG_MASK) {
849 	case MP_IRQTRIG_DEFAULT:
850 		/* conforms to spec, ie. bus-type dependent trigger mode */
851 		if (test_bit(bus, mp_bus_not_pci))
852 			trigger = default_ISA_trigger(idx);
853 		else
854 			trigger = default_PCI_trigger(idx);
855 		/* Take EISA into account */
856 		return eisa_irq_trigger(idx, bus, trigger);
857 	case MP_IRQTRIG_EDGE:
858 		return IOAPIC_EDGE;
859 	case MP_IRQTRIG_RESERVED:
860 		pr_warn("IOAPIC: Invalid trigger mode 2 defaulting to level\n");
861 	case MP_IRQTRIG_LEVEL:
862 	default: /* Pointless default required due to do gcc stupidity */
863 		return IOAPIC_LEVEL;
864 	}
865 }
866 
867 void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node,
868 			   int trigger, int polarity)
869 {
870 	init_irq_alloc_info(info, NULL);
871 	info->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
872 	info->ioapic_node = node;
873 	info->ioapic_trigger = trigger;
874 	info->ioapic_polarity = polarity;
875 	info->ioapic_valid = 1;
876 }
877 
878 #ifndef CONFIG_ACPI
879 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity);
880 #endif
881 
882 static void ioapic_copy_alloc_attr(struct irq_alloc_info *dst,
883 				   struct irq_alloc_info *src,
884 				   u32 gsi, int ioapic_idx, int pin)
885 {
886 	int trigger, polarity;
887 
888 	copy_irq_alloc_info(dst, src);
889 	dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
890 	dst->ioapic_id = mpc_ioapic_id(ioapic_idx);
891 	dst->ioapic_pin = pin;
892 	dst->ioapic_valid = 1;
893 	if (src && src->ioapic_valid) {
894 		dst->ioapic_node = src->ioapic_node;
895 		dst->ioapic_trigger = src->ioapic_trigger;
896 		dst->ioapic_polarity = src->ioapic_polarity;
897 	} else {
898 		dst->ioapic_node = NUMA_NO_NODE;
899 		if (acpi_get_override_irq(gsi, &trigger, &polarity) >= 0) {
900 			dst->ioapic_trigger = trigger;
901 			dst->ioapic_polarity = polarity;
902 		} else {
903 			/*
904 			 * PCI interrupts are always active low level
905 			 * triggered.
906 			 */
907 			dst->ioapic_trigger = IOAPIC_LEVEL;
908 			dst->ioapic_polarity = IOAPIC_POL_LOW;
909 		}
910 	}
911 }
912 
913 static int ioapic_alloc_attr_node(struct irq_alloc_info *info)
914 {
915 	return (info && info->ioapic_valid) ? info->ioapic_node : NUMA_NO_NODE;
916 }
917 
918 static void mp_register_handler(unsigned int irq, unsigned long trigger)
919 {
920 	irq_flow_handler_t hdl;
921 	bool fasteoi;
922 
923 	if (trigger) {
924 		irq_set_status_flags(irq, IRQ_LEVEL);
925 		fasteoi = true;
926 	} else {
927 		irq_clear_status_flags(irq, IRQ_LEVEL);
928 		fasteoi = false;
929 	}
930 
931 	hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
932 	__irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge");
933 }
934 
935 static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info)
936 {
937 	struct mp_chip_data *data = irq_get_chip_data(irq);
938 
939 	/*
940 	 * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger
941 	 * and polarity attirbutes. So allow the first user to reprogram the
942 	 * pin with real trigger and polarity attributes.
943 	 */
944 	if (irq < nr_legacy_irqs() && data->count == 1) {
945 		if (info->ioapic_trigger != data->trigger)
946 			mp_register_handler(irq, info->ioapic_trigger);
947 		data->entry.trigger = data->trigger = info->ioapic_trigger;
948 		data->entry.polarity = data->polarity = info->ioapic_polarity;
949 	}
950 
951 	return data->trigger == info->ioapic_trigger &&
952 	       data->polarity == info->ioapic_polarity;
953 }
954 
955 static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi,
956 				 struct irq_alloc_info *info)
957 {
958 	bool legacy = false;
959 	int irq = -1;
960 	int type = ioapics[ioapic].irqdomain_cfg.type;
961 
962 	switch (type) {
963 	case IOAPIC_DOMAIN_LEGACY:
964 		/*
965 		 * Dynamically allocate IRQ number for non-ISA IRQs in the first
966 		 * 16 GSIs on some weird platforms.
967 		 */
968 		if (!ioapic_initialized || gsi >= nr_legacy_irqs())
969 			irq = gsi;
970 		legacy = mp_is_legacy_irq(irq);
971 		break;
972 	case IOAPIC_DOMAIN_STRICT:
973 		irq = gsi;
974 		break;
975 	case IOAPIC_DOMAIN_DYNAMIC:
976 		break;
977 	default:
978 		WARN(1, "ioapic: unknown irqdomain type %d\n", type);
979 		return -1;
980 	}
981 
982 	return __irq_domain_alloc_irqs(domain, irq, 1,
983 				       ioapic_alloc_attr_node(info),
984 				       info, legacy, NULL);
985 }
986 
987 /*
988  * Need special handling for ISA IRQs because there may be multiple IOAPIC pins
989  * sharing the same ISA IRQ number and irqdomain only supports 1:1 mapping
990  * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are
991  * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
992  * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and
993  * some BIOSes may use MP Interrupt Source records to override IRQ numbers for
994  * PIRQs instead of reprogramming the interrupt routing logic. Thus there may be
995  * multiple pins sharing the same legacy IRQ number when ACPI is disabled.
996  */
997 static int alloc_isa_irq_from_domain(struct irq_domain *domain,
998 				     int irq, int ioapic, int pin,
999 				     struct irq_alloc_info *info)
1000 {
1001 	struct mp_chip_data *data;
1002 	struct irq_data *irq_data = irq_get_irq_data(irq);
1003 	int node = ioapic_alloc_attr_node(info);
1004 
1005 	/*
1006 	 * Legacy ISA IRQ has already been allocated, just add pin to
1007 	 * the pin list assoicated with this IRQ and program the IOAPIC
1008 	 * entry. The IOAPIC entry
1009 	 */
1010 	if (irq_data && irq_data->parent_data) {
1011 		if (!mp_check_pin_attr(irq, info))
1012 			return -EBUSY;
1013 		if (__add_pin_to_irq_node(irq_data->chip_data, node, ioapic,
1014 					  info->ioapic_pin))
1015 			return -ENOMEM;
1016 	} else {
1017 		info->flags |= X86_IRQ_ALLOC_LEGACY;
1018 		irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true,
1019 					      NULL);
1020 		if (irq >= 0) {
1021 			irq_data = irq_domain_get_irq_data(domain, irq);
1022 			data = irq_data->chip_data;
1023 			data->isa_irq = true;
1024 		}
1025 	}
1026 
1027 	return irq;
1028 }
1029 
1030 static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
1031 			     unsigned int flags, struct irq_alloc_info *info)
1032 {
1033 	int irq;
1034 	bool legacy = false;
1035 	struct irq_alloc_info tmp;
1036 	struct mp_chip_data *data;
1037 	struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
1038 
1039 	if (!domain)
1040 		return -ENOSYS;
1041 
1042 	if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) {
1043 		irq = mp_irqs[idx].srcbusirq;
1044 		legacy = mp_is_legacy_irq(irq);
1045 	}
1046 
1047 	mutex_lock(&ioapic_mutex);
1048 	if (!(flags & IOAPIC_MAP_ALLOC)) {
1049 		if (!legacy) {
1050 			irq = irq_find_mapping(domain, pin);
1051 			if (irq == 0)
1052 				irq = -ENOENT;
1053 		}
1054 	} else {
1055 		ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin);
1056 		if (legacy)
1057 			irq = alloc_isa_irq_from_domain(domain, irq,
1058 							ioapic, pin, &tmp);
1059 		else if ((irq = irq_find_mapping(domain, pin)) == 0)
1060 			irq = alloc_irq_from_domain(domain, ioapic, gsi, &tmp);
1061 		else if (!mp_check_pin_attr(irq, &tmp))
1062 			irq = -EBUSY;
1063 		if (irq >= 0) {
1064 			data = irq_get_chip_data(irq);
1065 			data->count++;
1066 		}
1067 	}
1068 	mutex_unlock(&ioapic_mutex);
1069 
1070 	return irq;
1071 }
1072 
1073 static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags)
1074 {
1075 	u32 gsi = mp_pin_to_gsi(ioapic, pin);
1076 
1077 	/*
1078 	 * Debugging check, we are in big trouble if this message pops up!
1079 	 */
1080 	if (mp_irqs[idx].dstirq != pin)
1081 		pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
1082 
1083 #ifdef CONFIG_X86_32
1084 	/*
1085 	 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1086 	 */
1087 	if ((pin >= 16) && (pin <= 23)) {
1088 		if (pirq_entries[pin-16] != -1) {
1089 			if (!pirq_entries[pin-16]) {
1090 				apic_printk(APIC_VERBOSE, KERN_DEBUG
1091 						"disabling PIRQ%d\n", pin-16);
1092 			} else {
1093 				int irq = pirq_entries[pin-16];
1094 				apic_printk(APIC_VERBOSE, KERN_DEBUG
1095 						"using PIRQ%d -> IRQ %d\n",
1096 						pin-16, irq);
1097 				return irq;
1098 			}
1099 		}
1100 	}
1101 #endif
1102 
1103 	return  mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL);
1104 }
1105 
1106 int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, struct irq_alloc_info *info)
1107 {
1108 	int ioapic, pin, idx;
1109 
1110 	ioapic = mp_find_ioapic(gsi);
1111 	if (ioapic < 0)
1112 		return -ENODEV;
1113 
1114 	pin = mp_find_ioapic_pin(ioapic, gsi);
1115 	idx = find_irq_entry(ioapic, pin, mp_INT);
1116 	if ((flags & IOAPIC_MAP_CHECK) && idx < 0)
1117 		return -ENODEV;
1118 
1119 	return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info);
1120 }
1121 
1122 void mp_unmap_irq(int irq)
1123 {
1124 	struct irq_data *irq_data = irq_get_irq_data(irq);
1125 	struct mp_chip_data *data;
1126 
1127 	if (!irq_data || !irq_data->domain)
1128 		return;
1129 
1130 	data = irq_data->chip_data;
1131 	if (!data || data->isa_irq)
1132 		return;
1133 
1134 	mutex_lock(&ioapic_mutex);
1135 	if (--data->count == 0)
1136 		irq_domain_free_irqs(irq, 1);
1137 	mutex_unlock(&ioapic_mutex);
1138 }
1139 
1140 /*
1141  * Find a specific PCI IRQ entry.
1142  * Not an __init, possibly needed by modules
1143  */
1144 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1145 {
1146 	int irq, i, best_ioapic = -1, best_idx = -1;
1147 
1148 	apic_printk(APIC_DEBUG,
1149 		    "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1150 		    bus, slot, pin);
1151 	if (test_bit(bus, mp_bus_not_pci)) {
1152 		apic_printk(APIC_VERBOSE,
1153 			    "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1154 		return -1;
1155 	}
1156 
1157 	for (i = 0; i < mp_irq_entries; i++) {
1158 		int lbus = mp_irqs[i].srcbus;
1159 		int ioapic_idx, found = 0;
1160 
1161 		if (bus != lbus || mp_irqs[i].irqtype != mp_INT ||
1162 		    slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f))
1163 			continue;
1164 
1165 		for_each_ioapic(ioapic_idx)
1166 			if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1167 			    mp_irqs[i].dstapic == MP_APIC_ALL) {
1168 				found = 1;
1169 				break;
1170 			}
1171 		if (!found)
1172 			continue;
1173 
1174 		/* Skip ISA IRQs */
1175 		irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0);
1176 		if (irq > 0 && !IO_APIC_IRQ(irq))
1177 			continue;
1178 
1179 		if (pin == (mp_irqs[i].srcbusirq & 3)) {
1180 			best_idx = i;
1181 			best_ioapic = ioapic_idx;
1182 			goto out;
1183 		}
1184 
1185 		/*
1186 		 * Use the first all-but-pin matching entry as a
1187 		 * best-guess fuzzy result for broken mptables.
1188 		 */
1189 		if (best_idx < 0) {
1190 			best_idx = i;
1191 			best_ioapic = ioapic_idx;
1192 		}
1193 	}
1194 	if (best_idx < 0)
1195 		return -1;
1196 
1197 out:
1198 	return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq,
1199 			 IOAPIC_MAP_ALLOC);
1200 }
1201 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1202 
1203 static struct irq_chip ioapic_chip, ioapic_ir_chip;
1204 
1205 static void __init setup_IO_APIC_irqs(void)
1206 {
1207 	unsigned int ioapic, pin;
1208 	int idx;
1209 
1210 	apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1211 
1212 	for_each_ioapic_pin(ioapic, pin) {
1213 		idx = find_irq_entry(ioapic, pin, mp_INT);
1214 		if (idx < 0)
1215 			apic_printk(APIC_VERBOSE,
1216 				    KERN_DEBUG " apic %d pin %d not connected\n",
1217 				    mpc_ioapic_id(ioapic), pin);
1218 		else
1219 			pin_2_irq(idx, ioapic, pin,
1220 				  ioapic ? 0 : IOAPIC_MAP_ALLOC);
1221 	}
1222 }
1223 
1224 void ioapic_zap_locks(void)
1225 {
1226 	raw_spin_lock_init(&ioapic_lock);
1227 }
1228 
1229 static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
1230 {
1231 	int i;
1232 	char buf[256];
1233 	struct IO_APIC_route_entry entry;
1234 	struct IR_IO_APIC_route_entry *ir_entry = (void *)&entry;
1235 
1236 	printk(KERN_DEBUG "IOAPIC %d:\n", apic);
1237 	for (i = 0; i <= nr_entries; i++) {
1238 		entry = ioapic_read_entry(apic, i);
1239 		snprintf(buf, sizeof(buf),
1240 			 " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)",
1241 			 i,
1242 			 entry.mask == IOAPIC_MASKED ? "disabled" : "enabled ",
1243 			 entry.trigger == IOAPIC_LEVEL ? "level" : "edge ",
1244 			 entry.polarity == IOAPIC_POL_LOW ? "low " : "high",
1245 			 entry.vector, entry.irr, entry.delivery_status);
1246 		if (ir_entry->format)
1247 			printk(KERN_DEBUG "%s, remapped, I(%04X),  Z(%X)\n",
1248 			       buf, (ir_entry->index2 << 15) | ir_entry->index,
1249 			       ir_entry->zero);
1250 		else
1251 			printk(KERN_DEBUG "%s, %s, D(%02X), M(%1d)\n",
1252 			       buf,
1253 			       entry.dest_mode == IOAPIC_DEST_MODE_LOGICAL ?
1254 			       "logical " : "physical",
1255 			       entry.dest, entry.delivery_mode);
1256 	}
1257 }
1258 
1259 static void __init print_IO_APIC(int ioapic_idx)
1260 {
1261 	union IO_APIC_reg_00 reg_00;
1262 	union IO_APIC_reg_01 reg_01;
1263 	union IO_APIC_reg_02 reg_02;
1264 	union IO_APIC_reg_03 reg_03;
1265 	unsigned long flags;
1266 
1267 	raw_spin_lock_irqsave(&ioapic_lock, flags);
1268 	reg_00.raw = io_apic_read(ioapic_idx, 0);
1269 	reg_01.raw = io_apic_read(ioapic_idx, 1);
1270 	if (reg_01.bits.version >= 0x10)
1271 		reg_02.raw = io_apic_read(ioapic_idx, 2);
1272 	if (reg_01.bits.version >= 0x20)
1273 		reg_03.raw = io_apic_read(ioapic_idx, 3);
1274 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1275 
1276 	printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1277 	printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1278 	printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1279 	printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1280 	printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1281 
1282 	printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1283 	printk(KERN_DEBUG ".......     : max redirection entries: %02X\n",
1284 		reg_01.bits.entries);
1285 
1286 	printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1287 	printk(KERN_DEBUG ".......     : IO APIC version: %02X\n",
1288 		reg_01.bits.version);
1289 
1290 	/*
1291 	 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1292 	 * but the value of reg_02 is read as the previous read register
1293 	 * value, so ignore it if reg_02 == reg_01.
1294 	 */
1295 	if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1296 		printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1297 		printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1298 	}
1299 
1300 	/*
1301 	 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1302 	 * or reg_03, but the value of reg_0[23] is read as the previous read
1303 	 * register value, so ignore it if reg_03 == reg_0[12].
1304 	 */
1305 	if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1306 	    reg_03.raw != reg_01.raw) {
1307 		printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1308 		printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1309 	}
1310 
1311 	printk(KERN_DEBUG ".... IRQ redirection table:\n");
1312 	io_apic_print_entries(ioapic_idx, reg_01.bits.entries);
1313 }
1314 
1315 void __init print_IO_APICs(void)
1316 {
1317 	int ioapic_idx;
1318 	unsigned int irq;
1319 
1320 	printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1321 	for_each_ioapic(ioapic_idx)
1322 		printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1323 		       mpc_ioapic_id(ioapic_idx),
1324 		       ioapics[ioapic_idx].nr_registers);
1325 
1326 	/*
1327 	 * We are a bit conservative about what we expect.  We have to
1328 	 * know about every hardware change ASAP.
1329 	 */
1330 	printk(KERN_INFO "testing the IO APIC.......................\n");
1331 
1332 	for_each_ioapic(ioapic_idx)
1333 		print_IO_APIC(ioapic_idx);
1334 
1335 	printk(KERN_DEBUG "IRQ to pin mappings:\n");
1336 	for_each_active_irq(irq) {
1337 		struct irq_pin_list *entry;
1338 		struct irq_chip *chip;
1339 		struct mp_chip_data *data;
1340 
1341 		chip = irq_get_chip(irq);
1342 		if (chip != &ioapic_chip && chip != &ioapic_ir_chip)
1343 			continue;
1344 		data = irq_get_chip_data(irq);
1345 		if (!data)
1346 			continue;
1347 		if (list_empty(&data->irq_2_pin))
1348 			continue;
1349 
1350 		printk(KERN_DEBUG "IRQ%d ", irq);
1351 		for_each_irq_pin(entry, data->irq_2_pin)
1352 			pr_cont("-> %d:%d", entry->apic, entry->pin);
1353 		pr_cont("\n");
1354 	}
1355 
1356 	printk(KERN_INFO ".................................... done.\n");
1357 }
1358 
1359 /* Where if anywhere is the i8259 connect in external int mode */
1360 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1361 
1362 void __init enable_IO_APIC(void)
1363 {
1364 	int i8259_apic, i8259_pin;
1365 	int apic, pin;
1366 
1367 	if (skip_ioapic_setup)
1368 		nr_ioapics = 0;
1369 
1370 	if (!nr_legacy_irqs() || !nr_ioapics)
1371 		return;
1372 
1373 	for_each_ioapic_pin(apic, pin) {
1374 		/* See if any of the pins is in ExtINT mode */
1375 		struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin);
1376 
1377 		/* If the interrupt line is enabled and in ExtInt mode
1378 		 * I have found the pin where the i8259 is connected.
1379 		 */
1380 		if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1381 			ioapic_i8259.apic = apic;
1382 			ioapic_i8259.pin  = pin;
1383 			goto found_i8259;
1384 		}
1385 	}
1386  found_i8259:
1387 	/* Look to see what if the MP table has reported the ExtINT */
1388 	/* If we could not find the appropriate pin by looking at the ioapic
1389 	 * the i8259 probably is not connected the ioapic but give the
1390 	 * mptable a chance anyway.
1391 	 */
1392 	i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1393 	i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1394 	/* Trust the MP table if nothing is setup in the hardware */
1395 	if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1396 		printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1397 		ioapic_i8259.pin  = i8259_pin;
1398 		ioapic_i8259.apic = i8259_apic;
1399 	}
1400 	/* Complain if the MP table and the hardware disagree */
1401 	if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1402 		(i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1403 	{
1404 		printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1405 	}
1406 
1407 	/*
1408 	 * Do not trust the IO-APIC being empty at bootup
1409 	 */
1410 	clear_IO_APIC();
1411 }
1412 
1413 void native_restore_boot_irq_mode(void)
1414 {
1415 	/*
1416 	 * If the i8259 is routed through an IOAPIC
1417 	 * Put that IOAPIC in virtual wire mode
1418 	 * so legacy interrupts can be delivered.
1419 	 */
1420 	if (ioapic_i8259.pin != -1) {
1421 		struct IO_APIC_route_entry entry;
1422 
1423 		memset(&entry, 0, sizeof(entry));
1424 		entry.mask		= IOAPIC_UNMASKED;
1425 		entry.trigger		= IOAPIC_EDGE;
1426 		entry.polarity		= IOAPIC_POL_HIGH;
1427 		entry.dest_mode		= IOAPIC_DEST_MODE_PHYSICAL;
1428 		entry.delivery_mode	= dest_ExtINT;
1429 		entry.dest		= read_apic_id();
1430 
1431 		/*
1432 		 * Add it to the IO-APIC irq-routing table:
1433 		 */
1434 		ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1435 	}
1436 
1437 	if (boot_cpu_has(X86_FEATURE_APIC) || apic_from_smp_config())
1438 		disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1439 }
1440 
1441 void restore_boot_irq_mode(void)
1442 {
1443 	if (!nr_legacy_irqs())
1444 		return;
1445 
1446 	x86_apic_ops.restore();
1447 }
1448 
1449 #ifdef CONFIG_X86_32
1450 /*
1451  * function to set the IO-APIC physical IDs based on the
1452  * values stored in the MPC table.
1453  *
1454  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1455  */
1456 void __init setup_ioapic_ids_from_mpc_nocheck(void)
1457 {
1458 	union IO_APIC_reg_00 reg_00;
1459 	physid_mask_t phys_id_present_map;
1460 	int ioapic_idx;
1461 	int i;
1462 	unsigned char old_id;
1463 	unsigned long flags;
1464 
1465 	/*
1466 	 * This is broken; anything with a real cpu count has to
1467 	 * circumvent this idiocy regardless.
1468 	 */
1469 	apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1470 
1471 	/*
1472 	 * Set the IOAPIC ID to the value stored in the MPC table.
1473 	 */
1474 	for_each_ioapic(ioapic_idx) {
1475 		/* Read the register 0 value */
1476 		raw_spin_lock_irqsave(&ioapic_lock, flags);
1477 		reg_00.raw = io_apic_read(ioapic_idx, 0);
1478 		raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1479 
1480 		old_id = mpc_ioapic_id(ioapic_idx);
1481 
1482 		if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
1483 			printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1484 				ioapic_idx, mpc_ioapic_id(ioapic_idx));
1485 			printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1486 				reg_00.bits.ID);
1487 			ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
1488 		}
1489 
1490 		/*
1491 		 * Sanity check, is the ID really free? Every APIC in a
1492 		 * system must have a unique ID or we get lots of nice
1493 		 * 'stuck on smp_invalidate_needed IPI wait' messages.
1494 		 */
1495 		if (apic->check_apicid_used(&phys_id_present_map,
1496 					    mpc_ioapic_id(ioapic_idx))) {
1497 			printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1498 				ioapic_idx, mpc_ioapic_id(ioapic_idx));
1499 			for (i = 0; i < get_physical_broadcast(); i++)
1500 				if (!physid_isset(i, phys_id_present_map))
1501 					break;
1502 			if (i >= get_physical_broadcast())
1503 				panic("Max APIC ID exceeded!\n");
1504 			printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1505 				i);
1506 			physid_set(i, phys_id_present_map);
1507 			ioapics[ioapic_idx].mp_config.apicid = i;
1508 		} else {
1509 			physid_mask_t tmp;
1510 			apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
1511 						    &tmp);
1512 			apic_printk(APIC_VERBOSE, "Setting %d in the "
1513 					"phys_id_present_map\n",
1514 					mpc_ioapic_id(ioapic_idx));
1515 			physids_or(phys_id_present_map, phys_id_present_map, tmp);
1516 		}
1517 
1518 		/*
1519 		 * We need to adjust the IRQ routing table
1520 		 * if the ID changed.
1521 		 */
1522 		if (old_id != mpc_ioapic_id(ioapic_idx))
1523 			for (i = 0; i < mp_irq_entries; i++)
1524 				if (mp_irqs[i].dstapic == old_id)
1525 					mp_irqs[i].dstapic
1526 						= mpc_ioapic_id(ioapic_idx);
1527 
1528 		/*
1529 		 * Update the ID register according to the right value
1530 		 * from the MPC table if they are different.
1531 		 */
1532 		if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
1533 			continue;
1534 
1535 		apic_printk(APIC_VERBOSE, KERN_INFO
1536 			"...changing IO-APIC physical APIC ID to %d ...",
1537 			mpc_ioapic_id(ioapic_idx));
1538 
1539 		reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
1540 		raw_spin_lock_irqsave(&ioapic_lock, flags);
1541 		io_apic_write(ioapic_idx, 0, reg_00.raw);
1542 		raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1543 
1544 		/*
1545 		 * Sanity check
1546 		 */
1547 		raw_spin_lock_irqsave(&ioapic_lock, flags);
1548 		reg_00.raw = io_apic_read(ioapic_idx, 0);
1549 		raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1550 		if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
1551 			pr_cont("could not set ID!\n");
1552 		else
1553 			apic_printk(APIC_VERBOSE, " ok.\n");
1554 	}
1555 }
1556 
1557 void __init setup_ioapic_ids_from_mpc(void)
1558 {
1559 
1560 	if (acpi_ioapic)
1561 		return;
1562 	/*
1563 	 * Don't check I/O APIC IDs for xAPIC systems.  They have
1564 	 * no meaning without the serial APIC bus.
1565 	 */
1566 	if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1567 		|| APIC_XAPIC(boot_cpu_apic_version))
1568 		return;
1569 	setup_ioapic_ids_from_mpc_nocheck();
1570 }
1571 #endif
1572 
1573 int no_timer_check __initdata;
1574 
1575 static int __init notimercheck(char *s)
1576 {
1577 	no_timer_check = 1;
1578 	return 1;
1579 }
1580 __setup("no_timer_check", notimercheck);
1581 
1582 static void __init delay_with_tsc(void)
1583 {
1584 	unsigned long long start, now;
1585 	unsigned long end = jiffies + 4;
1586 
1587 	start = rdtsc();
1588 
1589 	/*
1590 	 * We don't know the TSC frequency yet, but waiting for
1591 	 * 40000000000/HZ TSC cycles is safe:
1592 	 * 4 GHz == 10 jiffies
1593 	 * 1 GHz == 40 jiffies
1594 	 */
1595 	do {
1596 		rep_nop();
1597 		now = rdtsc();
1598 	} while ((now - start) < 40000000000ULL / HZ &&
1599 		time_before_eq(jiffies, end));
1600 }
1601 
1602 static void __init delay_without_tsc(void)
1603 {
1604 	unsigned long end = jiffies + 4;
1605 	int band = 1;
1606 
1607 	/*
1608 	 * We don't know any frequency yet, but waiting for
1609 	 * 40940000000/HZ cycles is safe:
1610 	 * 4 GHz == 10 jiffies
1611 	 * 1 GHz == 40 jiffies
1612 	 * 1 << 1 + 1 << 2 +...+ 1 << 11 = 4094
1613 	 */
1614 	do {
1615 		__delay(((1U << band++) * 10000000UL) / HZ);
1616 	} while (band < 12 && time_before_eq(jiffies, end));
1617 }
1618 
1619 /*
1620  * There is a nasty bug in some older SMP boards, their mptable lies
1621  * about the timer IRQ. We do the following to work around the situation:
1622  *
1623  *	- timer IRQ defaults to IO-APIC IRQ
1624  *	- if this function detects that timer IRQs are defunct, then we fall
1625  *	  back to ISA timer IRQs
1626  */
1627 static int __init timer_irq_works(void)
1628 {
1629 	unsigned long t1 = jiffies;
1630 	unsigned long flags;
1631 
1632 	if (no_timer_check)
1633 		return 1;
1634 
1635 	local_save_flags(flags);
1636 	local_irq_enable();
1637 
1638 	if (boot_cpu_has(X86_FEATURE_TSC))
1639 		delay_with_tsc();
1640 	else
1641 		delay_without_tsc();
1642 
1643 	local_irq_restore(flags);
1644 
1645 	/*
1646 	 * Expect a few ticks at least, to be sure some possible
1647 	 * glue logic does not lock up after one or two first
1648 	 * ticks in a non-ExtINT mode.  Also the local APIC
1649 	 * might have cached one ExtINT interrupt.  Finally, at
1650 	 * least one tick may be lost due to delays.
1651 	 */
1652 
1653 	/* jiffies wrap? */
1654 	if (time_after(jiffies, t1 + 4))
1655 		return 1;
1656 	return 0;
1657 }
1658 
1659 /*
1660  * In the SMP+IOAPIC case it might happen that there are an unspecified
1661  * number of pending IRQ events unhandled. These cases are very rare,
1662  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1663  * better to do it this way as thus we do not have to be aware of
1664  * 'pending' interrupts in the IRQ path, except at this point.
1665  */
1666 /*
1667  * Edge triggered needs to resend any interrupt
1668  * that was delayed but this is now handled in the device
1669  * independent code.
1670  */
1671 
1672 /*
1673  * Starting up a edge-triggered IO-APIC interrupt is
1674  * nasty - we need to make sure that we get the edge.
1675  * If it is already asserted for some reason, we need
1676  * return 1 to indicate that is was pending.
1677  *
1678  * This is not complete - we should be able to fake
1679  * an edge even if it isn't on the 8259A...
1680  */
1681 static unsigned int startup_ioapic_irq(struct irq_data *data)
1682 {
1683 	int was_pending = 0, irq = data->irq;
1684 	unsigned long flags;
1685 
1686 	raw_spin_lock_irqsave(&ioapic_lock, flags);
1687 	if (irq < nr_legacy_irqs()) {
1688 		legacy_pic->mask(irq);
1689 		if (legacy_pic->irq_pending(irq))
1690 			was_pending = 1;
1691 	}
1692 	__unmask_ioapic(data->chip_data);
1693 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1694 
1695 	return was_pending;
1696 }
1697 
1698 atomic_t irq_mis_count;
1699 
1700 #ifdef CONFIG_GENERIC_PENDING_IRQ
1701 static bool io_apic_level_ack_pending(struct mp_chip_data *data)
1702 {
1703 	struct irq_pin_list *entry;
1704 	unsigned long flags;
1705 
1706 	raw_spin_lock_irqsave(&ioapic_lock, flags);
1707 	for_each_irq_pin(entry, data->irq_2_pin) {
1708 		unsigned int reg;
1709 		int pin;
1710 
1711 		pin = entry->pin;
1712 		reg = io_apic_read(entry->apic, 0x10 + pin*2);
1713 		/* Is the remote IRR bit set? */
1714 		if (reg & IO_APIC_REDIR_REMOTE_IRR) {
1715 			raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1716 			return true;
1717 		}
1718 	}
1719 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1720 
1721 	return false;
1722 }
1723 
1724 static inline bool ioapic_irqd_mask(struct irq_data *data)
1725 {
1726 	/* If we are moving the irq we need to mask it */
1727 	if (unlikely(irqd_is_setaffinity_pending(data))) {
1728 		mask_ioapic_irq(data);
1729 		return true;
1730 	}
1731 	return false;
1732 }
1733 
1734 static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked)
1735 {
1736 	if (unlikely(masked)) {
1737 		/* Only migrate the irq if the ack has been received.
1738 		 *
1739 		 * On rare occasions the broadcast level triggered ack gets
1740 		 * delayed going to ioapics, and if we reprogram the
1741 		 * vector while Remote IRR is still set the irq will never
1742 		 * fire again.
1743 		 *
1744 		 * To prevent this scenario we read the Remote IRR bit
1745 		 * of the ioapic.  This has two effects.
1746 		 * - On any sane system the read of the ioapic will
1747 		 *   flush writes (and acks) going to the ioapic from
1748 		 *   this cpu.
1749 		 * - We get to see if the ACK has actually been delivered.
1750 		 *
1751 		 * Based on failed experiments of reprogramming the
1752 		 * ioapic entry from outside of irq context starting
1753 		 * with masking the ioapic entry and then polling until
1754 		 * Remote IRR was clear before reprogramming the
1755 		 * ioapic I don't trust the Remote IRR bit to be
1756 		 * completey accurate.
1757 		 *
1758 		 * However there appears to be no other way to plug
1759 		 * this race, so if the Remote IRR bit is not
1760 		 * accurate and is causing problems then it is a hardware bug
1761 		 * and you can go talk to the chipset vendor about it.
1762 		 */
1763 		if (!io_apic_level_ack_pending(data->chip_data))
1764 			irq_move_masked_irq(data);
1765 		unmask_ioapic_irq(data);
1766 	}
1767 }
1768 #else
1769 static inline bool ioapic_irqd_mask(struct irq_data *data)
1770 {
1771 	return false;
1772 }
1773 static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked)
1774 {
1775 }
1776 #endif
1777 
1778 static void ioapic_ack_level(struct irq_data *irq_data)
1779 {
1780 	struct irq_cfg *cfg = irqd_cfg(irq_data);
1781 	unsigned long v;
1782 	bool masked;
1783 	int i;
1784 
1785 	irq_complete_move(cfg);
1786 	masked = ioapic_irqd_mask(irq_data);
1787 
1788 	/*
1789 	 * It appears there is an erratum which affects at least version 0x11
1790 	 * of I/O APIC (that's the 82093AA and cores integrated into various
1791 	 * chipsets).  Under certain conditions a level-triggered interrupt is
1792 	 * erroneously delivered as edge-triggered one but the respective IRR
1793 	 * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1794 	 * message but it will never arrive and further interrupts are blocked
1795 	 * from the source.  The exact reason is so far unknown, but the
1796 	 * phenomenon was observed when two consecutive interrupt requests
1797 	 * from a given source get delivered to the same CPU and the source is
1798 	 * temporarily disabled in between.
1799 	 *
1800 	 * A workaround is to simulate an EOI message manually.  We achieve it
1801 	 * by setting the trigger mode to edge and then to level when the edge
1802 	 * trigger mode gets detected in the TMR of a local APIC for a
1803 	 * level-triggered interrupt.  We mask the source for the time of the
1804 	 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1805 	 * The idea is from Manfred Spraul.  --macro
1806 	 *
1807 	 * Also in the case when cpu goes offline, fixup_irqs() will forward
1808 	 * any unhandled interrupt on the offlined cpu to the new cpu
1809 	 * destination that is handling the corresponding interrupt. This
1810 	 * interrupt forwarding is done via IPI's. Hence, in this case also
1811 	 * level-triggered io-apic interrupt will be seen as an edge
1812 	 * interrupt in the IRR. And we can't rely on the cpu's EOI
1813 	 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
1814 	 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
1815 	 * supporting EOI register, we do an explicit EOI to clear the
1816 	 * remote IRR and on IO-APIC's which don't have an EOI register,
1817 	 * we use the above logic (mask+edge followed by unmask+level) from
1818 	 * Manfred Spraul to clear the remote IRR.
1819 	 */
1820 	i = cfg->vector;
1821 	v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1822 
1823 	/*
1824 	 * We must acknowledge the irq before we move it or the acknowledge will
1825 	 * not propagate properly.
1826 	 */
1827 	ack_APIC_irq();
1828 
1829 	/*
1830 	 * Tail end of clearing remote IRR bit (either by delivering the EOI
1831 	 * message via io-apic EOI register write or simulating it using
1832 	 * mask+edge followed by unnask+level logic) manually when the
1833 	 * level triggered interrupt is seen as the edge triggered interrupt
1834 	 * at the cpu.
1835 	 */
1836 	if (!(v & (1 << (i & 0x1f)))) {
1837 		atomic_inc(&irq_mis_count);
1838 		eoi_ioapic_pin(cfg->vector, irq_data->chip_data);
1839 	}
1840 
1841 	ioapic_irqd_unmask(irq_data, masked);
1842 }
1843 
1844 static void ioapic_ir_ack_level(struct irq_data *irq_data)
1845 {
1846 	struct mp_chip_data *data = irq_data->chip_data;
1847 
1848 	/*
1849 	 * Intr-remapping uses pin number as the virtual vector
1850 	 * in the RTE. Actual vector is programmed in
1851 	 * intr-remapping table entry. Hence for the io-apic
1852 	 * EOI we use the pin number.
1853 	 */
1854 	apic_ack_irq(irq_data);
1855 	eoi_ioapic_pin(data->entry.vector, data);
1856 }
1857 
1858 static void ioapic_configure_entry(struct irq_data *irqd)
1859 {
1860 	struct mp_chip_data *mpd = irqd->chip_data;
1861 	struct irq_cfg *cfg = irqd_cfg(irqd);
1862 	struct irq_pin_list *entry;
1863 
1864 	/*
1865 	 * Only update when the parent is the vector domain, don't touch it
1866 	 * if the parent is the remapping domain. Check the installed
1867 	 * ioapic chip to verify that.
1868 	 */
1869 	if (irqd->chip == &ioapic_chip) {
1870 		mpd->entry.dest = cfg->dest_apicid;
1871 		mpd->entry.vector = cfg->vector;
1872 	}
1873 	for_each_irq_pin(entry, mpd->irq_2_pin)
1874 		__ioapic_write_entry(entry->apic, entry->pin, mpd->entry);
1875 }
1876 
1877 static int ioapic_set_affinity(struct irq_data *irq_data,
1878 			       const struct cpumask *mask, bool force)
1879 {
1880 	struct irq_data *parent = irq_data->parent_data;
1881 	unsigned long flags;
1882 	int ret;
1883 
1884 	ret = parent->chip->irq_set_affinity(parent, mask, force);
1885 	raw_spin_lock_irqsave(&ioapic_lock, flags);
1886 	if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE)
1887 		ioapic_configure_entry(irq_data);
1888 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1889 
1890 	return ret;
1891 }
1892 
1893 static struct irq_chip ioapic_chip __read_mostly = {
1894 	.name			= "IO-APIC",
1895 	.irq_startup		= startup_ioapic_irq,
1896 	.irq_mask		= mask_ioapic_irq,
1897 	.irq_unmask		= unmask_ioapic_irq,
1898 	.irq_ack		= irq_chip_ack_parent,
1899 	.irq_eoi		= ioapic_ack_level,
1900 	.irq_set_affinity	= ioapic_set_affinity,
1901 	.irq_retrigger		= irq_chip_retrigger_hierarchy,
1902 	.flags			= IRQCHIP_SKIP_SET_WAKE,
1903 };
1904 
1905 static struct irq_chip ioapic_ir_chip __read_mostly = {
1906 	.name			= "IR-IO-APIC",
1907 	.irq_startup		= startup_ioapic_irq,
1908 	.irq_mask		= mask_ioapic_irq,
1909 	.irq_unmask		= unmask_ioapic_irq,
1910 	.irq_ack		= irq_chip_ack_parent,
1911 	.irq_eoi		= ioapic_ir_ack_level,
1912 	.irq_set_affinity	= ioapic_set_affinity,
1913 	.irq_retrigger		= irq_chip_retrigger_hierarchy,
1914 	.flags			= IRQCHIP_SKIP_SET_WAKE,
1915 };
1916 
1917 static inline void init_IO_APIC_traps(void)
1918 {
1919 	struct irq_cfg *cfg;
1920 	unsigned int irq;
1921 
1922 	for_each_active_irq(irq) {
1923 		cfg = irq_cfg(irq);
1924 		if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
1925 			/*
1926 			 * Hmm.. We don't have an entry for this,
1927 			 * so default to an old-fashioned 8259
1928 			 * interrupt if we can..
1929 			 */
1930 			if (irq < nr_legacy_irqs())
1931 				legacy_pic->make_irq(irq);
1932 			else
1933 				/* Strange. Oh, well.. */
1934 				irq_set_chip(irq, &no_irq_chip);
1935 		}
1936 	}
1937 }
1938 
1939 /*
1940  * The local APIC irq-chip implementation:
1941  */
1942 
1943 static void mask_lapic_irq(struct irq_data *data)
1944 {
1945 	unsigned long v;
1946 
1947 	v = apic_read(APIC_LVT0);
1948 	apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1949 }
1950 
1951 static void unmask_lapic_irq(struct irq_data *data)
1952 {
1953 	unsigned long v;
1954 
1955 	v = apic_read(APIC_LVT0);
1956 	apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1957 }
1958 
1959 static void ack_lapic_irq(struct irq_data *data)
1960 {
1961 	ack_APIC_irq();
1962 }
1963 
1964 static struct irq_chip lapic_chip __read_mostly = {
1965 	.name		= "local-APIC",
1966 	.irq_mask	= mask_lapic_irq,
1967 	.irq_unmask	= unmask_lapic_irq,
1968 	.irq_ack	= ack_lapic_irq,
1969 };
1970 
1971 static void lapic_register_intr(int irq)
1972 {
1973 	irq_clear_status_flags(irq, IRQ_LEVEL);
1974 	irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
1975 				      "edge");
1976 }
1977 
1978 /*
1979  * This looks a bit hackish but it's about the only one way of sending
1980  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1981  * not support the ExtINT mode, unfortunately.  We need to send these
1982  * cycles as some i82489DX-based boards have glue logic that keeps the
1983  * 8259A interrupt line asserted until INTA.  --macro
1984  */
1985 static inline void __init unlock_ExtINT_logic(void)
1986 {
1987 	int apic, pin, i;
1988 	struct IO_APIC_route_entry entry0, entry1;
1989 	unsigned char save_control, save_freq_select;
1990 
1991 	pin  = find_isa_irq_pin(8, mp_INT);
1992 	if (pin == -1) {
1993 		WARN_ON_ONCE(1);
1994 		return;
1995 	}
1996 	apic = find_isa_irq_apic(8, mp_INT);
1997 	if (apic == -1) {
1998 		WARN_ON_ONCE(1);
1999 		return;
2000 	}
2001 
2002 	entry0 = ioapic_read_entry(apic, pin);
2003 	clear_IO_APIC_pin(apic, pin);
2004 
2005 	memset(&entry1, 0, sizeof(entry1));
2006 
2007 	entry1.dest_mode = IOAPIC_DEST_MODE_PHYSICAL;
2008 	entry1.mask = IOAPIC_UNMASKED;
2009 	entry1.dest = hard_smp_processor_id();
2010 	entry1.delivery_mode = dest_ExtINT;
2011 	entry1.polarity = entry0.polarity;
2012 	entry1.trigger = IOAPIC_EDGE;
2013 	entry1.vector = 0;
2014 
2015 	ioapic_write_entry(apic, pin, entry1);
2016 
2017 	save_control = CMOS_READ(RTC_CONTROL);
2018 	save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2019 	CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2020 		   RTC_FREQ_SELECT);
2021 	CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2022 
2023 	i = 100;
2024 	while (i-- > 0) {
2025 		mdelay(10);
2026 		if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2027 			i -= 10;
2028 	}
2029 
2030 	CMOS_WRITE(save_control, RTC_CONTROL);
2031 	CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2032 	clear_IO_APIC_pin(apic, pin);
2033 
2034 	ioapic_write_entry(apic, pin, entry0);
2035 }
2036 
2037 static int disable_timer_pin_1 __initdata;
2038 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2039 static int __init disable_timer_pin_setup(char *arg)
2040 {
2041 	disable_timer_pin_1 = 1;
2042 	return 0;
2043 }
2044 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2045 
2046 static int mp_alloc_timer_irq(int ioapic, int pin)
2047 {
2048 	int irq = -1;
2049 	struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
2050 
2051 	if (domain) {
2052 		struct irq_alloc_info info;
2053 
2054 		ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0);
2055 		info.ioapic_id = mpc_ioapic_id(ioapic);
2056 		info.ioapic_pin = pin;
2057 		mutex_lock(&ioapic_mutex);
2058 		irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info);
2059 		mutex_unlock(&ioapic_mutex);
2060 	}
2061 
2062 	return irq;
2063 }
2064 
2065 /*
2066  * This code may look a bit paranoid, but it's supposed to cooperate with
2067  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2068  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2069  * fanatically on his truly buggy board.
2070  *
2071  * FIXME: really need to revamp this for all platforms.
2072  */
2073 static inline void __init check_timer(void)
2074 {
2075 	struct irq_data *irq_data = irq_get_irq_data(0);
2076 	struct mp_chip_data *data = irq_data->chip_data;
2077 	struct irq_cfg *cfg = irqd_cfg(irq_data);
2078 	int node = cpu_to_node(0);
2079 	int apic1, pin1, apic2, pin2;
2080 	unsigned long flags;
2081 	int no_pin1 = 0;
2082 
2083 	local_irq_save(flags);
2084 
2085 	/*
2086 	 * get/set the timer IRQ vector:
2087 	 */
2088 	legacy_pic->mask(0);
2089 
2090 	/*
2091 	 * As IRQ0 is to be enabled in the 8259A, the virtual
2092 	 * wire has to be disabled in the local APIC.  Also
2093 	 * timer interrupts need to be acknowledged manually in
2094 	 * the 8259A for the i82489DX when using the NMI
2095 	 * watchdog as that APIC treats NMIs as level-triggered.
2096 	 * The AEOI mode will finish them in the 8259A
2097 	 * automatically.
2098 	 */
2099 	apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2100 	legacy_pic->init(1);
2101 
2102 	pin1  = find_isa_irq_pin(0, mp_INT);
2103 	apic1 = find_isa_irq_apic(0, mp_INT);
2104 	pin2  = ioapic_i8259.pin;
2105 	apic2 = ioapic_i8259.apic;
2106 
2107 	apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2108 		    "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2109 		    cfg->vector, apic1, pin1, apic2, pin2);
2110 
2111 	/*
2112 	 * Some BIOS writers are clueless and report the ExtINTA
2113 	 * I/O APIC input from the cascaded 8259A as the timer
2114 	 * interrupt input.  So just in case, if only one pin
2115 	 * was found above, try it both directly and through the
2116 	 * 8259A.
2117 	 */
2118 	if (pin1 == -1) {
2119 		panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2120 		pin1 = pin2;
2121 		apic1 = apic2;
2122 		no_pin1 = 1;
2123 	} else if (pin2 == -1) {
2124 		pin2 = pin1;
2125 		apic2 = apic1;
2126 	}
2127 
2128 	if (pin1 != -1) {
2129 		/* Ok, does IRQ0 through the IOAPIC work? */
2130 		if (no_pin1) {
2131 			mp_alloc_timer_irq(apic1, pin1);
2132 		} else {
2133 			/*
2134 			 * for edge trigger, it's already unmasked,
2135 			 * so only need to unmask if it is level-trigger
2136 			 * do we really have level trigger timer?
2137 			 */
2138 			int idx;
2139 			idx = find_irq_entry(apic1, pin1, mp_INT);
2140 			if (idx != -1 && irq_trigger(idx))
2141 				unmask_ioapic_irq(irq_get_irq_data(0));
2142 		}
2143 		irq_domain_deactivate_irq(irq_data);
2144 		irq_domain_activate_irq(irq_data, false);
2145 		if (timer_irq_works()) {
2146 			if (disable_timer_pin_1 > 0)
2147 				clear_IO_APIC_pin(0, pin1);
2148 			goto out;
2149 		}
2150 		panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2151 		local_irq_disable();
2152 		clear_IO_APIC_pin(apic1, pin1);
2153 		if (!no_pin1)
2154 			apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2155 				    "8254 timer not connected to IO-APIC\n");
2156 
2157 		apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2158 			    "(IRQ0) through the 8259A ...\n");
2159 		apic_printk(APIC_QUIET, KERN_INFO
2160 			    "..... (found apic %d pin %d) ...\n", apic2, pin2);
2161 		/*
2162 		 * legacy devices should be connected to IO APIC #0
2163 		 */
2164 		replace_pin_at_irq_node(data, node, apic1, pin1, apic2, pin2);
2165 		irq_domain_deactivate_irq(irq_data);
2166 		irq_domain_activate_irq(irq_data, false);
2167 		legacy_pic->unmask(0);
2168 		if (timer_irq_works()) {
2169 			apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2170 			goto out;
2171 		}
2172 		/*
2173 		 * Cleanup, just in case ...
2174 		 */
2175 		local_irq_disable();
2176 		legacy_pic->mask(0);
2177 		clear_IO_APIC_pin(apic2, pin2);
2178 		apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2179 	}
2180 
2181 	apic_printk(APIC_QUIET, KERN_INFO
2182 		    "...trying to set up timer as Virtual Wire IRQ...\n");
2183 
2184 	lapic_register_intr(0);
2185 	apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector);	/* Fixed mode */
2186 	legacy_pic->unmask(0);
2187 
2188 	if (timer_irq_works()) {
2189 		apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2190 		goto out;
2191 	}
2192 	local_irq_disable();
2193 	legacy_pic->mask(0);
2194 	apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2195 	apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2196 
2197 	apic_printk(APIC_QUIET, KERN_INFO
2198 		    "...trying to set up timer as ExtINT IRQ...\n");
2199 
2200 	legacy_pic->init(0);
2201 	legacy_pic->make_irq(0);
2202 	apic_write(APIC_LVT0, APIC_DM_EXTINT);
2203 
2204 	unlock_ExtINT_logic();
2205 
2206 	if (timer_irq_works()) {
2207 		apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2208 		goto out;
2209 	}
2210 	local_irq_disable();
2211 	apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2212 	if (apic_is_x2apic_enabled())
2213 		apic_printk(APIC_QUIET, KERN_INFO
2214 			    "Perhaps problem with the pre-enabled x2apic mode\n"
2215 			    "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2216 	panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2217 		"report.  Then try booting with the 'noapic' option.\n");
2218 out:
2219 	local_irq_restore(flags);
2220 }
2221 
2222 /*
2223  * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2224  * to devices.  However there may be an I/O APIC pin available for
2225  * this interrupt regardless.  The pin may be left unconnected, but
2226  * typically it will be reused as an ExtINT cascade interrupt for
2227  * the master 8259A.  In the MPS case such a pin will normally be
2228  * reported as an ExtINT interrupt in the MP table.  With ACPI
2229  * there is no provision for ExtINT interrupts, and in the absence
2230  * of an override it would be treated as an ordinary ISA I/O APIC
2231  * interrupt, that is edge-triggered and unmasked by default.  We
2232  * used to do this, but it caused problems on some systems because
2233  * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2234  * the same ExtINT cascade interrupt to drive the local APIC of the
2235  * bootstrap processor.  Therefore we refrain from routing IRQ2 to
2236  * the I/O APIC in all cases now.  No actual device should request
2237  * it anyway.  --macro
2238  */
2239 #define PIC_IRQS	(1UL << PIC_CASCADE_IR)
2240 
2241 static int mp_irqdomain_create(int ioapic)
2242 {
2243 	struct irq_alloc_info info;
2244 	struct irq_domain *parent;
2245 	int hwirqs = mp_ioapic_pin_count(ioapic);
2246 	struct ioapic *ip = &ioapics[ioapic];
2247 	struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg;
2248 	struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2249 	struct fwnode_handle *fn;
2250 	char *name = "IO-APIC";
2251 
2252 	if (cfg->type == IOAPIC_DOMAIN_INVALID)
2253 		return 0;
2254 
2255 	init_irq_alloc_info(&info, NULL);
2256 	info.type = X86_IRQ_ALLOC_TYPE_IOAPIC;
2257 	info.ioapic_id = mpc_ioapic_id(ioapic);
2258 	parent = irq_remapping_get_ir_irq_domain(&info);
2259 	if (!parent)
2260 		parent = x86_vector_domain;
2261 	else
2262 		name = "IO-APIC-IR";
2263 
2264 	/* Handle device tree enumerated APICs proper */
2265 	if (cfg->dev) {
2266 		fn = of_node_to_fwnode(cfg->dev);
2267 	} else {
2268 		fn = irq_domain_alloc_named_id_fwnode(name, ioapic);
2269 		if (!fn)
2270 			return -ENOMEM;
2271 	}
2272 
2273 	ip->irqdomain = irq_domain_create_linear(fn, hwirqs, cfg->ops,
2274 						 (void *)(long)ioapic);
2275 
2276 	/* Release fw handle if it was allocated above */
2277 	if (!cfg->dev)
2278 		irq_domain_free_fwnode(fn);
2279 
2280 	if (!ip->irqdomain)
2281 		return -ENOMEM;
2282 
2283 	ip->irqdomain->parent = parent;
2284 
2285 	if (cfg->type == IOAPIC_DOMAIN_LEGACY ||
2286 	    cfg->type == IOAPIC_DOMAIN_STRICT)
2287 		ioapic_dynirq_base = max(ioapic_dynirq_base,
2288 					 gsi_cfg->gsi_end + 1);
2289 
2290 	return 0;
2291 }
2292 
2293 static void ioapic_destroy_irqdomain(int idx)
2294 {
2295 	if (ioapics[idx].irqdomain) {
2296 		irq_domain_remove(ioapics[idx].irqdomain);
2297 		ioapics[idx].irqdomain = NULL;
2298 	}
2299 }
2300 
2301 void __init setup_IO_APIC(void)
2302 {
2303 	int ioapic;
2304 
2305 	if (skip_ioapic_setup || !nr_ioapics)
2306 		return;
2307 
2308 	io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL;
2309 
2310 	apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2311 	for_each_ioapic(ioapic)
2312 		BUG_ON(mp_irqdomain_create(ioapic));
2313 
2314 	/*
2315          * Set up IO-APIC IRQ routing.
2316          */
2317 	x86_init.mpparse.setup_ioapic_ids();
2318 
2319 	sync_Arb_IDs();
2320 	setup_IO_APIC_irqs();
2321 	init_IO_APIC_traps();
2322 	if (nr_legacy_irqs())
2323 		check_timer();
2324 
2325 	ioapic_initialized = 1;
2326 }
2327 
2328 static void resume_ioapic_id(int ioapic_idx)
2329 {
2330 	unsigned long flags;
2331 	union IO_APIC_reg_00 reg_00;
2332 
2333 	raw_spin_lock_irqsave(&ioapic_lock, flags);
2334 	reg_00.raw = io_apic_read(ioapic_idx, 0);
2335 	if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2336 		reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2337 		io_apic_write(ioapic_idx, 0, reg_00.raw);
2338 	}
2339 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2340 }
2341 
2342 static void ioapic_resume(void)
2343 {
2344 	int ioapic_idx;
2345 
2346 	for_each_ioapic_reverse(ioapic_idx)
2347 		resume_ioapic_id(ioapic_idx);
2348 
2349 	restore_ioapic_entries();
2350 }
2351 
2352 static struct syscore_ops ioapic_syscore_ops = {
2353 	.suspend = save_ioapic_entries,
2354 	.resume = ioapic_resume,
2355 };
2356 
2357 static int __init ioapic_init_ops(void)
2358 {
2359 	register_syscore_ops(&ioapic_syscore_ops);
2360 
2361 	return 0;
2362 }
2363 
2364 device_initcall(ioapic_init_ops);
2365 
2366 static int io_apic_get_redir_entries(int ioapic)
2367 {
2368 	union IO_APIC_reg_01	reg_01;
2369 	unsigned long flags;
2370 
2371 	raw_spin_lock_irqsave(&ioapic_lock, flags);
2372 	reg_01.raw = io_apic_read(ioapic, 1);
2373 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2374 
2375 	/* The register returns the maximum index redir index
2376 	 * supported, which is one less than the total number of redir
2377 	 * entries.
2378 	 */
2379 	return reg_01.bits.entries + 1;
2380 }
2381 
2382 unsigned int arch_dynirq_lower_bound(unsigned int from)
2383 {
2384 	/*
2385 	 * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
2386 	 * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
2387 	 */
2388 	return ioapic_initialized ? ioapic_dynirq_base : gsi_top;
2389 }
2390 
2391 #ifdef CONFIG_X86_32
2392 static int io_apic_get_unique_id(int ioapic, int apic_id)
2393 {
2394 	union IO_APIC_reg_00 reg_00;
2395 	static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2396 	physid_mask_t tmp;
2397 	unsigned long flags;
2398 	int i = 0;
2399 
2400 	/*
2401 	 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2402 	 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2403 	 * supports up to 16 on one shared APIC bus.
2404 	 *
2405 	 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2406 	 *      advantage of new APIC bus architecture.
2407 	 */
2408 
2409 	if (physids_empty(apic_id_map))
2410 		apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
2411 
2412 	raw_spin_lock_irqsave(&ioapic_lock, flags);
2413 	reg_00.raw = io_apic_read(ioapic, 0);
2414 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2415 
2416 	if (apic_id >= get_physical_broadcast()) {
2417 		printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2418 			"%d\n", ioapic, apic_id, reg_00.bits.ID);
2419 		apic_id = reg_00.bits.ID;
2420 	}
2421 
2422 	/*
2423 	 * Every APIC in a system must have a unique ID or we get lots of nice
2424 	 * 'stuck on smp_invalidate_needed IPI wait' messages.
2425 	 */
2426 	if (apic->check_apicid_used(&apic_id_map, apic_id)) {
2427 
2428 		for (i = 0; i < get_physical_broadcast(); i++) {
2429 			if (!apic->check_apicid_used(&apic_id_map, i))
2430 				break;
2431 		}
2432 
2433 		if (i == get_physical_broadcast())
2434 			panic("Max apic_id exceeded!\n");
2435 
2436 		printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2437 			"trying %d\n", ioapic, apic_id, i);
2438 
2439 		apic_id = i;
2440 	}
2441 
2442 	apic->apicid_to_cpu_present(apic_id, &tmp);
2443 	physids_or(apic_id_map, apic_id_map, tmp);
2444 
2445 	if (reg_00.bits.ID != apic_id) {
2446 		reg_00.bits.ID = apic_id;
2447 
2448 		raw_spin_lock_irqsave(&ioapic_lock, flags);
2449 		io_apic_write(ioapic, 0, reg_00.raw);
2450 		reg_00.raw = io_apic_read(ioapic, 0);
2451 		raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2452 
2453 		/* Sanity check */
2454 		if (reg_00.bits.ID != apic_id) {
2455 			pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
2456 			       ioapic);
2457 			return -1;
2458 		}
2459 	}
2460 
2461 	apic_printk(APIC_VERBOSE, KERN_INFO
2462 			"IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2463 
2464 	return apic_id;
2465 }
2466 
2467 static u8 io_apic_unique_id(int idx, u8 id)
2468 {
2469 	if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
2470 	    !APIC_XAPIC(boot_cpu_apic_version))
2471 		return io_apic_get_unique_id(idx, id);
2472 	else
2473 		return id;
2474 }
2475 #else
2476 static u8 io_apic_unique_id(int idx, u8 id)
2477 {
2478 	union IO_APIC_reg_00 reg_00;
2479 	DECLARE_BITMAP(used, 256);
2480 	unsigned long flags;
2481 	u8 new_id;
2482 	int i;
2483 
2484 	bitmap_zero(used, 256);
2485 	for_each_ioapic(i)
2486 		__set_bit(mpc_ioapic_id(i), used);
2487 
2488 	/* Hand out the requested id if available */
2489 	if (!test_bit(id, used))
2490 		return id;
2491 
2492 	/*
2493 	 * Read the current id from the ioapic and keep it if
2494 	 * available.
2495 	 */
2496 	raw_spin_lock_irqsave(&ioapic_lock, flags);
2497 	reg_00.raw = io_apic_read(idx, 0);
2498 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2499 	new_id = reg_00.bits.ID;
2500 	if (!test_bit(new_id, used)) {
2501 		apic_printk(APIC_VERBOSE, KERN_INFO
2502 			"IOAPIC[%d]: Using reg apic_id %d instead of %d\n",
2503 			 idx, new_id, id);
2504 		return new_id;
2505 	}
2506 
2507 	/*
2508 	 * Get the next free id and write it to the ioapic.
2509 	 */
2510 	new_id = find_first_zero_bit(used, 256);
2511 	reg_00.bits.ID = new_id;
2512 	raw_spin_lock_irqsave(&ioapic_lock, flags);
2513 	io_apic_write(idx, 0, reg_00.raw);
2514 	reg_00.raw = io_apic_read(idx, 0);
2515 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2516 	/* Sanity check */
2517 	BUG_ON(reg_00.bits.ID != new_id);
2518 
2519 	return new_id;
2520 }
2521 #endif
2522 
2523 static int io_apic_get_version(int ioapic)
2524 {
2525 	union IO_APIC_reg_01	reg_01;
2526 	unsigned long flags;
2527 
2528 	raw_spin_lock_irqsave(&ioapic_lock, flags);
2529 	reg_01.raw = io_apic_read(ioapic, 1);
2530 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2531 
2532 	return reg_01.bits.version;
2533 }
2534 
2535 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
2536 {
2537 	int ioapic, pin, idx;
2538 
2539 	if (skip_ioapic_setup)
2540 		return -1;
2541 
2542 	ioapic = mp_find_ioapic(gsi);
2543 	if (ioapic < 0)
2544 		return -1;
2545 
2546 	pin = mp_find_ioapic_pin(ioapic, gsi);
2547 	if (pin < 0)
2548 		return -1;
2549 
2550 	idx = find_irq_entry(ioapic, pin, mp_INT);
2551 	if (idx < 0)
2552 		return -1;
2553 
2554 	*trigger = irq_trigger(idx);
2555 	*polarity = irq_polarity(idx);
2556 	return 0;
2557 }
2558 
2559 /*
2560  * This function updates target affinity of IOAPIC interrupts to include
2561  * the CPUs which came online during SMP bringup.
2562  */
2563 #define IOAPIC_RESOURCE_NAME_SIZE 11
2564 
2565 static struct resource *ioapic_resources;
2566 
2567 static struct resource * __init ioapic_setup_resources(void)
2568 {
2569 	unsigned long n;
2570 	struct resource *res;
2571 	char *mem;
2572 	int i;
2573 
2574 	if (nr_ioapics == 0)
2575 		return NULL;
2576 
2577 	n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2578 	n *= nr_ioapics;
2579 
2580 	mem = alloc_bootmem(n);
2581 	res = (void *)mem;
2582 
2583 	mem += sizeof(struct resource) * nr_ioapics;
2584 
2585 	for_each_ioapic(i) {
2586 		res[i].name = mem;
2587 		res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2588 		snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
2589 		mem += IOAPIC_RESOURCE_NAME_SIZE;
2590 		ioapics[i].iomem_res = &res[i];
2591 	}
2592 
2593 	ioapic_resources = res;
2594 
2595 	return res;
2596 }
2597 
2598 void __init io_apic_init_mappings(void)
2599 {
2600 	unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2601 	struct resource *ioapic_res;
2602 	int i;
2603 
2604 	ioapic_res = ioapic_setup_resources();
2605 	for_each_ioapic(i) {
2606 		if (smp_found_config) {
2607 			ioapic_phys = mpc_ioapic_addr(i);
2608 #ifdef CONFIG_X86_32
2609 			if (!ioapic_phys) {
2610 				printk(KERN_ERR
2611 				       "WARNING: bogus zero IO-APIC "
2612 				       "address found in MPTABLE, "
2613 				       "disabling IO/APIC support!\n");
2614 				smp_found_config = 0;
2615 				skip_ioapic_setup = 1;
2616 				goto fake_ioapic_page;
2617 			}
2618 #endif
2619 		} else {
2620 #ifdef CONFIG_X86_32
2621 fake_ioapic_page:
2622 #endif
2623 			ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
2624 			ioapic_phys = __pa(ioapic_phys);
2625 		}
2626 		set_fixmap_nocache(idx, ioapic_phys);
2627 		apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
2628 			__fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
2629 			ioapic_phys);
2630 		idx++;
2631 
2632 		ioapic_res->start = ioapic_phys;
2633 		ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
2634 		ioapic_res++;
2635 	}
2636 }
2637 
2638 void __init ioapic_insert_resources(void)
2639 {
2640 	int i;
2641 	struct resource *r = ioapic_resources;
2642 
2643 	if (!r) {
2644 		if (nr_ioapics > 0)
2645 			printk(KERN_ERR
2646 				"IO APIC resources couldn't be allocated.\n");
2647 		return;
2648 	}
2649 
2650 	for_each_ioapic(i) {
2651 		insert_resource(&iomem_resource, r);
2652 		r++;
2653 	}
2654 }
2655 
2656 int mp_find_ioapic(u32 gsi)
2657 {
2658 	int i;
2659 
2660 	if (nr_ioapics == 0)
2661 		return -1;
2662 
2663 	/* Find the IOAPIC that manages this GSI. */
2664 	for_each_ioapic(i) {
2665 		struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
2666 		if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end)
2667 			return i;
2668 	}
2669 
2670 	printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
2671 	return -1;
2672 }
2673 
2674 int mp_find_ioapic_pin(int ioapic, u32 gsi)
2675 {
2676 	struct mp_ioapic_gsi *gsi_cfg;
2677 
2678 	if (WARN_ON(ioapic < 0))
2679 		return -1;
2680 
2681 	gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2682 	if (WARN_ON(gsi > gsi_cfg->gsi_end))
2683 		return -1;
2684 
2685 	return gsi - gsi_cfg->gsi_base;
2686 }
2687 
2688 static int bad_ioapic_register(int idx)
2689 {
2690 	union IO_APIC_reg_00 reg_00;
2691 	union IO_APIC_reg_01 reg_01;
2692 	union IO_APIC_reg_02 reg_02;
2693 
2694 	reg_00.raw = io_apic_read(idx, 0);
2695 	reg_01.raw = io_apic_read(idx, 1);
2696 	reg_02.raw = io_apic_read(idx, 2);
2697 
2698 	if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
2699 		pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
2700 			mpc_ioapic_addr(idx));
2701 		return 1;
2702 	}
2703 
2704 	return 0;
2705 }
2706 
2707 static int find_free_ioapic_entry(void)
2708 {
2709 	int idx;
2710 
2711 	for (idx = 0; idx < MAX_IO_APICS; idx++)
2712 		if (ioapics[idx].nr_registers == 0)
2713 			return idx;
2714 
2715 	return MAX_IO_APICS;
2716 }
2717 
2718 /**
2719  * mp_register_ioapic - Register an IOAPIC device
2720  * @id:		hardware IOAPIC ID
2721  * @address:	physical address of IOAPIC register area
2722  * @gsi_base:	base of GSI associated with the IOAPIC
2723  * @cfg:	configuration information for the IOAPIC
2724  */
2725 int mp_register_ioapic(int id, u32 address, u32 gsi_base,
2726 		       struct ioapic_domain_cfg *cfg)
2727 {
2728 	bool hotplug = !!ioapic_initialized;
2729 	struct mp_ioapic_gsi *gsi_cfg;
2730 	int idx, ioapic, entries;
2731 	u32 gsi_end;
2732 
2733 	if (!address) {
2734 		pr_warn("Bogus (zero) I/O APIC address found, skipping!\n");
2735 		return -EINVAL;
2736 	}
2737 	for_each_ioapic(ioapic)
2738 		if (ioapics[ioapic].mp_config.apicaddr == address) {
2739 			pr_warn("address 0x%x conflicts with IOAPIC%d\n",
2740 				address, ioapic);
2741 			return -EEXIST;
2742 		}
2743 
2744 	idx = find_free_ioapic_entry();
2745 	if (idx >= MAX_IO_APICS) {
2746 		pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
2747 			MAX_IO_APICS, idx);
2748 		return -ENOSPC;
2749 	}
2750 
2751 	ioapics[idx].mp_config.type = MP_IOAPIC;
2752 	ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
2753 	ioapics[idx].mp_config.apicaddr = address;
2754 
2755 	set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
2756 	if (bad_ioapic_register(idx)) {
2757 		clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2758 		return -ENODEV;
2759 	}
2760 
2761 	ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id);
2762 	ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
2763 
2764 	/*
2765 	 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
2766 	 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
2767 	 */
2768 	entries = io_apic_get_redir_entries(idx);
2769 	gsi_end = gsi_base + entries - 1;
2770 	for_each_ioapic(ioapic) {
2771 		gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2772 		if ((gsi_base >= gsi_cfg->gsi_base &&
2773 		     gsi_base <= gsi_cfg->gsi_end) ||
2774 		    (gsi_end >= gsi_cfg->gsi_base &&
2775 		     gsi_end <= gsi_cfg->gsi_end)) {
2776 			pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n",
2777 				gsi_base, gsi_end,
2778 				gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2779 			clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2780 			return -ENOSPC;
2781 		}
2782 	}
2783 	gsi_cfg = mp_ioapic_gsi_routing(idx);
2784 	gsi_cfg->gsi_base = gsi_base;
2785 	gsi_cfg->gsi_end = gsi_end;
2786 
2787 	ioapics[idx].irqdomain = NULL;
2788 	ioapics[idx].irqdomain_cfg = *cfg;
2789 
2790 	/*
2791 	 * If mp_register_ioapic() is called during early boot stage when
2792 	 * walking ACPI/SFI/DT tables, it's too early to create irqdomain,
2793 	 * we are still using bootmem allocator. So delay it to setup_IO_APIC().
2794 	 */
2795 	if (hotplug) {
2796 		if (mp_irqdomain_create(idx)) {
2797 			clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2798 			return -ENOMEM;
2799 		}
2800 		alloc_ioapic_saved_registers(idx);
2801 	}
2802 
2803 	if (gsi_cfg->gsi_end >= gsi_top)
2804 		gsi_top = gsi_cfg->gsi_end + 1;
2805 	if (nr_ioapics <= idx)
2806 		nr_ioapics = idx + 1;
2807 
2808 	/* Set nr_registers to mark entry present */
2809 	ioapics[idx].nr_registers = entries;
2810 
2811 	pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
2812 		idx, mpc_ioapic_id(idx),
2813 		mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
2814 		gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2815 
2816 	return 0;
2817 }
2818 
2819 int mp_unregister_ioapic(u32 gsi_base)
2820 {
2821 	int ioapic, pin;
2822 	int found = 0;
2823 
2824 	for_each_ioapic(ioapic)
2825 		if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) {
2826 			found = 1;
2827 			break;
2828 		}
2829 	if (!found) {
2830 		pr_warn("can't find IOAPIC for GSI %d\n", gsi_base);
2831 		return -ENODEV;
2832 	}
2833 
2834 	for_each_pin(ioapic, pin) {
2835 		u32 gsi = mp_pin_to_gsi(ioapic, pin);
2836 		int irq = mp_map_gsi_to_irq(gsi, 0, NULL);
2837 		struct mp_chip_data *data;
2838 
2839 		if (irq >= 0) {
2840 			data = irq_get_chip_data(irq);
2841 			if (data && data->count) {
2842 				pr_warn("pin%d on IOAPIC%d is still in use.\n",
2843 					pin, ioapic);
2844 				return -EBUSY;
2845 			}
2846 		}
2847 	}
2848 
2849 	/* Mark entry not present */
2850 	ioapics[ioapic].nr_registers  = 0;
2851 	ioapic_destroy_irqdomain(ioapic);
2852 	free_ioapic_saved_registers(ioapic);
2853 	if (ioapics[ioapic].iomem_res)
2854 		release_resource(ioapics[ioapic].iomem_res);
2855 	clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic);
2856 	memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic]));
2857 
2858 	return 0;
2859 }
2860 
2861 int mp_ioapic_registered(u32 gsi_base)
2862 {
2863 	int ioapic;
2864 
2865 	for_each_ioapic(ioapic)
2866 		if (ioapics[ioapic].gsi_config.gsi_base == gsi_base)
2867 			return 1;
2868 
2869 	return 0;
2870 }
2871 
2872 static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data,
2873 				  struct irq_alloc_info *info)
2874 {
2875 	if (info && info->ioapic_valid) {
2876 		data->trigger = info->ioapic_trigger;
2877 		data->polarity = info->ioapic_polarity;
2878 	} else if (acpi_get_override_irq(gsi, &data->trigger,
2879 					 &data->polarity) < 0) {
2880 		/* PCI interrupts are always active low level triggered. */
2881 		data->trigger = IOAPIC_LEVEL;
2882 		data->polarity = IOAPIC_POL_LOW;
2883 	}
2884 }
2885 
2886 static void mp_setup_entry(struct irq_cfg *cfg, struct mp_chip_data *data,
2887 			   struct IO_APIC_route_entry *entry)
2888 {
2889 	memset(entry, 0, sizeof(*entry));
2890 	entry->delivery_mode = apic->irq_delivery_mode;
2891 	entry->dest_mode     = apic->irq_dest_mode;
2892 	entry->dest	     = cfg->dest_apicid;
2893 	entry->vector	     = cfg->vector;
2894 	entry->trigger	     = data->trigger;
2895 	entry->polarity	     = data->polarity;
2896 	/*
2897 	 * Mask level triggered irqs. Edge triggered irqs are masked
2898 	 * by the irq core code in case they fire.
2899 	 */
2900 	if (data->trigger == IOAPIC_LEVEL)
2901 		entry->mask = IOAPIC_MASKED;
2902 	else
2903 		entry->mask = IOAPIC_UNMASKED;
2904 }
2905 
2906 int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
2907 		       unsigned int nr_irqs, void *arg)
2908 {
2909 	int ret, ioapic, pin;
2910 	struct irq_cfg *cfg;
2911 	struct irq_data *irq_data;
2912 	struct mp_chip_data *data;
2913 	struct irq_alloc_info *info = arg;
2914 	unsigned long flags;
2915 
2916 	if (!info || nr_irqs > 1)
2917 		return -EINVAL;
2918 	irq_data = irq_domain_get_irq_data(domain, virq);
2919 	if (!irq_data)
2920 		return -EINVAL;
2921 
2922 	ioapic = mp_irqdomain_ioapic_idx(domain);
2923 	pin = info->ioapic_pin;
2924 	if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0)
2925 		return -EEXIST;
2926 
2927 	data = kzalloc(sizeof(*data), GFP_KERNEL);
2928 	if (!data)
2929 		return -ENOMEM;
2930 
2931 	info->ioapic_entry = &data->entry;
2932 	ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info);
2933 	if (ret < 0) {
2934 		kfree(data);
2935 		return ret;
2936 	}
2937 
2938 	INIT_LIST_HEAD(&data->irq_2_pin);
2939 	irq_data->hwirq = info->ioapic_pin;
2940 	irq_data->chip = (domain->parent == x86_vector_domain) ?
2941 			  &ioapic_chip : &ioapic_ir_chip;
2942 	irq_data->chip_data = data;
2943 	mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info);
2944 
2945 	cfg = irqd_cfg(irq_data);
2946 	add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin);
2947 
2948 	local_irq_save(flags);
2949 	if (info->ioapic_entry)
2950 		mp_setup_entry(cfg, data, info->ioapic_entry);
2951 	mp_register_handler(virq, data->trigger);
2952 	if (virq < nr_legacy_irqs())
2953 		legacy_pic->mask(virq);
2954 	local_irq_restore(flags);
2955 
2956 	apic_printk(APIC_VERBOSE, KERN_DEBUG
2957 		    "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i Dest:%d)\n",
2958 		    ioapic, mpc_ioapic_id(ioapic), pin, cfg->vector,
2959 		    virq, data->trigger, data->polarity, cfg->dest_apicid);
2960 
2961 	return 0;
2962 }
2963 
2964 void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
2965 		       unsigned int nr_irqs)
2966 {
2967 	struct irq_data *irq_data;
2968 	struct mp_chip_data *data;
2969 
2970 	BUG_ON(nr_irqs != 1);
2971 	irq_data = irq_domain_get_irq_data(domain, virq);
2972 	if (irq_data && irq_data->chip_data) {
2973 		data = irq_data->chip_data;
2974 		__remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain),
2975 				      (int)irq_data->hwirq);
2976 		WARN_ON(!list_empty(&data->irq_2_pin));
2977 		kfree(irq_data->chip_data);
2978 	}
2979 	irq_domain_free_irqs_top(domain, virq, nr_irqs);
2980 }
2981 
2982 int mp_irqdomain_activate(struct irq_domain *domain,
2983 			  struct irq_data *irq_data, bool reserve)
2984 {
2985 	unsigned long flags;
2986 
2987 	raw_spin_lock_irqsave(&ioapic_lock, flags);
2988 	ioapic_configure_entry(irq_data);
2989 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2990 	return 0;
2991 }
2992 
2993 void mp_irqdomain_deactivate(struct irq_domain *domain,
2994 			     struct irq_data *irq_data)
2995 {
2996 	/* It won't be called for IRQ with multiple IOAPIC pins associated */
2997 	ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain),
2998 			  (int)irq_data->hwirq);
2999 }
3000 
3001 int mp_irqdomain_ioapic_idx(struct irq_domain *domain)
3002 {
3003 	return (int)(long)domain->host_data;
3004 }
3005 
3006 const struct irq_domain_ops mp_ioapic_irqdomain_ops = {
3007 	.alloc		= mp_irqdomain_alloc,
3008 	.free		= mp_irqdomain_free,
3009 	.activate	= mp_irqdomain_activate,
3010 	.deactivate	= mp_irqdomain_deactivate,
3011 };
3012