1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Numascale NumaConnect-Specific APIC Code 7 * 8 * Copyright (C) 2011 Numascale AS. All rights reserved. 9 * 10 * Send feedback to <support@numascale.com> 11 * 12 */ 13 14 #include <linux/errno.h> 15 #include <linux/threads.h> 16 #include <linux/cpumask.h> 17 #include <linux/string.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/ctype.h> 21 #include <linux/init.h> 22 #include <linux/hardirq.h> 23 #include <linux/delay.h> 24 25 #include <asm/numachip/numachip_csr.h> 26 #include <asm/smp.h> 27 #include <asm/apic.h> 28 #include <asm/ipi.h> 29 #include <asm/apic_flat_64.h> 30 31 static int numachip_system __read_mostly; 32 33 static struct apic apic_numachip __read_mostly; 34 35 static unsigned int get_apic_id(unsigned long x) 36 { 37 unsigned long value; 38 unsigned int id; 39 40 rdmsrl(MSR_FAM10H_NODE_ID, value); 41 id = ((x >> 24) & 0xffU) | ((value << 2) & 0x3f00U); 42 43 return id; 44 } 45 46 static unsigned long set_apic_id(unsigned int id) 47 { 48 unsigned long x; 49 50 x = ((id & 0xffU) << 24); 51 return x; 52 } 53 54 static unsigned int read_xapic_id(void) 55 { 56 return get_apic_id(apic_read(APIC_ID)); 57 } 58 59 static int numachip_apic_id_registered(void) 60 { 61 return physid_isset(read_xapic_id(), phys_cpu_present_map); 62 } 63 64 static int numachip_phys_pkg_id(int initial_apic_id, int index_msb) 65 { 66 return initial_apic_id >> index_msb; 67 } 68 69 static const struct cpumask *numachip_target_cpus(void) 70 { 71 return cpu_online_mask; 72 } 73 74 static void numachip_vector_allocation_domain(int cpu, struct cpumask *retmask) 75 { 76 cpumask_clear(retmask); 77 cpumask_set_cpu(cpu, retmask); 78 } 79 80 static int __cpuinit numachip_wakeup_secondary(int phys_apicid, unsigned long start_rip) 81 { 82 union numachip_csr_g3_ext_irq_gen int_gen; 83 84 int_gen.s._destination_apic_id = phys_apicid; 85 int_gen.s._vector = 0; 86 int_gen.s._msgtype = APIC_DM_INIT >> 8; 87 int_gen.s._index = 0; 88 89 write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v); 90 91 int_gen.s._msgtype = APIC_DM_STARTUP >> 8; 92 int_gen.s._vector = start_rip >> 12; 93 94 write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v); 95 96 atomic_set(&init_deasserted, 1); 97 return 0; 98 } 99 100 static void numachip_send_IPI_one(int cpu, int vector) 101 { 102 union numachip_csr_g3_ext_irq_gen int_gen; 103 int apicid = per_cpu(x86_cpu_to_apicid, cpu); 104 105 int_gen.s._destination_apic_id = apicid; 106 int_gen.s._vector = vector; 107 int_gen.s._msgtype = (vector == NMI_VECTOR ? APIC_DM_NMI : APIC_DM_FIXED) >> 8; 108 int_gen.s._index = 0; 109 110 write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v); 111 } 112 113 static void numachip_send_IPI_mask(const struct cpumask *mask, int vector) 114 { 115 unsigned int cpu; 116 117 for_each_cpu(cpu, mask) 118 numachip_send_IPI_one(cpu, vector); 119 } 120 121 static void numachip_send_IPI_mask_allbutself(const struct cpumask *mask, 122 int vector) 123 { 124 unsigned int this_cpu = smp_processor_id(); 125 unsigned int cpu; 126 127 for_each_cpu(cpu, mask) { 128 if (cpu != this_cpu) 129 numachip_send_IPI_one(cpu, vector); 130 } 131 } 132 133 static void numachip_send_IPI_allbutself(int vector) 134 { 135 unsigned int this_cpu = smp_processor_id(); 136 unsigned int cpu; 137 138 for_each_online_cpu(cpu) { 139 if (cpu != this_cpu) 140 numachip_send_IPI_one(cpu, vector); 141 } 142 } 143 144 static void numachip_send_IPI_all(int vector) 145 { 146 numachip_send_IPI_mask(cpu_online_mask, vector); 147 } 148 149 static void numachip_send_IPI_self(int vector) 150 { 151 __default_send_IPI_shortcut(APIC_DEST_SELF, vector, APIC_DEST_PHYSICAL); 152 } 153 154 static unsigned int numachip_cpu_mask_to_apicid(const struct cpumask *cpumask) 155 { 156 int cpu; 157 158 /* 159 * We're using fixed IRQ delivery, can only return one phys APIC ID. 160 * May as well be the first. 161 */ 162 cpu = cpumask_first(cpumask); 163 if (likely((unsigned)cpu < nr_cpu_ids)) 164 return per_cpu(x86_cpu_to_apicid, cpu); 165 166 return BAD_APICID; 167 } 168 169 static unsigned int 170 numachip_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 171 const struct cpumask *andmask) 172 { 173 int cpu; 174 175 /* 176 * We're using fixed IRQ delivery, can only return one phys APIC ID. 177 * May as well be the first. 178 */ 179 for_each_cpu_and(cpu, cpumask, andmask) { 180 if (cpumask_test_cpu(cpu, cpu_online_mask)) 181 break; 182 } 183 return per_cpu(x86_cpu_to_apicid, cpu); 184 } 185 186 static int __init numachip_probe(void) 187 { 188 return apic == &apic_numachip; 189 } 190 191 static void __init map_csrs(void) 192 { 193 printk(KERN_INFO "NumaChip: Mapping local CSR space (%016llx - %016llx)\n", 194 NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_BASE + NUMACHIP_LCSR_SIZE - 1); 195 init_extra_mapping_uc(NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_SIZE); 196 197 printk(KERN_INFO "NumaChip: Mapping global CSR space (%016llx - %016llx)\n", 198 NUMACHIP_GCSR_BASE, NUMACHIP_GCSR_BASE + NUMACHIP_GCSR_SIZE - 1); 199 init_extra_mapping_uc(NUMACHIP_GCSR_BASE, NUMACHIP_GCSR_SIZE); 200 } 201 202 static void fixup_cpu_id(struct cpuinfo_x86 *c, int node) 203 { 204 c->phys_proc_id = node; 205 per_cpu(cpu_llc_id, smp_processor_id()) = node; 206 } 207 208 static int __init numachip_system_init(void) 209 { 210 unsigned int val; 211 212 if (!numachip_system) 213 return 0; 214 215 x86_cpuinit.fixup_cpu_id = fixup_cpu_id; 216 217 map_csrs(); 218 219 val = read_lcsr(CSR_G0_NODE_IDS); 220 printk(KERN_INFO "NumaChip: Local NodeID = %08x\n", val); 221 222 return 0; 223 } 224 early_initcall(numachip_system_init); 225 226 static int numachip_acpi_madt_oem_check(char *oem_id, char *oem_table_id) 227 { 228 if (!strncmp(oem_id, "NUMASC", 6)) { 229 numachip_system = 1; 230 return 1; 231 } 232 233 return 0; 234 } 235 236 static struct apic apic_numachip __refconst = { 237 238 .name = "NumaConnect system", 239 .probe = numachip_probe, 240 .acpi_madt_oem_check = numachip_acpi_madt_oem_check, 241 .apic_id_registered = numachip_apic_id_registered, 242 243 .irq_delivery_mode = dest_Fixed, 244 .irq_dest_mode = 0, /* physical */ 245 246 .target_cpus = numachip_target_cpus, 247 .disable_esr = 0, 248 .dest_logical = 0, 249 .check_apicid_used = NULL, 250 .check_apicid_present = NULL, 251 252 .vector_allocation_domain = numachip_vector_allocation_domain, 253 .init_apic_ldr = flat_init_apic_ldr, 254 255 .ioapic_phys_id_map = NULL, 256 .setup_apic_routing = NULL, 257 .multi_timer_check = NULL, 258 .cpu_present_to_apicid = default_cpu_present_to_apicid, 259 .apicid_to_cpu_present = NULL, 260 .setup_portio_remap = NULL, 261 .check_phys_apicid_present = default_check_phys_apicid_present, 262 .enable_apic_mode = NULL, 263 .phys_pkg_id = numachip_phys_pkg_id, 264 .mps_oem_check = NULL, 265 266 .get_apic_id = get_apic_id, 267 .set_apic_id = set_apic_id, 268 .apic_id_mask = 0xffU << 24, 269 270 .cpu_mask_to_apicid = numachip_cpu_mask_to_apicid, 271 .cpu_mask_to_apicid_and = numachip_cpu_mask_to_apicid_and, 272 273 .send_IPI_mask = numachip_send_IPI_mask, 274 .send_IPI_mask_allbutself = numachip_send_IPI_mask_allbutself, 275 .send_IPI_allbutself = numachip_send_IPI_allbutself, 276 .send_IPI_all = numachip_send_IPI_all, 277 .send_IPI_self = numachip_send_IPI_self, 278 279 .wakeup_secondary_cpu = numachip_wakeup_secondary, 280 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW, 281 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH, 282 .wait_for_init_deassert = NULL, 283 .smp_callin_clear_local_apic = NULL, 284 .inquire_remote_apic = NULL, /* REMRD not supported */ 285 286 .read = native_apic_mem_read, 287 .write = native_apic_mem_write, 288 .icr_read = native_apic_icr_read, 289 .icr_write = native_apic_icr_write, 290 .wait_icr_idle = native_apic_wait_icr_idle, 291 .safe_wait_icr_idle = native_safe_apic_wait_icr_idle, 292 }; 293 apic_driver(apic_numachip); 294 295