1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Numascale NumaConnect-Specific APIC Code 7 * 8 * Copyright (C) 2011 Numascale AS. All rights reserved. 9 * 10 * Send feedback to <support@numascale.com> 11 * 12 */ 13 #include <linux/types.h> 14 #include <linux/init.h> 15 #include <linux/pgtable.h> 16 17 #include <asm/numachip/numachip.h> 18 #include <asm/numachip/numachip_csr.h> 19 20 21 #include "local.h" 22 23 u8 numachip_system __read_mostly; 24 static const struct apic apic_numachip1; 25 static const struct apic apic_numachip2; 26 static void (*numachip_apic_icr_write)(int apicid, unsigned int val) __read_mostly; 27 28 static u32 numachip1_get_apic_id(u32 x) 29 { 30 unsigned long value; 31 unsigned int id = (x >> 24) & 0xff; 32 33 if (static_cpu_has(X86_FEATURE_NODEID_MSR)) { 34 rdmsrl(MSR_FAM10H_NODE_ID, value); 35 id |= (value << 2) & 0xff00; 36 } 37 38 return id; 39 } 40 41 static u32 numachip1_set_apic_id(u32 id) 42 { 43 return (id & 0xff) << 24; 44 } 45 46 static u32 numachip2_get_apic_id(u32 x) 47 { 48 u64 mcfg; 49 50 rdmsrl(MSR_FAM10H_MMIO_CONF_BASE, mcfg); 51 return ((mcfg >> (28 - 8)) & 0xfff00) | (x >> 24); 52 } 53 54 static u32 numachip2_set_apic_id(u32 id) 55 { 56 return id << 24; 57 } 58 59 static void numachip1_apic_icr_write(int apicid, unsigned int val) 60 { 61 write_lcsr(CSR_G3_EXT_IRQ_GEN, (apicid << 16) | val); 62 } 63 64 static void numachip2_apic_icr_write(int apicid, unsigned int val) 65 { 66 numachip2_write32_lcsr(NUMACHIP2_APIC_ICR, (apicid << 12) | val); 67 } 68 69 static int numachip_wakeup_secondary(u32 phys_apicid, unsigned long start_rip) 70 { 71 numachip_apic_icr_write(phys_apicid, APIC_DM_INIT); 72 numachip_apic_icr_write(phys_apicid, APIC_DM_STARTUP | 73 (start_rip >> 12)); 74 75 return 0; 76 } 77 78 static void numachip_send_IPI_one(int cpu, int vector) 79 { 80 int local_apicid, apicid = per_cpu(x86_cpu_to_apicid, cpu); 81 unsigned int dmode; 82 83 preempt_disable(); 84 local_apicid = __this_cpu_read(x86_cpu_to_apicid); 85 86 /* Send via local APIC where non-local part matches */ 87 if (!((apicid ^ local_apicid) >> NUMACHIP_LAPIC_BITS)) { 88 unsigned long flags; 89 90 local_irq_save(flags); 91 __default_send_IPI_dest_field(apicid, vector, 92 APIC_DEST_PHYSICAL); 93 local_irq_restore(flags); 94 preempt_enable(); 95 return; 96 } 97 preempt_enable(); 98 99 dmode = (vector == NMI_VECTOR) ? APIC_DM_NMI : APIC_DM_FIXED; 100 numachip_apic_icr_write(apicid, dmode | vector); 101 } 102 103 static void numachip_send_IPI_mask(const struct cpumask *mask, int vector) 104 { 105 unsigned int cpu; 106 107 for_each_cpu(cpu, mask) 108 numachip_send_IPI_one(cpu, vector); 109 } 110 111 static void numachip_send_IPI_mask_allbutself(const struct cpumask *mask, 112 int vector) 113 { 114 unsigned int this_cpu = smp_processor_id(); 115 unsigned int cpu; 116 117 for_each_cpu(cpu, mask) { 118 if (cpu != this_cpu) 119 numachip_send_IPI_one(cpu, vector); 120 } 121 } 122 123 static void numachip_send_IPI_allbutself(int vector) 124 { 125 unsigned int this_cpu = smp_processor_id(); 126 unsigned int cpu; 127 128 for_each_online_cpu(cpu) { 129 if (cpu != this_cpu) 130 numachip_send_IPI_one(cpu, vector); 131 } 132 } 133 134 static void numachip_send_IPI_all(int vector) 135 { 136 numachip_send_IPI_mask(cpu_online_mask, vector); 137 } 138 139 static void numachip_send_IPI_self(int vector) 140 { 141 apic_write(APIC_SELF_IPI, vector); 142 } 143 144 static int __init numachip1_probe(void) 145 { 146 return apic == &apic_numachip1; 147 } 148 149 static int __init numachip2_probe(void) 150 { 151 return apic == &apic_numachip2; 152 } 153 154 static void fixup_cpu_id(struct cpuinfo_x86 *c, int node) 155 { 156 u64 val; 157 u32 nodes = 1; 158 159 c->topo.llc_id = node; 160 161 /* Account for nodes per socket in multi-core-module processors */ 162 if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) { 163 rdmsrl(MSR_FAM10H_NODE_ID, val); 164 nodes = ((val >> 3) & 7) + 1; 165 } 166 167 c->topo.pkg_id = node / nodes; 168 } 169 170 static int __init numachip_system_init(void) 171 { 172 /* Map the LCSR area and set up the apic_icr_write function */ 173 switch (numachip_system) { 174 case 1: 175 init_extra_mapping_uc(NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_SIZE); 176 numachip_apic_icr_write = numachip1_apic_icr_write; 177 break; 178 case 2: 179 init_extra_mapping_uc(NUMACHIP2_LCSR_BASE, NUMACHIP2_LCSR_SIZE); 180 numachip_apic_icr_write = numachip2_apic_icr_write; 181 break; 182 default: 183 return 0; 184 } 185 186 x86_cpuinit.fixup_cpu_id = fixup_cpu_id; 187 x86_init.pci.arch_init = pci_numachip_init; 188 189 return 0; 190 } 191 early_initcall(numachip_system_init); 192 193 static int numachip1_acpi_madt_oem_check(char *oem_id, char *oem_table_id) 194 { 195 if ((strncmp(oem_id, "NUMASC", 6) != 0) || 196 (strncmp(oem_table_id, "NCONNECT", 8) != 0)) 197 return 0; 198 199 numachip_system = 1; 200 201 return 1; 202 } 203 204 static int numachip2_acpi_madt_oem_check(char *oem_id, char *oem_table_id) 205 { 206 if ((strncmp(oem_id, "NUMASC", 6) != 0) || 207 (strncmp(oem_table_id, "NCONECT2", 8) != 0)) 208 return 0; 209 210 numachip_system = 2; 211 212 return 1; 213 } 214 215 static const struct apic apic_numachip1 __refconst = { 216 .name = "NumaConnect system", 217 .probe = numachip1_probe, 218 .acpi_madt_oem_check = numachip1_acpi_madt_oem_check, 219 220 .dest_mode_logical = false, 221 222 .disable_esr = 0, 223 224 .cpu_present_to_apicid = default_cpu_present_to_apicid, 225 226 .max_apic_id = UINT_MAX, 227 .get_apic_id = numachip1_get_apic_id, 228 .set_apic_id = numachip1_set_apic_id, 229 230 .calc_dest_apicid = apic_default_calc_apicid, 231 232 .send_IPI = numachip_send_IPI_one, 233 .send_IPI_mask = numachip_send_IPI_mask, 234 .send_IPI_mask_allbutself = numachip_send_IPI_mask_allbutself, 235 .send_IPI_allbutself = numachip_send_IPI_allbutself, 236 .send_IPI_all = numachip_send_IPI_all, 237 .send_IPI_self = numachip_send_IPI_self, 238 239 .wakeup_secondary_cpu = numachip_wakeup_secondary, 240 241 .read = native_apic_mem_read, 242 .write = native_apic_mem_write, 243 .eoi = native_apic_mem_eoi, 244 .icr_read = native_apic_icr_read, 245 .icr_write = native_apic_icr_write, 246 }; 247 248 apic_driver(apic_numachip1); 249 250 static const struct apic apic_numachip2 __refconst = { 251 .name = "NumaConnect2 system", 252 .probe = numachip2_probe, 253 .acpi_madt_oem_check = numachip2_acpi_madt_oem_check, 254 255 .dest_mode_logical = false, 256 257 .disable_esr = 0, 258 259 .cpu_present_to_apicid = default_cpu_present_to_apicid, 260 261 .max_apic_id = UINT_MAX, 262 .get_apic_id = numachip2_get_apic_id, 263 .set_apic_id = numachip2_set_apic_id, 264 265 .calc_dest_apicid = apic_default_calc_apicid, 266 267 .send_IPI = numachip_send_IPI_one, 268 .send_IPI_mask = numachip_send_IPI_mask, 269 .send_IPI_mask_allbutself = numachip_send_IPI_mask_allbutself, 270 .send_IPI_allbutself = numachip_send_IPI_allbutself, 271 .send_IPI_all = numachip_send_IPI_all, 272 .send_IPI_self = numachip_send_IPI_self, 273 274 .wakeup_secondary_cpu = numachip_wakeup_secondary, 275 276 .read = native_apic_mem_read, 277 .write = native_apic_mem_write, 278 .eoi = native_apic_mem_eoi, 279 .icr_read = native_apic_icr_read, 280 .icr_write = native_apic_icr_write, 281 }; 282 283 apic_driver(apic_numachip2); 284