1 /* 2 * Local APIC handling, local APIC timers 3 * 4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5 * 6 * Fixes 7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8 * thanks to Eric Gilmore 9 * and Rolf G. Tews 10 * for testing these extensively. 11 * Maciej W. Rozycki : Various updates and fixes. 12 * Mikael Pettersson : Power Management for UP-APIC. 13 * Pavel Machek and 14 * Mikael Pettersson : PM converted to driver model. 15 */ 16 17 #include <linux/perf_event.h> 18 #include <linux/kernel_stat.h> 19 #include <linux/mc146818rtc.h> 20 #include <linux/acpi_pmtmr.h> 21 #include <linux/clockchips.h> 22 #include <linux/interrupt.h> 23 #include <linux/bootmem.h> 24 #include <linux/ftrace.h> 25 #include <linux/ioport.h> 26 #include <linux/module.h> 27 #include <linux/syscore_ops.h> 28 #include <linux/delay.h> 29 #include <linux/timex.h> 30 #include <linux/dmar.h> 31 #include <linux/init.h> 32 #include <linux/cpu.h> 33 #include <linux/dmi.h> 34 #include <linux/smp.h> 35 #include <linux/mm.h> 36 37 #include <asm/perf_event.h> 38 #include <asm/x86_init.h> 39 #include <asm/pgalloc.h> 40 #include <asm/atomic.h> 41 #include <asm/mpspec.h> 42 #include <asm/i8253.h> 43 #include <asm/i8259.h> 44 #include <asm/proto.h> 45 #include <asm/apic.h> 46 #include <asm/io_apic.h> 47 #include <asm/desc.h> 48 #include <asm/hpet.h> 49 #include <asm/idle.h> 50 #include <asm/mtrr.h> 51 #include <asm/smp.h> 52 #include <asm/mce.h> 53 #include <asm/tsc.h> 54 #include <asm/hypervisor.h> 55 56 unsigned int num_processors; 57 58 unsigned disabled_cpus __cpuinitdata; 59 60 /* Processor that is doing the boot up */ 61 unsigned int boot_cpu_physical_apicid = -1U; 62 63 /* 64 * The highest APIC ID seen during enumeration. 65 */ 66 unsigned int max_physical_apicid; 67 68 /* 69 * Bitmask of physically existing CPUs: 70 */ 71 physid_mask_t phys_cpu_present_map; 72 73 /* 74 * Map cpu index to physical APIC ID 75 */ 76 DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID); 77 DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID); 78 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 79 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 80 81 #ifdef CONFIG_X86_32 82 83 /* 84 * On x86_32, the mapping between cpu and logical apicid may vary 85 * depending on apic in use. The following early percpu variable is 86 * used for the mapping. This is where the behaviors of x86_64 and 32 87 * actually diverge. Let's keep it ugly for now. 88 */ 89 DEFINE_EARLY_PER_CPU(int, x86_cpu_to_logical_apicid, BAD_APICID); 90 91 /* 92 * Knob to control our willingness to enable the local APIC. 93 * 94 * +1=force-enable 95 */ 96 static int force_enable_local_apic __initdata; 97 /* 98 * APIC command line parameters 99 */ 100 static int __init parse_lapic(char *arg) 101 { 102 force_enable_local_apic = 1; 103 return 0; 104 } 105 early_param("lapic", parse_lapic); 106 /* Local APIC was disabled by the BIOS and enabled by the kernel */ 107 static int enabled_via_apicbase; 108 109 /* 110 * Handle interrupt mode configuration register (IMCR). 111 * This register controls whether the interrupt signals 112 * that reach the BSP come from the master PIC or from the 113 * local APIC. Before entering Symmetric I/O Mode, either 114 * the BIOS or the operating system must switch out of 115 * PIC Mode by changing the IMCR. 116 */ 117 static inline void imcr_pic_to_apic(void) 118 { 119 /* select IMCR register */ 120 outb(0x70, 0x22); 121 /* NMI and 8259 INTR go through APIC */ 122 outb(0x01, 0x23); 123 } 124 125 static inline void imcr_apic_to_pic(void) 126 { 127 /* select IMCR register */ 128 outb(0x70, 0x22); 129 /* NMI and 8259 INTR go directly to BSP */ 130 outb(0x00, 0x23); 131 } 132 #endif 133 134 #ifdef CONFIG_X86_64 135 static int apic_calibrate_pmtmr __initdata; 136 static __init int setup_apicpmtimer(char *s) 137 { 138 apic_calibrate_pmtmr = 1; 139 notsc_setup(NULL); 140 return 0; 141 } 142 __setup("apicpmtimer", setup_apicpmtimer); 143 #endif 144 145 int x2apic_mode; 146 #ifdef CONFIG_X86_X2APIC 147 /* x2apic enabled before OS handover */ 148 static int x2apic_preenabled; 149 static __init int setup_nox2apic(char *str) 150 { 151 if (x2apic_enabled()) { 152 pr_warning("Bios already enabled x2apic, " 153 "can't enforce nox2apic"); 154 return 0; 155 } 156 157 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 158 return 0; 159 } 160 early_param("nox2apic", setup_nox2apic); 161 #endif 162 163 unsigned long mp_lapic_addr; 164 int disable_apic; 165 /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 166 static int disable_apic_timer __initdata; 167 /* Local APIC timer works in C2 */ 168 int local_apic_timer_c2_ok; 169 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 170 171 int first_system_vector = 0xfe; 172 173 /* 174 * Debug level, exported for io_apic.c 175 */ 176 unsigned int apic_verbosity; 177 178 int pic_mode; 179 180 /* Have we found an MP table */ 181 int smp_found_config; 182 183 static struct resource lapic_resource = { 184 .name = "Local APIC", 185 .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 186 }; 187 188 static unsigned int calibration_result; 189 190 static void apic_pm_activate(void); 191 192 static unsigned long apic_phys; 193 194 /* 195 * Get the LAPIC version 196 */ 197 static inline int lapic_get_version(void) 198 { 199 return GET_APIC_VERSION(apic_read(APIC_LVR)); 200 } 201 202 /* 203 * Check, if the APIC is integrated or a separate chip 204 */ 205 static inline int lapic_is_integrated(void) 206 { 207 #ifdef CONFIG_X86_64 208 return 1; 209 #else 210 return APIC_INTEGRATED(lapic_get_version()); 211 #endif 212 } 213 214 /* 215 * Check, whether this is a modern or a first generation APIC 216 */ 217 static int modern_apic(void) 218 { 219 /* AMD systems use old APIC versions, so check the CPU */ 220 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 221 boot_cpu_data.x86 >= 0xf) 222 return 1; 223 return lapic_get_version() >= 0x14; 224 } 225 226 /* 227 * right after this call apic become NOOP driven 228 * so apic->write/read doesn't do anything 229 */ 230 static void __init apic_disable(void) 231 { 232 pr_info("APIC: switched to apic NOOP\n"); 233 apic = &apic_noop; 234 } 235 236 void native_apic_wait_icr_idle(void) 237 { 238 while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 239 cpu_relax(); 240 } 241 242 u32 native_safe_apic_wait_icr_idle(void) 243 { 244 u32 send_status; 245 int timeout; 246 247 timeout = 0; 248 do { 249 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 250 if (!send_status) 251 break; 252 udelay(100); 253 } while (timeout++ < 1000); 254 255 return send_status; 256 } 257 258 void native_apic_icr_write(u32 low, u32 id) 259 { 260 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 261 apic_write(APIC_ICR, low); 262 } 263 264 u64 native_apic_icr_read(void) 265 { 266 u32 icr1, icr2; 267 268 icr2 = apic_read(APIC_ICR2); 269 icr1 = apic_read(APIC_ICR); 270 271 return icr1 | ((u64)icr2 << 32); 272 } 273 274 #ifdef CONFIG_X86_32 275 /** 276 * get_physical_broadcast - Get number of physical broadcast IDs 277 */ 278 int get_physical_broadcast(void) 279 { 280 return modern_apic() ? 0xff : 0xf; 281 } 282 #endif 283 284 /** 285 * lapic_get_maxlvt - get the maximum number of local vector table entries 286 */ 287 int lapic_get_maxlvt(void) 288 { 289 unsigned int v; 290 291 v = apic_read(APIC_LVR); 292 /* 293 * - we always have APIC integrated on 64bit mode 294 * - 82489DXs do not report # of LVT entries 295 */ 296 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; 297 } 298 299 /* 300 * Local APIC timer 301 */ 302 303 /* Clock divisor */ 304 #define APIC_DIVISOR 16 305 306 /* 307 * This function sets up the local APIC timer, with a timeout of 308 * 'clocks' APIC bus clock. During calibration we actually call 309 * this function twice on the boot CPU, once with a bogus timeout 310 * value, second time for real. The other (noncalibrating) CPUs 311 * call this function only once, with the real, calibrated value. 312 * 313 * We do reads before writes even if unnecessary, to get around the 314 * P5 APIC double write bug. 315 */ 316 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 317 { 318 unsigned int lvtt_value, tmp_value; 319 320 lvtt_value = LOCAL_TIMER_VECTOR; 321 if (!oneshot) 322 lvtt_value |= APIC_LVT_TIMER_PERIODIC; 323 if (!lapic_is_integrated()) 324 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 325 326 if (!irqen) 327 lvtt_value |= APIC_LVT_MASKED; 328 329 apic_write(APIC_LVTT, lvtt_value); 330 331 /* 332 * Divide PICLK by 16 333 */ 334 tmp_value = apic_read(APIC_TDCR); 335 apic_write(APIC_TDCR, 336 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 337 APIC_TDR_DIV_16); 338 339 if (!oneshot) 340 apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 341 } 342 343 /* 344 * Setup extended LVT, AMD specific 345 * 346 * Software should use the LVT offsets the BIOS provides. The offsets 347 * are determined by the subsystems using it like those for MCE 348 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 349 * are supported. Beginning with family 10h at least 4 offsets are 350 * available. 351 * 352 * Since the offsets must be consistent for all cores, we keep track 353 * of the LVT offsets in software and reserve the offset for the same 354 * vector also to be used on other cores. An offset is freed by 355 * setting the entry to APIC_EILVT_MASKED. 356 * 357 * If the BIOS is right, there should be no conflicts. Otherwise a 358 * "[Firmware Bug]: ..." error message is generated. However, if 359 * software does not properly determines the offsets, it is not 360 * necessarily a BIOS bug. 361 */ 362 363 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 364 365 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 366 { 367 return (old & APIC_EILVT_MASKED) 368 || (new == APIC_EILVT_MASKED) 369 || ((new & ~APIC_EILVT_MASKED) == old); 370 } 371 372 static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 373 { 374 unsigned int rsvd; /* 0: uninitialized */ 375 376 if (offset >= APIC_EILVT_NR_MAX) 377 return ~0; 378 379 rsvd = atomic_read(&eilvt_offsets[offset]) & ~APIC_EILVT_MASKED; 380 do { 381 if (rsvd && 382 !eilvt_entry_is_changeable(rsvd, new)) 383 /* may not change if vectors are different */ 384 return rsvd; 385 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 386 } while (rsvd != new); 387 388 return new; 389 } 390 391 /* 392 * If mask=1, the LVT entry does not generate interrupts while mask=0 393 * enables the vector. See also the BKDGs. Must be called with 394 * preemption disabled. 395 */ 396 397 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 398 { 399 unsigned long reg = APIC_EILVTn(offset); 400 unsigned int new, old, reserved; 401 402 new = (mask << 16) | (msg_type << 8) | vector; 403 old = apic_read(reg); 404 reserved = reserve_eilvt_offset(offset, new); 405 406 if (reserved != new) { 407 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 408 "vector 0x%x, but the register is already in use for " 409 "vector 0x%x on another cpu\n", 410 smp_processor_id(), reg, offset, new, reserved); 411 return -EINVAL; 412 } 413 414 if (!eilvt_entry_is_changeable(old, new)) { 415 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 416 "vector 0x%x, but the register is already in use for " 417 "vector 0x%x on this cpu\n", 418 smp_processor_id(), reg, offset, new, old); 419 return -EBUSY; 420 } 421 422 apic_write(reg, new); 423 424 return 0; 425 } 426 EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 427 428 /* 429 * Program the next event, relative to now 430 */ 431 static int lapic_next_event(unsigned long delta, 432 struct clock_event_device *evt) 433 { 434 apic_write(APIC_TMICT, delta); 435 return 0; 436 } 437 438 /* 439 * Setup the lapic timer in periodic or oneshot mode 440 */ 441 static void lapic_timer_setup(enum clock_event_mode mode, 442 struct clock_event_device *evt) 443 { 444 unsigned long flags; 445 unsigned int v; 446 447 /* Lapic used as dummy for broadcast ? */ 448 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 449 return; 450 451 local_irq_save(flags); 452 453 switch (mode) { 454 case CLOCK_EVT_MODE_PERIODIC: 455 case CLOCK_EVT_MODE_ONESHOT: 456 __setup_APIC_LVTT(calibration_result, 457 mode != CLOCK_EVT_MODE_PERIODIC, 1); 458 break; 459 case CLOCK_EVT_MODE_UNUSED: 460 case CLOCK_EVT_MODE_SHUTDOWN: 461 v = apic_read(APIC_LVTT); 462 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 463 apic_write(APIC_LVTT, v); 464 apic_write(APIC_TMICT, 0); 465 break; 466 case CLOCK_EVT_MODE_RESUME: 467 /* Nothing to do here */ 468 break; 469 } 470 471 local_irq_restore(flags); 472 } 473 474 /* 475 * Local APIC timer broadcast function 476 */ 477 static void lapic_timer_broadcast(const struct cpumask *mask) 478 { 479 #ifdef CONFIG_SMP 480 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 481 #endif 482 } 483 484 485 /* 486 * The local apic timer can be used for any function which is CPU local. 487 */ 488 static struct clock_event_device lapic_clockevent = { 489 .name = "lapic", 490 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT 491 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, 492 .shift = 32, 493 .set_mode = lapic_timer_setup, 494 .set_next_event = lapic_next_event, 495 .broadcast = lapic_timer_broadcast, 496 .rating = 100, 497 .irq = -1, 498 }; 499 static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 500 501 /* 502 * Setup the local APIC timer for this CPU. Copy the initialized values 503 * of the boot CPU and register the clock event in the framework. 504 */ 505 static void __cpuinit setup_APIC_timer(void) 506 { 507 struct clock_event_device *levt = &__get_cpu_var(lapic_events); 508 509 if (this_cpu_has(X86_FEATURE_ARAT)) { 510 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 511 /* Make LAPIC timer preferrable over percpu HPET */ 512 lapic_clockevent.rating = 150; 513 } 514 515 memcpy(levt, &lapic_clockevent, sizeof(*levt)); 516 levt->cpumask = cpumask_of(smp_processor_id()); 517 518 clockevents_register_device(levt); 519 } 520 521 /* 522 * In this functions we calibrate APIC bus clocks to the external timer. 523 * 524 * We want to do the calibration only once since we want to have local timer 525 * irqs syncron. CPUs connected by the same APIC bus have the very same bus 526 * frequency. 527 * 528 * This was previously done by reading the PIT/HPET and waiting for a wrap 529 * around to find out, that a tick has elapsed. I have a box, where the PIT 530 * readout is broken, so it never gets out of the wait loop again. This was 531 * also reported by others. 532 * 533 * Monitoring the jiffies value is inaccurate and the clockevents 534 * infrastructure allows us to do a simple substitution of the interrupt 535 * handler. 536 * 537 * The calibration routine also uses the pm_timer when possible, as the PIT 538 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 539 * back to normal later in the boot process). 540 */ 541 542 #define LAPIC_CAL_LOOPS (HZ/10) 543 544 static __initdata int lapic_cal_loops = -1; 545 static __initdata long lapic_cal_t1, lapic_cal_t2; 546 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 547 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 548 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 549 550 /* 551 * Temporary interrupt handler. 552 */ 553 static void __init lapic_cal_handler(struct clock_event_device *dev) 554 { 555 unsigned long long tsc = 0; 556 long tapic = apic_read(APIC_TMCCT); 557 unsigned long pm = acpi_pm_read_early(); 558 559 if (cpu_has_tsc) 560 rdtscll(tsc); 561 562 switch (lapic_cal_loops++) { 563 case 0: 564 lapic_cal_t1 = tapic; 565 lapic_cal_tsc1 = tsc; 566 lapic_cal_pm1 = pm; 567 lapic_cal_j1 = jiffies; 568 break; 569 570 case LAPIC_CAL_LOOPS: 571 lapic_cal_t2 = tapic; 572 lapic_cal_tsc2 = tsc; 573 if (pm < lapic_cal_pm1) 574 pm += ACPI_PM_OVRRUN; 575 lapic_cal_pm2 = pm; 576 lapic_cal_j2 = jiffies; 577 break; 578 } 579 } 580 581 static int __init 582 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 583 { 584 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 585 const long pm_thresh = pm_100ms / 100; 586 unsigned long mult; 587 u64 res; 588 589 #ifndef CONFIG_X86_PM_TIMER 590 return -1; 591 #endif 592 593 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 594 595 /* Check, if the PM timer is available */ 596 if (!deltapm) 597 return -1; 598 599 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 600 601 if (deltapm > (pm_100ms - pm_thresh) && 602 deltapm < (pm_100ms + pm_thresh)) { 603 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 604 return 0; 605 } 606 607 res = (((u64)deltapm) * mult) >> 22; 608 do_div(res, 1000000); 609 pr_warning("APIC calibration not consistent " 610 "with PM-Timer: %ldms instead of 100ms\n",(long)res); 611 612 /* Correct the lapic counter value */ 613 res = (((u64)(*delta)) * pm_100ms); 614 do_div(res, deltapm); 615 pr_info("APIC delta adjusted to PM-Timer: " 616 "%lu (%ld)\n", (unsigned long)res, *delta); 617 *delta = (long)res; 618 619 /* Correct the tsc counter value */ 620 if (cpu_has_tsc) { 621 res = (((u64)(*deltatsc)) * pm_100ms); 622 do_div(res, deltapm); 623 apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 624 "PM-Timer: %lu (%ld)\n", 625 (unsigned long)res, *deltatsc); 626 *deltatsc = (long)res; 627 } 628 629 return 0; 630 } 631 632 static int __init calibrate_APIC_clock(void) 633 { 634 struct clock_event_device *levt = &__get_cpu_var(lapic_events); 635 void (*real_handler)(struct clock_event_device *dev); 636 unsigned long deltaj; 637 long delta, deltatsc; 638 int pm_referenced = 0; 639 640 local_irq_disable(); 641 642 /* Replace the global interrupt handler */ 643 real_handler = global_clock_event->event_handler; 644 global_clock_event->event_handler = lapic_cal_handler; 645 646 /* 647 * Setup the APIC counter to maximum. There is no way the lapic 648 * can underflow in the 100ms detection time frame 649 */ 650 __setup_APIC_LVTT(0xffffffff, 0, 0); 651 652 /* Let the interrupts run */ 653 local_irq_enable(); 654 655 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 656 cpu_relax(); 657 658 local_irq_disable(); 659 660 /* Restore the real event handler */ 661 global_clock_event->event_handler = real_handler; 662 663 /* Build delta t1-t2 as apic timer counts down */ 664 delta = lapic_cal_t1 - lapic_cal_t2; 665 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 666 667 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 668 669 /* we trust the PM based calibration if possible */ 670 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 671 &delta, &deltatsc); 672 673 /* Calculate the scaled math multiplication factor */ 674 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 675 lapic_clockevent.shift); 676 lapic_clockevent.max_delta_ns = 677 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 678 lapic_clockevent.min_delta_ns = 679 clockevent_delta2ns(0xF, &lapic_clockevent); 680 681 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 682 683 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 684 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 685 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 686 calibration_result); 687 688 if (cpu_has_tsc) { 689 apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 690 "%ld.%04ld MHz.\n", 691 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 692 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 693 } 694 695 apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 696 "%u.%04u MHz.\n", 697 calibration_result / (1000000 / HZ), 698 calibration_result % (1000000 / HZ)); 699 700 /* 701 * Do a sanity check on the APIC calibration result 702 */ 703 if (calibration_result < (1000000 / HZ)) { 704 local_irq_enable(); 705 pr_warning("APIC frequency too slow, disabling apic timer\n"); 706 return -1; 707 } 708 709 levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 710 711 /* 712 * PM timer calibration failed or not turned on 713 * so lets try APIC timer based calibration 714 */ 715 if (!pm_referenced) { 716 apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 717 718 /* 719 * Setup the apic timer manually 720 */ 721 levt->event_handler = lapic_cal_handler; 722 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); 723 lapic_cal_loops = -1; 724 725 /* Let the interrupts run */ 726 local_irq_enable(); 727 728 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 729 cpu_relax(); 730 731 /* Stop the lapic timer */ 732 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); 733 734 /* Jiffies delta */ 735 deltaj = lapic_cal_j2 - lapic_cal_j1; 736 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 737 738 /* Check, if the jiffies result is consistent */ 739 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 740 apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 741 else 742 levt->features |= CLOCK_EVT_FEAT_DUMMY; 743 } else 744 local_irq_enable(); 745 746 if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 747 pr_warning("APIC timer disabled due to verification failure\n"); 748 return -1; 749 } 750 751 return 0; 752 } 753 754 /* 755 * Setup the boot APIC 756 * 757 * Calibrate and verify the result. 758 */ 759 void __init setup_boot_APIC_clock(void) 760 { 761 /* 762 * The local apic timer can be disabled via the kernel 763 * commandline or from the CPU detection code. Register the lapic 764 * timer as a dummy clock event source on SMP systems, so the 765 * broadcast mechanism is used. On UP systems simply ignore it. 766 */ 767 if (disable_apic_timer) { 768 pr_info("Disabling APIC timer\n"); 769 /* No broadcast on UP ! */ 770 if (num_possible_cpus() > 1) { 771 lapic_clockevent.mult = 1; 772 setup_APIC_timer(); 773 } 774 return; 775 } 776 777 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 778 "calibrating APIC timer ...\n"); 779 780 if (calibrate_APIC_clock()) { 781 /* No broadcast on UP ! */ 782 if (num_possible_cpus() > 1) 783 setup_APIC_timer(); 784 return; 785 } 786 787 /* 788 * If nmi_watchdog is set to IO_APIC, we need the 789 * PIT/HPET going. Otherwise register lapic as a dummy 790 * device. 791 */ 792 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 793 794 /* Setup the lapic or request the broadcast */ 795 setup_APIC_timer(); 796 } 797 798 void __cpuinit setup_secondary_APIC_clock(void) 799 { 800 setup_APIC_timer(); 801 } 802 803 /* 804 * The guts of the apic timer interrupt 805 */ 806 static void local_apic_timer_interrupt(void) 807 { 808 int cpu = smp_processor_id(); 809 struct clock_event_device *evt = &per_cpu(lapic_events, cpu); 810 811 /* 812 * Normally we should not be here till LAPIC has been initialized but 813 * in some cases like kdump, its possible that there is a pending LAPIC 814 * timer interrupt from previous kernel's context and is delivered in 815 * new kernel the moment interrupts are enabled. 816 * 817 * Interrupts are enabled early and LAPIC is setup much later, hence 818 * its possible that when we get here evt->event_handler is NULL. 819 * Check for event_handler being NULL and discard the interrupt as 820 * spurious. 821 */ 822 if (!evt->event_handler) { 823 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); 824 /* Switch it off */ 825 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); 826 return; 827 } 828 829 /* 830 * the NMI deadlock-detector uses this. 831 */ 832 inc_irq_stat(apic_timer_irqs); 833 834 evt->event_handler(evt); 835 } 836 837 /* 838 * Local APIC timer interrupt. This is the most natural way for doing 839 * local interrupts, but local timer interrupts can be emulated by 840 * broadcast interrupts too. [in case the hw doesn't support APIC timers] 841 * 842 * [ if a single-CPU system runs an SMP kernel then we call the local 843 * interrupt as well. Thus we cannot inline the local irq ... ] 844 */ 845 void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 846 { 847 struct pt_regs *old_regs = set_irq_regs(regs); 848 849 /* 850 * NOTE! We'd better ACK the irq immediately, 851 * because timer handling can be slow. 852 */ 853 ack_APIC_irq(); 854 /* 855 * update_process_times() expects us to have done irq_enter(). 856 * Besides, if we don't timer interrupts ignore the global 857 * interrupt lock, which is the WrongThing (tm) to do. 858 */ 859 exit_idle(); 860 irq_enter(); 861 local_apic_timer_interrupt(); 862 irq_exit(); 863 864 set_irq_regs(old_regs); 865 } 866 867 int setup_profiling_timer(unsigned int multiplier) 868 { 869 return -EINVAL; 870 } 871 872 /* 873 * Local APIC start and shutdown 874 */ 875 876 /** 877 * clear_local_APIC - shutdown the local APIC 878 * 879 * This is called, when a CPU is disabled and before rebooting, so the state of 880 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 881 * leftovers during boot. 882 */ 883 void clear_local_APIC(void) 884 { 885 int maxlvt; 886 u32 v; 887 888 /* APIC hasn't been mapped yet */ 889 if (!x2apic_mode && !apic_phys) 890 return; 891 892 maxlvt = lapic_get_maxlvt(); 893 /* 894 * Masking an LVT entry can trigger a local APIC error 895 * if the vector is zero. Mask LVTERR first to prevent this. 896 */ 897 if (maxlvt >= 3) { 898 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 899 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 900 } 901 /* 902 * Careful: we have to set masks only first to deassert 903 * any level-triggered sources. 904 */ 905 v = apic_read(APIC_LVTT); 906 apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 907 v = apic_read(APIC_LVT0); 908 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 909 v = apic_read(APIC_LVT1); 910 apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 911 if (maxlvt >= 4) { 912 v = apic_read(APIC_LVTPC); 913 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 914 } 915 916 /* lets not touch this if we didn't frob it */ 917 #ifdef CONFIG_X86_THERMAL_VECTOR 918 if (maxlvt >= 5) { 919 v = apic_read(APIC_LVTTHMR); 920 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 921 } 922 #endif 923 #ifdef CONFIG_X86_MCE_INTEL 924 if (maxlvt >= 6) { 925 v = apic_read(APIC_LVTCMCI); 926 if (!(v & APIC_LVT_MASKED)) 927 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 928 } 929 #endif 930 931 /* 932 * Clean APIC state for other OSs: 933 */ 934 apic_write(APIC_LVTT, APIC_LVT_MASKED); 935 apic_write(APIC_LVT0, APIC_LVT_MASKED); 936 apic_write(APIC_LVT1, APIC_LVT_MASKED); 937 if (maxlvt >= 3) 938 apic_write(APIC_LVTERR, APIC_LVT_MASKED); 939 if (maxlvt >= 4) 940 apic_write(APIC_LVTPC, APIC_LVT_MASKED); 941 942 /* Integrated APIC (!82489DX) ? */ 943 if (lapic_is_integrated()) { 944 if (maxlvt > 3) 945 /* Clear ESR due to Pentium errata 3AP and 11AP */ 946 apic_write(APIC_ESR, 0); 947 apic_read(APIC_ESR); 948 } 949 } 950 951 /** 952 * disable_local_APIC - clear and disable the local APIC 953 */ 954 void disable_local_APIC(void) 955 { 956 unsigned int value; 957 958 /* APIC hasn't been mapped yet */ 959 if (!x2apic_mode && !apic_phys) 960 return; 961 962 clear_local_APIC(); 963 964 /* 965 * Disable APIC (implies clearing of registers 966 * for 82489DX!). 967 */ 968 value = apic_read(APIC_SPIV); 969 value &= ~APIC_SPIV_APIC_ENABLED; 970 apic_write(APIC_SPIV, value); 971 972 #ifdef CONFIG_X86_32 973 /* 974 * When LAPIC was disabled by the BIOS and enabled by the kernel, 975 * restore the disabled state. 976 */ 977 if (enabled_via_apicbase) { 978 unsigned int l, h; 979 980 rdmsr(MSR_IA32_APICBASE, l, h); 981 l &= ~MSR_IA32_APICBASE_ENABLE; 982 wrmsr(MSR_IA32_APICBASE, l, h); 983 } 984 #endif 985 } 986 987 /* 988 * If Linux enabled the LAPIC against the BIOS default disable it down before 989 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 990 * not power-off. Additionally clear all LVT entries before disable_local_APIC 991 * for the case where Linux didn't enable the LAPIC. 992 */ 993 void lapic_shutdown(void) 994 { 995 unsigned long flags; 996 997 if (!cpu_has_apic && !apic_from_smp_config()) 998 return; 999 1000 local_irq_save(flags); 1001 1002 #ifdef CONFIG_X86_32 1003 if (!enabled_via_apicbase) 1004 clear_local_APIC(); 1005 else 1006 #endif 1007 disable_local_APIC(); 1008 1009 1010 local_irq_restore(flags); 1011 } 1012 1013 /* 1014 * This is to verify that we're looking at a real local APIC. 1015 * Check these against your board if the CPUs aren't getting 1016 * started for no apparent reason. 1017 */ 1018 int __init verify_local_APIC(void) 1019 { 1020 unsigned int reg0, reg1; 1021 1022 /* 1023 * The version register is read-only in a real APIC. 1024 */ 1025 reg0 = apic_read(APIC_LVR); 1026 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); 1027 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); 1028 reg1 = apic_read(APIC_LVR); 1029 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); 1030 1031 /* 1032 * The two version reads above should print the same 1033 * numbers. If the second one is different, then we 1034 * poke at a non-APIC. 1035 */ 1036 if (reg1 != reg0) 1037 return 0; 1038 1039 /* 1040 * Check if the version looks reasonably. 1041 */ 1042 reg1 = GET_APIC_VERSION(reg0); 1043 if (reg1 == 0x00 || reg1 == 0xff) 1044 return 0; 1045 reg1 = lapic_get_maxlvt(); 1046 if (reg1 < 0x02 || reg1 == 0xff) 1047 return 0; 1048 1049 /* 1050 * The ID register is read/write in a real APIC. 1051 */ 1052 reg0 = apic_read(APIC_ID); 1053 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); 1054 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask); 1055 reg1 = apic_read(APIC_ID); 1056 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); 1057 apic_write(APIC_ID, reg0); 1058 if (reg1 != (reg0 ^ apic->apic_id_mask)) 1059 return 0; 1060 1061 /* 1062 * The next two are just to see if we have sane values. 1063 * They're only really relevant if we're in Virtual Wire 1064 * compatibility mode, but most boxes are anymore. 1065 */ 1066 reg0 = apic_read(APIC_LVT0); 1067 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); 1068 reg1 = apic_read(APIC_LVT1); 1069 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); 1070 1071 return 1; 1072 } 1073 1074 /** 1075 * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1076 */ 1077 void __init sync_Arb_IDs(void) 1078 { 1079 /* 1080 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1081 * needed on AMD. 1082 */ 1083 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1084 return; 1085 1086 /* 1087 * Wait for idle. 1088 */ 1089 apic_wait_icr_idle(); 1090 1091 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1092 apic_write(APIC_ICR, APIC_DEST_ALLINC | 1093 APIC_INT_LEVELTRIG | APIC_DM_INIT); 1094 } 1095 1096 /* 1097 * An initial setup of the virtual wire mode. 1098 */ 1099 void __init init_bsp_APIC(void) 1100 { 1101 unsigned int value; 1102 1103 /* 1104 * Don't do the setup now if we have a SMP BIOS as the 1105 * through-I/O-APIC virtual wire mode might be active. 1106 */ 1107 if (smp_found_config || !cpu_has_apic) 1108 return; 1109 1110 /* 1111 * Do not trust the local APIC being empty at bootup. 1112 */ 1113 clear_local_APIC(); 1114 1115 /* 1116 * Enable APIC. 1117 */ 1118 value = apic_read(APIC_SPIV); 1119 value &= ~APIC_VECTOR_MASK; 1120 value |= APIC_SPIV_APIC_ENABLED; 1121 1122 #ifdef CONFIG_X86_32 1123 /* This bit is reserved on P4/Xeon and should be cleared */ 1124 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1125 (boot_cpu_data.x86 == 15)) 1126 value &= ~APIC_SPIV_FOCUS_DISABLED; 1127 else 1128 #endif 1129 value |= APIC_SPIV_FOCUS_DISABLED; 1130 value |= SPURIOUS_APIC_VECTOR; 1131 apic_write(APIC_SPIV, value); 1132 1133 /* 1134 * Set up the virtual wire mode. 1135 */ 1136 apic_write(APIC_LVT0, APIC_DM_EXTINT); 1137 value = APIC_DM_NMI; 1138 if (!lapic_is_integrated()) /* 82489DX */ 1139 value |= APIC_LVT_LEVEL_TRIGGER; 1140 apic_write(APIC_LVT1, value); 1141 } 1142 1143 static void __cpuinit lapic_setup_esr(void) 1144 { 1145 unsigned int oldvalue, value, maxlvt; 1146 1147 if (!lapic_is_integrated()) { 1148 pr_info("No ESR for 82489DX.\n"); 1149 return; 1150 } 1151 1152 if (apic->disable_esr) { 1153 /* 1154 * Something untraceable is creating bad interrupts on 1155 * secondary quads ... for the moment, just leave the 1156 * ESR disabled - we can't do anything useful with the 1157 * errors anyway - mbligh 1158 */ 1159 pr_info("Leaving ESR disabled.\n"); 1160 return; 1161 } 1162 1163 maxlvt = lapic_get_maxlvt(); 1164 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1165 apic_write(APIC_ESR, 0); 1166 oldvalue = apic_read(APIC_ESR); 1167 1168 /* enables sending errors */ 1169 value = ERROR_APIC_VECTOR; 1170 apic_write(APIC_LVTERR, value); 1171 1172 /* 1173 * spec says clear errors after enabling vector. 1174 */ 1175 if (maxlvt > 3) 1176 apic_write(APIC_ESR, 0); 1177 value = apic_read(APIC_ESR); 1178 if (value != oldvalue) 1179 apic_printk(APIC_VERBOSE, "ESR value before enabling " 1180 "vector: 0x%08x after: 0x%08x\n", 1181 oldvalue, value); 1182 } 1183 1184 /** 1185 * setup_local_APIC - setup the local APIC 1186 * 1187 * Used to setup local APIC while initializing BSP or bringin up APs. 1188 * Always called with preemption disabled. 1189 */ 1190 void __cpuinit setup_local_APIC(void) 1191 { 1192 int cpu = smp_processor_id(); 1193 unsigned int value, queued; 1194 int i, j, acked = 0; 1195 unsigned long long tsc = 0, ntsc; 1196 long long max_loops = cpu_khz; 1197 1198 if (cpu_has_tsc) 1199 rdtscll(tsc); 1200 1201 if (disable_apic) { 1202 disable_ioapic_support(); 1203 return; 1204 } 1205 1206 #ifdef CONFIG_X86_32 1207 /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1208 if (lapic_is_integrated() && apic->disable_esr) { 1209 apic_write(APIC_ESR, 0); 1210 apic_write(APIC_ESR, 0); 1211 apic_write(APIC_ESR, 0); 1212 apic_write(APIC_ESR, 0); 1213 } 1214 #endif 1215 perf_events_lapic_init(); 1216 1217 /* 1218 * Double-check whether this APIC is really registered. 1219 * This is meaningless in clustered apic mode, so we skip it. 1220 */ 1221 BUG_ON(!apic->apic_id_registered()); 1222 1223 /* 1224 * Intel recommends to set DFR, LDR and TPR before enabling 1225 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1226 * document number 292116). So here it goes... 1227 */ 1228 apic->init_apic_ldr(); 1229 1230 #ifdef CONFIG_X86_32 1231 /* 1232 * APIC LDR is initialized. If logical_apicid mapping was 1233 * initialized during get_smp_config(), make sure it matches the 1234 * actual value. 1235 */ 1236 i = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 1237 WARN_ON(i != BAD_APICID && i != logical_smp_processor_id()); 1238 /* always use the value from LDR */ 1239 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 1240 logical_smp_processor_id(); 1241 1242 /* 1243 * Some NUMA implementations (NUMAQ) don't initialize apicid to 1244 * node mapping during NUMA init. Now that logical apicid is 1245 * guaranteed to be known, give it another chance. This is already 1246 * a bit too late - percpu allocation has already happened without 1247 * proper NUMA affinity. 1248 */ 1249 if (apic->x86_32_numa_cpu_node) 1250 set_apicid_to_node(early_per_cpu(x86_cpu_to_apicid, cpu), 1251 apic->x86_32_numa_cpu_node(cpu)); 1252 #endif 1253 1254 /* 1255 * Set Task Priority to 'accept all'. We never change this 1256 * later on. 1257 */ 1258 value = apic_read(APIC_TASKPRI); 1259 value &= ~APIC_TPRI_MASK; 1260 apic_write(APIC_TASKPRI, value); 1261 1262 /* 1263 * After a crash, we no longer service the interrupts and a pending 1264 * interrupt from previous kernel might still have ISR bit set. 1265 * 1266 * Most probably by now CPU has serviced that pending interrupt and 1267 * it might not have done the ack_APIC_irq() because it thought, 1268 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1269 * does not clear the ISR bit and cpu thinks it has already serivced 1270 * the interrupt. Hence a vector might get locked. It was noticed 1271 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1272 */ 1273 do { 1274 queued = 0; 1275 for (i = APIC_ISR_NR - 1; i >= 0; i--) 1276 queued |= apic_read(APIC_IRR + i*0x10); 1277 1278 for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1279 value = apic_read(APIC_ISR + i*0x10); 1280 for (j = 31; j >= 0; j--) { 1281 if (value & (1<<j)) { 1282 ack_APIC_irq(); 1283 acked++; 1284 } 1285 } 1286 } 1287 if (acked > 256) { 1288 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", 1289 acked); 1290 break; 1291 } 1292 if (cpu_has_tsc) { 1293 rdtscll(ntsc); 1294 max_loops = (cpu_khz << 10) - (ntsc - tsc); 1295 } else 1296 max_loops--; 1297 } while (queued && max_loops > 0); 1298 WARN_ON(max_loops <= 0); 1299 1300 /* 1301 * Now that we are all set up, enable the APIC 1302 */ 1303 value = apic_read(APIC_SPIV); 1304 value &= ~APIC_VECTOR_MASK; 1305 /* 1306 * Enable APIC 1307 */ 1308 value |= APIC_SPIV_APIC_ENABLED; 1309 1310 #ifdef CONFIG_X86_32 1311 /* 1312 * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1313 * certain networking cards. If high frequency interrupts are 1314 * happening on a particular IOAPIC pin, plus the IOAPIC routing 1315 * entry is masked/unmasked at a high rate as well then sooner or 1316 * later IOAPIC line gets 'stuck', no more interrupts are received 1317 * from the device. If focus CPU is disabled then the hang goes 1318 * away, oh well :-( 1319 * 1320 * [ This bug can be reproduced easily with a level-triggered 1321 * PCI Ne2000 networking cards and PII/PIII processors, dual 1322 * BX chipset. ] 1323 */ 1324 /* 1325 * Actually disabling the focus CPU check just makes the hang less 1326 * frequent as it makes the interrupt distributon model be more 1327 * like LRU than MRU (the short-term load is more even across CPUs). 1328 * See also the comment in end_level_ioapic_irq(). --macro 1329 */ 1330 1331 /* 1332 * - enable focus processor (bit==0) 1333 * - 64bit mode always use processor focus 1334 * so no need to set it 1335 */ 1336 value &= ~APIC_SPIV_FOCUS_DISABLED; 1337 #endif 1338 1339 /* 1340 * Set spurious IRQ vector 1341 */ 1342 value |= SPURIOUS_APIC_VECTOR; 1343 apic_write(APIC_SPIV, value); 1344 1345 /* 1346 * Set up LVT0, LVT1: 1347 * 1348 * set up through-local-APIC on the BP's LINT0. This is not 1349 * strictly necessary in pure symmetric-IO mode, but sometimes 1350 * we delegate interrupts to the 8259A. 1351 */ 1352 /* 1353 * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1354 */ 1355 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1356 if (!cpu && (pic_mode || !value)) { 1357 value = APIC_DM_EXTINT; 1358 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1359 } else { 1360 value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1361 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1362 } 1363 apic_write(APIC_LVT0, value); 1364 1365 /* 1366 * only the BP should see the LINT1 NMI signal, obviously. 1367 */ 1368 if (!cpu) 1369 value = APIC_DM_NMI; 1370 else 1371 value = APIC_DM_NMI | APIC_LVT_MASKED; 1372 if (!lapic_is_integrated()) /* 82489DX */ 1373 value |= APIC_LVT_LEVEL_TRIGGER; 1374 apic_write(APIC_LVT1, value); 1375 1376 #ifdef CONFIG_X86_MCE_INTEL 1377 /* Recheck CMCI information after local APIC is up on CPU #0 */ 1378 if (!cpu) 1379 cmci_recheck(); 1380 #endif 1381 } 1382 1383 void __cpuinit end_local_APIC_setup(void) 1384 { 1385 lapic_setup_esr(); 1386 1387 #ifdef CONFIG_X86_32 1388 { 1389 unsigned int value; 1390 /* Disable the local apic timer */ 1391 value = apic_read(APIC_LVTT); 1392 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1393 apic_write(APIC_LVTT, value); 1394 } 1395 #endif 1396 1397 apic_pm_activate(); 1398 } 1399 1400 void __init bsp_end_local_APIC_setup(void) 1401 { 1402 end_local_APIC_setup(); 1403 1404 /* 1405 * Now that local APIC setup is completed for BP, configure the fault 1406 * handling for interrupt remapping. 1407 */ 1408 if (intr_remapping_enabled) 1409 enable_drhd_fault_handling(); 1410 1411 } 1412 1413 #ifdef CONFIG_X86_X2APIC 1414 void check_x2apic(void) 1415 { 1416 if (x2apic_enabled()) { 1417 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); 1418 x2apic_preenabled = x2apic_mode = 1; 1419 } 1420 } 1421 1422 void enable_x2apic(void) 1423 { 1424 int msr, msr2; 1425 1426 if (!x2apic_mode) 1427 return; 1428 1429 rdmsr(MSR_IA32_APICBASE, msr, msr2); 1430 if (!(msr & X2APIC_ENABLE)) { 1431 printk_once(KERN_INFO "Enabling x2apic\n"); 1432 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); 1433 } 1434 } 1435 #endif /* CONFIG_X86_X2APIC */ 1436 1437 int __init enable_IR(void) 1438 { 1439 #ifdef CONFIG_INTR_REMAP 1440 if (!intr_remapping_supported()) { 1441 pr_debug("intr-remapping not supported\n"); 1442 return 0; 1443 } 1444 1445 if (!x2apic_preenabled && skip_ioapic_setup) { 1446 pr_info("Skipped enabling intr-remap because of skipping " 1447 "io-apic setup\n"); 1448 return 0; 1449 } 1450 1451 if (enable_intr_remapping(x2apic_supported())) 1452 return 0; 1453 1454 pr_info("Enabled Interrupt-remapping\n"); 1455 1456 return 1; 1457 1458 #endif 1459 return 0; 1460 } 1461 1462 void __init enable_IR_x2apic(void) 1463 { 1464 unsigned long flags; 1465 int ret, x2apic_enabled = 0; 1466 int dmar_table_init_ret; 1467 1468 dmar_table_init_ret = dmar_table_init(); 1469 if (dmar_table_init_ret && !x2apic_supported()) 1470 return; 1471 1472 ret = save_ioapic_entries(); 1473 if (ret) { 1474 pr_info("Saving IO-APIC state failed: %d\n", ret); 1475 goto out; 1476 } 1477 1478 local_irq_save(flags); 1479 legacy_pic->mask_all(); 1480 mask_ioapic_entries(); 1481 1482 if (dmar_table_init_ret) 1483 ret = 0; 1484 else 1485 ret = enable_IR(); 1486 1487 if (!ret) { 1488 /* IR is required if there is APIC ID > 255 even when running 1489 * under KVM 1490 */ 1491 if (max_physical_apicid > 255 || 1492 !hypervisor_x2apic_available()) 1493 goto nox2apic; 1494 /* 1495 * without IR all CPUs can be addressed by IOAPIC/MSI 1496 * only in physical mode 1497 */ 1498 x2apic_force_phys(); 1499 } 1500 1501 x2apic_enabled = 1; 1502 1503 if (x2apic_supported() && !x2apic_mode) { 1504 x2apic_mode = 1; 1505 enable_x2apic(); 1506 pr_info("Enabled x2apic\n"); 1507 } 1508 1509 nox2apic: 1510 if (!ret) /* IR enabling failed */ 1511 restore_ioapic_entries(); 1512 legacy_pic->restore_mask(); 1513 local_irq_restore(flags); 1514 1515 out: 1516 if (x2apic_enabled) 1517 return; 1518 1519 if (x2apic_preenabled) 1520 panic("x2apic: enabled by BIOS but kernel init failed."); 1521 else if (cpu_has_x2apic) 1522 pr_info("Not enabling x2apic, Intr-remapping init failed.\n"); 1523 } 1524 1525 #ifdef CONFIG_X86_64 1526 /* 1527 * Detect and enable local APICs on non-SMP boards. 1528 * Original code written by Keir Fraser. 1529 * On AMD64 we trust the BIOS - if it says no APIC it is likely 1530 * not correctly set up (usually the APIC timer won't work etc.) 1531 */ 1532 static int __init detect_init_APIC(void) 1533 { 1534 if (!cpu_has_apic) { 1535 pr_info("No local APIC present\n"); 1536 return -1; 1537 } 1538 1539 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1540 return 0; 1541 } 1542 #else 1543 1544 static int __init apic_verify(void) 1545 { 1546 u32 features, h, l; 1547 1548 /* 1549 * The APIC feature bit should now be enabled 1550 * in `cpuid' 1551 */ 1552 features = cpuid_edx(1); 1553 if (!(features & (1 << X86_FEATURE_APIC))) { 1554 pr_warning("Could not enable APIC!\n"); 1555 return -1; 1556 } 1557 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1558 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1559 1560 /* The BIOS may have set up the APIC at some other address */ 1561 rdmsr(MSR_IA32_APICBASE, l, h); 1562 if (l & MSR_IA32_APICBASE_ENABLE) 1563 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1564 1565 pr_info("Found and enabled local APIC!\n"); 1566 return 0; 1567 } 1568 1569 int __init apic_force_enable(unsigned long addr) 1570 { 1571 u32 h, l; 1572 1573 if (disable_apic) 1574 return -1; 1575 1576 /* 1577 * Some BIOSes disable the local APIC in the APIC_BASE 1578 * MSR. This can only be done in software for Intel P6 or later 1579 * and AMD K7 (Model > 1) or later. 1580 */ 1581 rdmsr(MSR_IA32_APICBASE, l, h); 1582 if (!(l & MSR_IA32_APICBASE_ENABLE)) { 1583 pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 1584 l &= ~MSR_IA32_APICBASE_BASE; 1585 l |= MSR_IA32_APICBASE_ENABLE | addr; 1586 wrmsr(MSR_IA32_APICBASE, l, h); 1587 enabled_via_apicbase = 1; 1588 } 1589 return apic_verify(); 1590 } 1591 1592 /* 1593 * Detect and initialize APIC 1594 */ 1595 static int __init detect_init_APIC(void) 1596 { 1597 /* Disabled by kernel option? */ 1598 if (disable_apic) 1599 return -1; 1600 1601 switch (boot_cpu_data.x86_vendor) { 1602 case X86_VENDOR_AMD: 1603 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1604 (boot_cpu_data.x86 >= 15)) 1605 break; 1606 goto no_apic; 1607 case X86_VENDOR_INTEL: 1608 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1609 (boot_cpu_data.x86 == 5 && cpu_has_apic)) 1610 break; 1611 goto no_apic; 1612 default: 1613 goto no_apic; 1614 } 1615 1616 if (!cpu_has_apic) { 1617 /* 1618 * Over-ride BIOS and try to enable the local APIC only if 1619 * "lapic" specified. 1620 */ 1621 if (!force_enable_local_apic) { 1622 pr_info("Local APIC disabled by BIOS -- " 1623 "you can enable it with \"lapic\"\n"); 1624 return -1; 1625 } 1626 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 1627 return -1; 1628 } else { 1629 if (apic_verify()) 1630 return -1; 1631 } 1632 1633 apic_pm_activate(); 1634 1635 return 0; 1636 1637 no_apic: 1638 pr_info("No local APIC present or hardware disabled\n"); 1639 return -1; 1640 } 1641 #endif 1642 1643 /** 1644 * init_apic_mappings - initialize APIC mappings 1645 */ 1646 void __init init_apic_mappings(void) 1647 { 1648 unsigned int new_apicid; 1649 1650 if (x2apic_mode) { 1651 boot_cpu_physical_apicid = read_apic_id(); 1652 return; 1653 } 1654 1655 /* If no local APIC can be found return early */ 1656 if (!smp_found_config && detect_init_APIC()) { 1657 /* lets NOP'ify apic operations */ 1658 pr_info("APIC: disable apic facility\n"); 1659 apic_disable(); 1660 } else { 1661 apic_phys = mp_lapic_addr; 1662 1663 /* 1664 * acpi lapic path already maps that address in 1665 * acpi_register_lapic_address() 1666 */ 1667 if (!acpi_lapic && !smp_found_config) 1668 register_lapic_address(apic_phys); 1669 } 1670 1671 /* 1672 * Fetch the APIC ID of the BSP in case we have a 1673 * default configuration (or the MP table is broken). 1674 */ 1675 new_apicid = read_apic_id(); 1676 if (boot_cpu_physical_apicid != new_apicid) { 1677 boot_cpu_physical_apicid = new_apicid; 1678 /* 1679 * yeah -- we lie about apic_version 1680 * in case if apic was disabled via boot option 1681 * but it's not a problem for SMP compiled kernel 1682 * since smp_sanity_check is prepared for such a case 1683 * and disable smp mode 1684 */ 1685 apic_version[new_apicid] = 1686 GET_APIC_VERSION(apic_read(APIC_LVR)); 1687 } 1688 } 1689 1690 void __init register_lapic_address(unsigned long address) 1691 { 1692 mp_lapic_addr = address; 1693 1694 if (!x2apic_mode) { 1695 set_fixmap_nocache(FIX_APIC_BASE, address); 1696 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 1697 APIC_BASE, mp_lapic_addr); 1698 } 1699 if (boot_cpu_physical_apicid == -1U) { 1700 boot_cpu_physical_apicid = read_apic_id(); 1701 apic_version[boot_cpu_physical_apicid] = 1702 GET_APIC_VERSION(apic_read(APIC_LVR)); 1703 } 1704 } 1705 1706 /* 1707 * This initializes the IO-APIC and APIC hardware if this is 1708 * a UP kernel. 1709 */ 1710 int apic_version[MAX_LOCAL_APIC]; 1711 1712 int __init APIC_init_uniprocessor(void) 1713 { 1714 if (disable_apic) { 1715 pr_info("Apic disabled\n"); 1716 return -1; 1717 } 1718 #ifdef CONFIG_X86_64 1719 if (!cpu_has_apic) { 1720 disable_apic = 1; 1721 pr_info("Apic disabled by BIOS\n"); 1722 return -1; 1723 } 1724 #else 1725 if (!smp_found_config && !cpu_has_apic) 1726 return -1; 1727 1728 /* 1729 * Complain if the BIOS pretends there is one. 1730 */ 1731 if (!cpu_has_apic && 1732 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 1733 pr_err("BIOS bug, local APIC 0x%x not detected!...\n", 1734 boot_cpu_physical_apicid); 1735 return -1; 1736 } 1737 #endif 1738 1739 default_setup_apic_routing(); 1740 1741 verify_local_APIC(); 1742 connect_bsp_APIC(); 1743 1744 #ifdef CONFIG_X86_64 1745 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); 1746 #else 1747 /* 1748 * Hack: In case of kdump, after a crash, kernel might be booting 1749 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 1750 * might be zero if read from MP tables. Get it from LAPIC. 1751 */ 1752 # ifdef CONFIG_CRASH_DUMP 1753 boot_cpu_physical_apicid = read_apic_id(); 1754 # endif 1755 #endif 1756 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1757 setup_local_APIC(); 1758 1759 #ifdef CONFIG_X86_IO_APIC 1760 /* 1761 * Now enable IO-APICs, actually call clear_IO_APIC 1762 * We need clear_IO_APIC before enabling error vector 1763 */ 1764 if (!skip_ioapic_setup && nr_ioapics) 1765 enable_IO_APIC(); 1766 #endif 1767 1768 bsp_end_local_APIC_setup(); 1769 1770 #ifdef CONFIG_X86_IO_APIC 1771 if (smp_found_config && !skip_ioapic_setup && nr_ioapics) 1772 setup_IO_APIC(); 1773 else { 1774 nr_ioapics = 0; 1775 } 1776 #endif 1777 1778 x86_init.timers.setup_percpu_clockev(); 1779 return 0; 1780 } 1781 1782 /* 1783 * Local APIC interrupts 1784 */ 1785 1786 /* 1787 * This interrupt should _never_ happen with our APIC/SMP architecture 1788 */ 1789 void smp_spurious_interrupt(struct pt_regs *regs) 1790 { 1791 u32 v; 1792 1793 exit_idle(); 1794 irq_enter(); 1795 /* 1796 * Check if this really is a spurious interrupt and ACK it 1797 * if it is a vectored one. Just in case... 1798 * Spurious interrupts should not be ACKed. 1799 */ 1800 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); 1801 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) 1802 ack_APIC_irq(); 1803 1804 inc_irq_stat(irq_spurious_count); 1805 1806 /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 1807 pr_info("spurious APIC interrupt on CPU#%d, " 1808 "should never happen.\n", smp_processor_id()); 1809 irq_exit(); 1810 } 1811 1812 /* 1813 * This interrupt should never happen with our APIC/SMP architecture 1814 */ 1815 void smp_error_interrupt(struct pt_regs *regs) 1816 { 1817 u32 v0, v1; 1818 u32 i = 0; 1819 static const char * const error_interrupt_reason[] = { 1820 "Send CS error", /* APIC Error Bit 0 */ 1821 "Receive CS error", /* APIC Error Bit 1 */ 1822 "Send accept error", /* APIC Error Bit 2 */ 1823 "Receive accept error", /* APIC Error Bit 3 */ 1824 "Redirectable IPI", /* APIC Error Bit 4 */ 1825 "Send illegal vector", /* APIC Error Bit 5 */ 1826 "Received illegal vector", /* APIC Error Bit 6 */ 1827 "Illegal register address", /* APIC Error Bit 7 */ 1828 }; 1829 1830 exit_idle(); 1831 irq_enter(); 1832 /* First tickle the hardware, only then report what went on. -- REW */ 1833 v0 = apic_read(APIC_ESR); 1834 apic_write(APIC_ESR, 0); 1835 v1 = apic_read(APIC_ESR); 1836 ack_APIC_irq(); 1837 atomic_inc(&irq_err_count); 1838 1839 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x(%02x)", 1840 smp_processor_id(), v0 , v1); 1841 1842 v1 = v1 & 0xff; 1843 while (v1) { 1844 if (v1 & 0x1) 1845 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 1846 i++; 1847 v1 >>= 1; 1848 }; 1849 1850 apic_printk(APIC_DEBUG, KERN_CONT "\n"); 1851 1852 irq_exit(); 1853 } 1854 1855 /** 1856 * connect_bsp_APIC - attach the APIC to the interrupt system 1857 */ 1858 void __init connect_bsp_APIC(void) 1859 { 1860 #ifdef CONFIG_X86_32 1861 if (pic_mode) { 1862 /* 1863 * Do not trust the local APIC being empty at bootup. 1864 */ 1865 clear_local_APIC(); 1866 /* 1867 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 1868 * local APIC to INT and NMI lines. 1869 */ 1870 apic_printk(APIC_VERBOSE, "leaving PIC mode, " 1871 "enabling APIC mode.\n"); 1872 imcr_pic_to_apic(); 1873 } 1874 #endif 1875 if (apic->enable_apic_mode) 1876 apic->enable_apic_mode(); 1877 } 1878 1879 /** 1880 * disconnect_bsp_APIC - detach the APIC from the interrupt system 1881 * @virt_wire_setup: indicates, whether virtual wire mode is selected 1882 * 1883 * Virtual wire mode is necessary to deliver legacy interrupts even when the 1884 * APIC is disabled. 1885 */ 1886 void disconnect_bsp_APIC(int virt_wire_setup) 1887 { 1888 unsigned int value; 1889 1890 #ifdef CONFIG_X86_32 1891 if (pic_mode) { 1892 /* 1893 * Put the board back into PIC mode (has an effect only on 1894 * certain older boards). Note that APIC interrupts, including 1895 * IPIs, won't work beyond this point! The only exception are 1896 * INIT IPIs. 1897 */ 1898 apic_printk(APIC_VERBOSE, "disabling APIC mode, " 1899 "entering PIC mode.\n"); 1900 imcr_apic_to_pic(); 1901 return; 1902 } 1903 #endif 1904 1905 /* Go back to Virtual Wire compatibility mode */ 1906 1907 /* For the spurious interrupt use vector F, and enable it */ 1908 value = apic_read(APIC_SPIV); 1909 value &= ~APIC_VECTOR_MASK; 1910 value |= APIC_SPIV_APIC_ENABLED; 1911 value |= 0xf; 1912 apic_write(APIC_SPIV, value); 1913 1914 if (!virt_wire_setup) { 1915 /* 1916 * For LVT0 make it edge triggered, active high, 1917 * external and enabled 1918 */ 1919 value = apic_read(APIC_LVT0); 1920 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1921 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1922 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1923 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1924 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 1925 apic_write(APIC_LVT0, value); 1926 } else { 1927 /* Disable LVT0 */ 1928 apic_write(APIC_LVT0, APIC_LVT_MASKED); 1929 } 1930 1931 /* 1932 * For LVT1 make it edge triggered, active high, 1933 * nmi and enabled 1934 */ 1935 value = apic_read(APIC_LVT1); 1936 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1937 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1938 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1939 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1940 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 1941 apic_write(APIC_LVT1, value); 1942 } 1943 1944 void __cpuinit generic_processor_info(int apicid, int version) 1945 { 1946 int cpu; 1947 1948 if (num_processors >= nr_cpu_ids) { 1949 int max = nr_cpu_ids; 1950 int thiscpu = max + disabled_cpus; 1951 1952 pr_warning( 1953 "ACPI: NR_CPUS/possible_cpus limit of %i reached." 1954 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 1955 1956 disabled_cpus++; 1957 return; 1958 } 1959 1960 num_processors++; 1961 if (apicid == boot_cpu_physical_apicid) { 1962 /* 1963 * x86_bios_cpu_apicid is required to have processors listed 1964 * in same order as logical cpu numbers. Hence the first 1965 * entry is BSP, and so on. 1966 * boot_cpu_init() already hold bit 0 in cpu_present_mask 1967 * for BSP. 1968 */ 1969 cpu = 0; 1970 } else 1971 cpu = cpumask_next_zero(-1, cpu_present_mask); 1972 1973 /* 1974 * Validate version 1975 */ 1976 if (version == 0x0) { 1977 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", 1978 cpu, apicid); 1979 version = 0x10; 1980 } 1981 apic_version[apicid] = version; 1982 1983 if (version != apic_version[boot_cpu_physical_apicid]) { 1984 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", 1985 apic_version[boot_cpu_physical_apicid], cpu, version); 1986 } 1987 1988 physid_set(apicid, phys_cpu_present_map); 1989 if (apicid > max_physical_apicid) 1990 max_physical_apicid = apicid; 1991 1992 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 1993 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 1994 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 1995 #endif 1996 #ifdef CONFIG_X86_32 1997 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 1998 apic->x86_32_early_logical_apicid(cpu); 1999 #endif 2000 set_cpu_possible(cpu, true); 2001 set_cpu_present(cpu, true); 2002 } 2003 2004 int hard_smp_processor_id(void) 2005 { 2006 return read_apic_id(); 2007 } 2008 2009 void default_init_apic_ldr(void) 2010 { 2011 unsigned long val; 2012 2013 apic_write(APIC_DFR, APIC_DFR_VALUE); 2014 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; 2015 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); 2016 apic_write(APIC_LDR, val); 2017 } 2018 2019 /* 2020 * Power management 2021 */ 2022 #ifdef CONFIG_PM 2023 2024 static struct { 2025 /* 2026 * 'active' is true if the local APIC was enabled by us and 2027 * not the BIOS; this signifies that we are also responsible 2028 * for disabling it before entering apm/acpi suspend 2029 */ 2030 int active; 2031 /* r/w apic fields */ 2032 unsigned int apic_id; 2033 unsigned int apic_taskpri; 2034 unsigned int apic_ldr; 2035 unsigned int apic_dfr; 2036 unsigned int apic_spiv; 2037 unsigned int apic_lvtt; 2038 unsigned int apic_lvtpc; 2039 unsigned int apic_lvt0; 2040 unsigned int apic_lvt1; 2041 unsigned int apic_lvterr; 2042 unsigned int apic_tmict; 2043 unsigned int apic_tdcr; 2044 unsigned int apic_thmr; 2045 } apic_pm_state; 2046 2047 static int lapic_suspend(void) 2048 { 2049 unsigned long flags; 2050 int maxlvt; 2051 2052 if (!apic_pm_state.active) 2053 return 0; 2054 2055 maxlvt = lapic_get_maxlvt(); 2056 2057 apic_pm_state.apic_id = apic_read(APIC_ID); 2058 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2059 apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2060 apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2061 apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2062 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2063 if (maxlvt >= 4) 2064 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2065 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2066 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2067 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2068 apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2069 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 2070 #ifdef CONFIG_X86_THERMAL_VECTOR 2071 if (maxlvt >= 5) 2072 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2073 #endif 2074 2075 local_irq_save(flags); 2076 disable_local_APIC(); 2077 2078 if (intr_remapping_enabled) 2079 disable_intr_remapping(); 2080 2081 local_irq_restore(flags); 2082 return 0; 2083 } 2084 2085 static void lapic_resume(void) 2086 { 2087 unsigned int l, h; 2088 unsigned long flags; 2089 int maxlvt; 2090 2091 if (!apic_pm_state.active) 2092 return; 2093 2094 local_irq_save(flags); 2095 if (intr_remapping_enabled) { 2096 /* 2097 * IO-APIC and PIC have their own resume routines. 2098 * We just mask them here to make sure the interrupt 2099 * subsystem is completely quiet while we enable x2apic 2100 * and interrupt-remapping. 2101 */ 2102 mask_ioapic_entries(); 2103 legacy_pic->mask_all(); 2104 } 2105 2106 if (x2apic_mode) 2107 enable_x2apic(); 2108 else { 2109 /* 2110 * Make sure the APICBASE points to the right address 2111 * 2112 * FIXME! This will be wrong if we ever support suspend on 2113 * SMP! We'll need to do this as part of the CPU restore! 2114 */ 2115 rdmsr(MSR_IA32_APICBASE, l, h); 2116 l &= ~MSR_IA32_APICBASE_BASE; 2117 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2118 wrmsr(MSR_IA32_APICBASE, l, h); 2119 } 2120 2121 maxlvt = lapic_get_maxlvt(); 2122 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2123 apic_write(APIC_ID, apic_pm_state.apic_id); 2124 apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2125 apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2126 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2127 apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2128 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2129 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2130 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) 2131 if (maxlvt >= 5) 2132 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2133 #endif 2134 if (maxlvt >= 4) 2135 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2136 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2137 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2138 apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2139 apic_write(APIC_ESR, 0); 2140 apic_read(APIC_ESR); 2141 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2142 apic_write(APIC_ESR, 0); 2143 apic_read(APIC_ESR); 2144 2145 if (intr_remapping_enabled) 2146 reenable_intr_remapping(x2apic_mode); 2147 2148 local_irq_restore(flags); 2149 } 2150 2151 /* 2152 * This device has no shutdown method - fully functioning local APICs 2153 * are needed on every CPU up until machine_halt/restart/poweroff. 2154 */ 2155 2156 static struct syscore_ops lapic_syscore_ops = { 2157 .resume = lapic_resume, 2158 .suspend = lapic_suspend, 2159 }; 2160 2161 static void __cpuinit apic_pm_activate(void) 2162 { 2163 apic_pm_state.active = 1; 2164 } 2165 2166 static int __init init_lapic_sysfs(void) 2167 { 2168 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2169 if (cpu_has_apic) 2170 register_syscore_ops(&lapic_syscore_ops); 2171 2172 return 0; 2173 } 2174 2175 /* local apic needs to resume before other devices access its registers. */ 2176 core_initcall(init_lapic_sysfs); 2177 2178 #else /* CONFIG_PM */ 2179 2180 static void apic_pm_activate(void) { } 2181 2182 #endif /* CONFIG_PM */ 2183 2184 #ifdef CONFIG_X86_64 2185 2186 static int __cpuinit apic_cluster_num(void) 2187 { 2188 int i, clusters, zeros; 2189 unsigned id; 2190 u16 *bios_cpu_apicid; 2191 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); 2192 2193 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); 2194 bitmap_zero(clustermap, NUM_APIC_CLUSTERS); 2195 2196 for (i = 0; i < nr_cpu_ids; i++) { 2197 /* are we being called early in kernel startup? */ 2198 if (bios_cpu_apicid) { 2199 id = bios_cpu_apicid[i]; 2200 } else if (i < nr_cpu_ids) { 2201 if (cpu_present(i)) 2202 id = per_cpu(x86_bios_cpu_apicid, i); 2203 else 2204 continue; 2205 } else 2206 break; 2207 2208 if (id != BAD_APICID) 2209 __set_bit(APIC_CLUSTERID(id), clustermap); 2210 } 2211 2212 /* Problem: Partially populated chassis may not have CPUs in some of 2213 * the APIC clusters they have been allocated. Only present CPUs have 2214 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. 2215 * Since clusters are allocated sequentially, count zeros only if 2216 * they are bounded by ones. 2217 */ 2218 clusters = 0; 2219 zeros = 0; 2220 for (i = 0; i < NUM_APIC_CLUSTERS; i++) { 2221 if (test_bit(i, clustermap)) { 2222 clusters += 1 + zeros; 2223 zeros = 0; 2224 } else 2225 ++zeros; 2226 } 2227 2228 return clusters; 2229 } 2230 2231 static int __cpuinitdata multi_checked; 2232 static int __cpuinitdata multi; 2233 2234 static int __cpuinit set_multi(const struct dmi_system_id *d) 2235 { 2236 if (multi) 2237 return 0; 2238 pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2239 multi = 1; 2240 return 0; 2241 } 2242 2243 static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = { 2244 { 2245 .callback = set_multi, 2246 .ident = "IBM System Summit2", 2247 .matches = { 2248 DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2249 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2250 }, 2251 }, 2252 {} 2253 }; 2254 2255 static void __cpuinit dmi_check_multi(void) 2256 { 2257 if (multi_checked) 2258 return; 2259 2260 dmi_check_system(multi_dmi_table); 2261 multi_checked = 1; 2262 } 2263 2264 /* 2265 * apic_is_clustered_box() -- Check if we can expect good TSC 2266 * 2267 * Thus far, the major user of this is IBM's Summit2 series: 2268 * Clustered boxes may have unsynced TSC problems if they are 2269 * multi-chassis. 2270 * Use DMI to check them 2271 */ 2272 __cpuinit int apic_is_clustered_box(void) 2273 { 2274 dmi_check_multi(); 2275 if (multi) 2276 return 1; 2277 2278 if (!is_vsmp_box()) 2279 return 0; 2280 2281 /* 2282 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are 2283 * not guaranteed to be synced between boards 2284 */ 2285 if (apic_cluster_num() > 1) 2286 return 1; 2287 2288 return 0; 2289 } 2290 #endif 2291 2292 /* 2293 * APIC command line parameters 2294 */ 2295 static int __init setup_disableapic(char *arg) 2296 { 2297 disable_apic = 1; 2298 setup_clear_cpu_cap(X86_FEATURE_APIC); 2299 return 0; 2300 } 2301 early_param("disableapic", setup_disableapic); 2302 2303 /* same as disableapic, for compatibility */ 2304 static int __init setup_nolapic(char *arg) 2305 { 2306 return setup_disableapic(arg); 2307 } 2308 early_param("nolapic", setup_nolapic); 2309 2310 static int __init parse_lapic_timer_c2_ok(char *arg) 2311 { 2312 local_apic_timer_c2_ok = 1; 2313 return 0; 2314 } 2315 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2316 2317 static int __init parse_disable_apic_timer(char *arg) 2318 { 2319 disable_apic_timer = 1; 2320 return 0; 2321 } 2322 early_param("noapictimer", parse_disable_apic_timer); 2323 2324 static int __init parse_nolapic_timer(char *arg) 2325 { 2326 disable_apic_timer = 1; 2327 return 0; 2328 } 2329 early_param("nolapic_timer", parse_nolapic_timer); 2330 2331 static int __init apic_set_verbosity(char *arg) 2332 { 2333 if (!arg) { 2334 #ifdef CONFIG_X86_64 2335 skip_ioapic_setup = 0; 2336 return 0; 2337 #endif 2338 return -EINVAL; 2339 } 2340 2341 if (strcmp("debug", arg) == 0) 2342 apic_verbosity = APIC_DEBUG; 2343 else if (strcmp("verbose", arg) == 0) 2344 apic_verbosity = APIC_VERBOSE; 2345 else { 2346 pr_warning("APIC Verbosity level %s not recognised" 2347 " use apic=verbose or apic=debug\n", arg); 2348 return -EINVAL; 2349 } 2350 2351 return 0; 2352 } 2353 early_param("apic", apic_set_verbosity); 2354 2355 static int __init lapic_insert_resource(void) 2356 { 2357 if (!apic_phys) 2358 return -1; 2359 2360 /* Put local APIC into the resource map. */ 2361 lapic_resource.start = apic_phys; 2362 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2363 insert_resource(&iomem_resource, &lapic_resource); 2364 2365 return 0; 2366 } 2367 2368 /* 2369 * need call insert after e820_reserve_resources() 2370 * that is using request_resource 2371 */ 2372 late_initcall(lapic_insert_resource); 2373