1 /* 2 * Local APIC handling, local APIC timers 3 * 4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5 * 6 * Fixes 7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8 * thanks to Eric Gilmore 9 * and Rolf G. Tews 10 * for testing these extensively. 11 * Maciej W. Rozycki : Various updates and fixes. 12 * Mikael Pettersson : Power Management for UP-APIC. 13 * Pavel Machek and 14 * Mikael Pettersson : PM converted to driver model. 15 */ 16 17 #include <linux/perf_event.h> 18 #include <linux/kernel_stat.h> 19 #include <linux/mc146818rtc.h> 20 #include <linux/acpi_pmtmr.h> 21 #include <linux/clockchips.h> 22 #include <linux/interrupt.h> 23 #include <linux/bootmem.h> 24 #include <linux/ftrace.h> 25 #include <linux/ioport.h> 26 #include <linux/module.h> 27 #include <linux/syscore_ops.h> 28 #include <linux/delay.h> 29 #include <linux/timex.h> 30 #include <linux/i8253.h> 31 #include <linux/dmar.h> 32 #include <linux/init.h> 33 #include <linux/cpu.h> 34 #include <linux/dmi.h> 35 #include <linux/smp.h> 36 #include <linux/mm.h> 37 38 #include <asm/trace/irq_vectors.h> 39 #include <asm/irq_remapping.h> 40 #include <asm/perf_event.h> 41 #include <asm/x86_init.h> 42 #include <asm/pgalloc.h> 43 #include <linux/atomic.h> 44 #include <asm/mpspec.h> 45 #include <asm/i8259.h> 46 #include <asm/proto.h> 47 #include <asm/apic.h> 48 #include <asm/io_apic.h> 49 #include <asm/desc.h> 50 #include <asm/hpet.h> 51 #include <asm/idle.h> 52 #include <asm/mtrr.h> 53 #include <asm/time.h> 54 #include <asm/smp.h> 55 #include <asm/mce.h> 56 #include <asm/tsc.h> 57 #include <asm/hypervisor.h> 58 59 unsigned int num_processors; 60 61 unsigned disabled_cpus; 62 63 /* Processor that is doing the boot up */ 64 unsigned int boot_cpu_physical_apicid = -1U; 65 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); 66 67 /* 68 * The highest APIC ID seen during enumeration. 69 */ 70 static unsigned int max_physical_apicid; 71 72 /* 73 * Bitmask of physically existing CPUs: 74 */ 75 physid_mask_t phys_cpu_present_map; 76 77 /* 78 * Processor to be disabled specified by kernel parameter 79 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to 80 * avoid undefined behaviour caused by sending INIT from AP to BSP. 81 */ 82 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID; 83 84 /* 85 * Map cpu index to physical APIC ID 86 */ 87 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); 88 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); 89 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 90 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 91 92 #ifdef CONFIG_X86_32 93 94 /* 95 * On x86_32, the mapping between cpu and logical apicid may vary 96 * depending on apic in use. The following early percpu variable is 97 * used for the mapping. This is where the behaviors of x86_64 and 32 98 * actually diverge. Let's keep it ugly for now. 99 */ 100 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); 101 102 /* Local APIC was disabled by the BIOS and enabled by the kernel */ 103 static int enabled_via_apicbase; 104 105 /* 106 * Handle interrupt mode configuration register (IMCR). 107 * This register controls whether the interrupt signals 108 * that reach the BSP come from the master PIC or from the 109 * local APIC. Before entering Symmetric I/O Mode, either 110 * the BIOS or the operating system must switch out of 111 * PIC Mode by changing the IMCR. 112 */ 113 static inline void imcr_pic_to_apic(void) 114 { 115 /* select IMCR register */ 116 outb(0x70, 0x22); 117 /* NMI and 8259 INTR go through APIC */ 118 outb(0x01, 0x23); 119 } 120 121 static inline void imcr_apic_to_pic(void) 122 { 123 /* select IMCR register */ 124 outb(0x70, 0x22); 125 /* NMI and 8259 INTR go directly to BSP */ 126 outb(0x00, 0x23); 127 } 128 #endif 129 130 /* 131 * Knob to control our willingness to enable the local APIC. 132 * 133 * +1=force-enable 134 */ 135 static int force_enable_local_apic __initdata; 136 137 /* 138 * APIC command line parameters 139 */ 140 static int __init parse_lapic(char *arg) 141 { 142 if (config_enabled(CONFIG_X86_32) && !arg) 143 force_enable_local_apic = 1; 144 else if (arg && !strncmp(arg, "notscdeadline", 13)) 145 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 146 return 0; 147 } 148 early_param("lapic", parse_lapic); 149 150 #ifdef CONFIG_X86_64 151 static int apic_calibrate_pmtmr __initdata; 152 static __init int setup_apicpmtimer(char *s) 153 { 154 apic_calibrate_pmtmr = 1; 155 notsc_setup(NULL); 156 return 0; 157 } 158 __setup("apicpmtimer", setup_apicpmtimer); 159 #endif 160 161 unsigned long mp_lapic_addr; 162 int disable_apic; 163 /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 164 static int disable_apic_timer __initdata; 165 /* Local APIC timer works in C2 */ 166 int local_apic_timer_c2_ok; 167 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 168 169 int first_system_vector = FIRST_SYSTEM_VECTOR; 170 171 /* 172 * Debug level, exported for io_apic.c 173 */ 174 unsigned int apic_verbosity; 175 176 int pic_mode; 177 178 /* Have we found an MP table */ 179 int smp_found_config; 180 181 static struct resource lapic_resource = { 182 .name = "Local APIC", 183 .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 184 }; 185 186 unsigned int lapic_timer_frequency = 0; 187 188 static void apic_pm_activate(void); 189 190 static unsigned long apic_phys; 191 192 /* 193 * Get the LAPIC version 194 */ 195 static inline int lapic_get_version(void) 196 { 197 return GET_APIC_VERSION(apic_read(APIC_LVR)); 198 } 199 200 /* 201 * Check, if the APIC is integrated or a separate chip 202 */ 203 static inline int lapic_is_integrated(void) 204 { 205 #ifdef CONFIG_X86_64 206 return 1; 207 #else 208 return APIC_INTEGRATED(lapic_get_version()); 209 #endif 210 } 211 212 /* 213 * Check, whether this is a modern or a first generation APIC 214 */ 215 static int modern_apic(void) 216 { 217 /* AMD systems use old APIC versions, so check the CPU */ 218 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 219 boot_cpu_data.x86 >= 0xf) 220 return 1; 221 return lapic_get_version() >= 0x14; 222 } 223 224 /* 225 * right after this call apic become NOOP driven 226 * so apic->write/read doesn't do anything 227 */ 228 static void __init apic_disable(void) 229 { 230 pr_info("APIC: switched to apic NOOP\n"); 231 apic = &apic_noop; 232 } 233 234 void native_apic_wait_icr_idle(void) 235 { 236 while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 237 cpu_relax(); 238 } 239 240 u32 native_safe_apic_wait_icr_idle(void) 241 { 242 u32 send_status; 243 int timeout; 244 245 timeout = 0; 246 do { 247 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 248 if (!send_status) 249 break; 250 inc_irq_stat(icr_read_retry_count); 251 udelay(100); 252 } while (timeout++ < 1000); 253 254 return send_status; 255 } 256 257 void native_apic_icr_write(u32 low, u32 id) 258 { 259 unsigned long flags; 260 261 local_irq_save(flags); 262 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 263 apic_write(APIC_ICR, low); 264 local_irq_restore(flags); 265 } 266 267 u64 native_apic_icr_read(void) 268 { 269 u32 icr1, icr2; 270 271 icr2 = apic_read(APIC_ICR2); 272 icr1 = apic_read(APIC_ICR); 273 274 return icr1 | ((u64)icr2 << 32); 275 } 276 277 #ifdef CONFIG_X86_32 278 /** 279 * get_physical_broadcast - Get number of physical broadcast IDs 280 */ 281 int get_physical_broadcast(void) 282 { 283 return modern_apic() ? 0xff : 0xf; 284 } 285 #endif 286 287 /** 288 * lapic_get_maxlvt - get the maximum number of local vector table entries 289 */ 290 int lapic_get_maxlvt(void) 291 { 292 unsigned int v; 293 294 v = apic_read(APIC_LVR); 295 /* 296 * - we always have APIC integrated on 64bit mode 297 * - 82489DXs do not report # of LVT entries 298 */ 299 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; 300 } 301 302 /* 303 * Local APIC timer 304 */ 305 306 /* Clock divisor */ 307 #define APIC_DIVISOR 16 308 #define TSC_DIVISOR 32 309 310 /* 311 * This function sets up the local APIC timer, with a timeout of 312 * 'clocks' APIC bus clock. During calibration we actually call 313 * this function twice on the boot CPU, once with a bogus timeout 314 * value, second time for real. The other (noncalibrating) CPUs 315 * call this function only once, with the real, calibrated value. 316 * 317 * We do reads before writes even if unnecessary, to get around the 318 * P5 APIC double write bug. 319 */ 320 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 321 { 322 unsigned int lvtt_value, tmp_value; 323 324 lvtt_value = LOCAL_TIMER_VECTOR; 325 if (!oneshot) 326 lvtt_value |= APIC_LVT_TIMER_PERIODIC; 327 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 328 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; 329 330 if (!lapic_is_integrated()) 331 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 332 333 if (!irqen) 334 lvtt_value |= APIC_LVT_MASKED; 335 336 apic_write(APIC_LVTT, lvtt_value); 337 338 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { 339 printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); 340 return; 341 } 342 343 /* 344 * Divide PICLK by 16 345 */ 346 tmp_value = apic_read(APIC_TDCR); 347 apic_write(APIC_TDCR, 348 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 349 APIC_TDR_DIV_16); 350 351 if (!oneshot) 352 apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 353 } 354 355 /* 356 * Setup extended LVT, AMD specific 357 * 358 * Software should use the LVT offsets the BIOS provides. The offsets 359 * are determined by the subsystems using it like those for MCE 360 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 361 * are supported. Beginning with family 10h at least 4 offsets are 362 * available. 363 * 364 * Since the offsets must be consistent for all cores, we keep track 365 * of the LVT offsets in software and reserve the offset for the same 366 * vector also to be used on other cores. An offset is freed by 367 * setting the entry to APIC_EILVT_MASKED. 368 * 369 * If the BIOS is right, there should be no conflicts. Otherwise a 370 * "[Firmware Bug]: ..." error message is generated. However, if 371 * software does not properly determines the offsets, it is not 372 * necessarily a BIOS bug. 373 */ 374 375 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 376 377 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 378 { 379 return (old & APIC_EILVT_MASKED) 380 || (new == APIC_EILVT_MASKED) 381 || ((new & ~APIC_EILVT_MASKED) == old); 382 } 383 384 static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 385 { 386 unsigned int rsvd, vector; 387 388 if (offset >= APIC_EILVT_NR_MAX) 389 return ~0; 390 391 rsvd = atomic_read(&eilvt_offsets[offset]); 392 do { 393 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ 394 if (vector && !eilvt_entry_is_changeable(vector, new)) 395 /* may not change if vectors are different */ 396 return rsvd; 397 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 398 } while (rsvd != new); 399 400 rsvd &= ~APIC_EILVT_MASKED; 401 if (rsvd && rsvd != vector) 402 pr_info("LVT offset %d assigned for vector 0x%02x\n", 403 offset, rsvd); 404 405 return new; 406 } 407 408 /* 409 * If mask=1, the LVT entry does not generate interrupts while mask=0 410 * enables the vector. See also the BKDGs. Must be called with 411 * preemption disabled. 412 */ 413 414 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 415 { 416 unsigned long reg = APIC_EILVTn(offset); 417 unsigned int new, old, reserved; 418 419 new = (mask << 16) | (msg_type << 8) | vector; 420 old = apic_read(reg); 421 reserved = reserve_eilvt_offset(offset, new); 422 423 if (reserved != new) { 424 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 425 "vector 0x%x, but the register is already in use for " 426 "vector 0x%x on another cpu\n", 427 smp_processor_id(), reg, offset, new, reserved); 428 return -EINVAL; 429 } 430 431 if (!eilvt_entry_is_changeable(old, new)) { 432 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 433 "vector 0x%x, but the register is already in use for " 434 "vector 0x%x on this cpu\n", 435 smp_processor_id(), reg, offset, new, old); 436 return -EBUSY; 437 } 438 439 apic_write(reg, new); 440 441 return 0; 442 } 443 EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 444 445 /* 446 * Program the next event, relative to now 447 */ 448 static int lapic_next_event(unsigned long delta, 449 struct clock_event_device *evt) 450 { 451 apic_write(APIC_TMICT, delta); 452 return 0; 453 } 454 455 static int lapic_next_deadline(unsigned long delta, 456 struct clock_event_device *evt) 457 { 458 u64 tsc; 459 460 rdtscll(tsc); 461 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); 462 return 0; 463 } 464 465 /* 466 * Setup the lapic timer in periodic or oneshot mode 467 */ 468 static void lapic_timer_setup(enum clock_event_mode mode, 469 struct clock_event_device *evt) 470 { 471 unsigned long flags; 472 unsigned int v; 473 474 /* Lapic used as dummy for broadcast ? */ 475 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 476 return; 477 478 local_irq_save(flags); 479 480 switch (mode) { 481 case CLOCK_EVT_MODE_PERIODIC: 482 case CLOCK_EVT_MODE_ONESHOT: 483 __setup_APIC_LVTT(lapic_timer_frequency, 484 mode != CLOCK_EVT_MODE_PERIODIC, 1); 485 break; 486 case CLOCK_EVT_MODE_UNUSED: 487 case CLOCK_EVT_MODE_SHUTDOWN: 488 v = apic_read(APIC_LVTT); 489 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 490 apic_write(APIC_LVTT, v); 491 apic_write(APIC_TMICT, 0); 492 break; 493 case CLOCK_EVT_MODE_RESUME: 494 /* Nothing to do here */ 495 break; 496 } 497 498 local_irq_restore(flags); 499 } 500 501 /* 502 * Local APIC timer broadcast function 503 */ 504 static void lapic_timer_broadcast(const struct cpumask *mask) 505 { 506 #ifdef CONFIG_SMP 507 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 508 #endif 509 } 510 511 512 /* 513 * The local apic timer can be used for any function which is CPU local. 514 */ 515 static struct clock_event_device lapic_clockevent = { 516 .name = "lapic", 517 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT 518 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, 519 .shift = 32, 520 .set_mode = lapic_timer_setup, 521 .set_next_event = lapic_next_event, 522 .broadcast = lapic_timer_broadcast, 523 .rating = 100, 524 .irq = -1, 525 }; 526 static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 527 528 /* 529 * Setup the local APIC timer for this CPU. Copy the initialized values 530 * of the boot CPU and register the clock event in the framework. 531 */ 532 static void setup_APIC_timer(void) 533 { 534 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 535 536 if (this_cpu_has(X86_FEATURE_ARAT)) { 537 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 538 /* Make LAPIC timer preferrable over percpu HPET */ 539 lapic_clockevent.rating = 150; 540 } 541 542 memcpy(levt, &lapic_clockevent, sizeof(*levt)); 543 levt->cpumask = cpumask_of(smp_processor_id()); 544 545 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 546 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | 547 CLOCK_EVT_FEAT_DUMMY); 548 levt->set_next_event = lapic_next_deadline; 549 clockevents_config_and_register(levt, 550 (tsc_khz / TSC_DIVISOR) * 1000, 551 0xF, ~0UL); 552 } else 553 clockevents_register_device(levt); 554 } 555 556 /* 557 * In this functions we calibrate APIC bus clocks to the external timer. 558 * 559 * We want to do the calibration only once since we want to have local timer 560 * irqs syncron. CPUs connected by the same APIC bus have the very same bus 561 * frequency. 562 * 563 * This was previously done by reading the PIT/HPET and waiting for a wrap 564 * around to find out, that a tick has elapsed. I have a box, where the PIT 565 * readout is broken, so it never gets out of the wait loop again. This was 566 * also reported by others. 567 * 568 * Monitoring the jiffies value is inaccurate and the clockevents 569 * infrastructure allows us to do a simple substitution of the interrupt 570 * handler. 571 * 572 * The calibration routine also uses the pm_timer when possible, as the PIT 573 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 574 * back to normal later in the boot process). 575 */ 576 577 #define LAPIC_CAL_LOOPS (HZ/10) 578 579 static __initdata int lapic_cal_loops = -1; 580 static __initdata long lapic_cal_t1, lapic_cal_t2; 581 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 582 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 583 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 584 585 /* 586 * Temporary interrupt handler. 587 */ 588 static void __init lapic_cal_handler(struct clock_event_device *dev) 589 { 590 unsigned long long tsc = 0; 591 long tapic = apic_read(APIC_TMCCT); 592 unsigned long pm = acpi_pm_read_early(); 593 594 if (cpu_has_tsc) 595 rdtscll(tsc); 596 597 switch (lapic_cal_loops++) { 598 case 0: 599 lapic_cal_t1 = tapic; 600 lapic_cal_tsc1 = tsc; 601 lapic_cal_pm1 = pm; 602 lapic_cal_j1 = jiffies; 603 break; 604 605 case LAPIC_CAL_LOOPS: 606 lapic_cal_t2 = tapic; 607 lapic_cal_tsc2 = tsc; 608 if (pm < lapic_cal_pm1) 609 pm += ACPI_PM_OVRRUN; 610 lapic_cal_pm2 = pm; 611 lapic_cal_j2 = jiffies; 612 break; 613 } 614 } 615 616 static int __init 617 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 618 { 619 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 620 const long pm_thresh = pm_100ms / 100; 621 unsigned long mult; 622 u64 res; 623 624 #ifndef CONFIG_X86_PM_TIMER 625 return -1; 626 #endif 627 628 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 629 630 /* Check, if the PM timer is available */ 631 if (!deltapm) 632 return -1; 633 634 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 635 636 if (deltapm > (pm_100ms - pm_thresh) && 637 deltapm < (pm_100ms + pm_thresh)) { 638 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 639 return 0; 640 } 641 642 res = (((u64)deltapm) * mult) >> 22; 643 do_div(res, 1000000); 644 pr_warning("APIC calibration not consistent " 645 "with PM-Timer: %ldms instead of 100ms\n",(long)res); 646 647 /* Correct the lapic counter value */ 648 res = (((u64)(*delta)) * pm_100ms); 649 do_div(res, deltapm); 650 pr_info("APIC delta adjusted to PM-Timer: " 651 "%lu (%ld)\n", (unsigned long)res, *delta); 652 *delta = (long)res; 653 654 /* Correct the tsc counter value */ 655 if (cpu_has_tsc) { 656 res = (((u64)(*deltatsc)) * pm_100ms); 657 do_div(res, deltapm); 658 apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 659 "PM-Timer: %lu (%ld)\n", 660 (unsigned long)res, *deltatsc); 661 *deltatsc = (long)res; 662 } 663 664 return 0; 665 } 666 667 static int __init calibrate_APIC_clock(void) 668 { 669 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 670 void (*real_handler)(struct clock_event_device *dev); 671 unsigned long deltaj; 672 long delta, deltatsc; 673 int pm_referenced = 0; 674 675 /** 676 * check if lapic timer has already been calibrated by platform 677 * specific routine, such as tsc calibration code. if so, we just fill 678 * in the clockevent structure and return. 679 */ 680 681 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 682 return 0; 683 } else if (lapic_timer_frequency) { 684 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", 685 lapic_timer_frequency); 686 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR, 687 TICK_NSEC, lapic_clockevent.shift); 688 lapic_clockevent.max_delta_ns = 689 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); 690 lapic_clockevent.min_delta_ns = 691 clockevent_delta2ns(0xF, &lapic_clockevent); 692 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 693 return 0; 694 } 695 696 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 697 "calibrating APIC timer ...\n"); 698 699 local_irq_disable(); 700 701 /* Replace the global interrupt handler */ 702 real_handler = global_clock_event->event_handler; 703 global_clock_event->event_handler = lapic_cal_handler; 704 705 /* 706 * Setup the APIC counter to maximum. There is no way the lapic 707 * can underflow in the 100ms detection time frame 708 */ 709 __setup_APIC_LVTT(0xffffffff, 0, 0); 710 711 /* Let the interrupts run */ 712 local_irq_enable(); 713 714 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 715 cpu_relax(); 716 717 local_irq_disable(); 718 719 /* Restore the real event handler */ 720 global_clock_event->event_handler = real_handler; 721 722 /* Build delta t1-t2 as apic timer counts down */ 723 delta = lapic_cal_t1 - lapic_cal_t2; 724 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 725 726 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 727 728 /* we trust the PM based calibration if possible */ 729 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 730 &delta, &deltatsc); 731 732 /* Calculate the scaled math multiplication factor */ 733 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 734 lapic_clockevent.shift); 735 lapic_clockevent.max_delta_ns = 736 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 737 lapic_clockevent.min_delta_ns = 738 clockevent_delta2ns(0xF, &lapic_clockevent); 739 740 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 741 742 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 743 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 744 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 745 lapic_timer_frequency); 746 747 if (cpu_has_tsc) { 748 apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 749 "%ld.%04ld MHz.\n", 750 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 751 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 752 } 753 754 apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 755 "%u.%04u MHz.\n", 756 lapic_timer_frequency / (1000000 / HZ), 757 lapic_timer_frequency % (1000000 / HZ)); 758 759 /* 760 * Do a sanity check on the APIC calibration result 761 */ 762 if (lapic_timer_frequency < (1000000 / HZ)) { 763 local_irq_enable(); 764 pr_warning("APIC frequency too slow, disabling apic timer\n"); 765 return -1; 766 } 767 768 levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 769 770 /* 771 * PM timer calibration failed or not turned on 772 * so lets try APIC timer based calibration 773 */ 774 if (!pm_referenced) { 775 apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 776 777 /* 778 * Setup the apic timer manually 779 */ 780 levt->event_handler = lapic_cal_handler; 781 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); 782 lapic_cal_loops = -1; 783 784 /* Let the interrupts run */ 785 local_irq_enable(); 786 787 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 788 cpu_relax(); 789 790 /* Stop the lapic timer */ 791 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); 792 793 /* Jiffies delta */ 794 deltaj = lapic_cal_j2 - lapic_cal_j1; 795 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 796 797 /* Check, if the jiffies result is consistent */ 798 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 799 apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 800 else 801 levt->features |= CLOCK_EVT_FEAT_DUMMY; 802 } else 803 local_irq_enable(); 804 805 if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 806 pr_warning("APIC timer disabled due to verification failure\n"); 807 return -1; 808 } 809 810 return 0; 811 } 812 813 /* 814 * Setup the boot APIC 815 * 816 * Calibrate and verify the result. 817 */ 818 void __init setup_boot_APIC_clock(void) 819 { 820 /* 821 * The local apic timer can be disabled via the kernel 822 * commandline or from the CPU detection code. Register the lapic 823 * timer as a dummy clock event source on SMP systems, so the 824 * broadcast mechanism is used. On UP systems simply ignore it. 825 */ 826 if (disable_apic_timer) { 827 pr_info("Disabling APIC timer\n"); 828 /* No broadcast on UP ! */ 829 if (num_possible_cpus() > 1) { 830 lapic_clockevent.mult = 1; 831 setup_APIC_timer(); 832 } 833 return; 834 } 835 836 if (calibrate_APIC_clock()) { 837 /* No broadcast on UP ! */ 838 if (num_possible_cpus() > 1) 839 setup_APIC_timer(); 840 return; 841 } 842 843 /* 844 * If nmi_watchdog is set to IO_APIC, we need the 845 * PIT/HPET going. Otherwise register lapic as a dummy 846 * device. 847 */ 848 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 849 850 /* Setup the lapic or request the broadcast */ 851 setup_APIC_timer(); 852 } 853 854 void setup_secondary_APIC_clock(void) 855 { 856 setup_APIC_timer(); 857 } 858 859 /* 860 * The guts of the apic timer interrupt 861 */ 862 static void local_apic_timer_interrupt(void) 863 { 864 int cpu = smp_processor_id(); 865 struct clock_event_device *evt = &per_cpu(lapic_events, cpu); 866 867 /* 868 * Normally we should not be here till LAPIC has been initialized but 869 * in some cases like kdump, its possible that there is a pending LAPIC 870 * timer interrupt from previous kernel's context and is delivered in 871 * new kernel the moment interrupts are enabled. 872 * 873 * Interrupts are enabled early and LAPIC is setup much later, hence 874 * its possible that when we get here evt->event_handler is NULL. 875 * Check for event_handler being NULL and discard the interrupt as 876 * spurious. 877 */ 878 if (!evt->event_handler) { 879 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); 880 /* Switch it off */ 881 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); 882 return; 883 } 884 885 /* 886 * the NMI deadlock-detector uses this. 887 */ 888 inc_irq_stat(apic_timer_irqs); 889 890 evt->event_handler(evt); 891 } 892 893 /* 894 * Local APIC timer interrupt. This is the most natural way for doing 895 * local interrupts, but local timer interrupts can be emulated by 896 * broadcast interrupts too. [in case the hw doesn't support APIC timers] 897 * 898 * [ if a single-CPU system runs an SMP kernel then we call the local 899 * interrupt as well. Thus we cannot inline the local irq ... ] 900 */ 901 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 902 { 903 struct pt_regs *old_regs = set_irq_regs(regs); 904 905 /* 906 * NOTE! We'd better ACK the irq immediately, 907 * because timer handling can be slow. 908 * 909 * update_process_times() expects us to have done irq_enter(). 910 * Besides, if we don't timer interrupts ignore the global 911 * interrupt lock, which is the WrongThing (tm) to do. 912 */ 913 entering_ack_irq(); 914 local_apic_timer_interrupt(); 915 exiting_irq(); 916 917 set_irq_regs(old_regs); 918 } 919 920 __visible void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs) 921 { 922 struct pt_regs *old_regs = set_irq_regs(regs); 923 924 /* 925 * NOTE! We'd better ACK the irq immediately, 926 * because timer handling can be slow. 927 * 928 * update_process_times() expects us to have done irq_enter(). 929 * Besides, if we don't timer interrupts ignore the global 930 * interrupt lock, which is the WrongThing (tm) to do. 931 */ 932 entering_ack_irq(); 933 trace_local_timer_entry(LOCAL_TIMER_VECTOR); 934 local_apic_timer_interrupt(); 935 trace_local_timer_exit(LOCAL_TIMER_VECTOR); 936 exiting_irq(); 937 938 set_irq_regs(old_regs); 939 } 940 941 int setup_profiling_timer(unsigned int multiplier) 942 { 943 return -EINVAL; 944 } 945 946 /* 947 * Local APIC start and shutdown 948 */ 949 950 /** 951 * clear_local_APIC - shutdown the local APIC 952 * 953 * This is called, when a CPU is disabled and before rebooting, so the state of 954 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 955 * leftovers during boot. 956 */ 957 void clear_local_APIC(void) 958 { 959 int maxlvt; 960 u32 v; 961 962 /* APIC hasn't been mapped yet */ 963 if (!x2apic_mode && !apic_phys) 964 return; 965 966 maxlvt = lapic_get_maxlvt(); 967 /* 968 * Masking an LVT entry can trigger a local APIC error 969 * if the vector is zero. Mask LVTERR first to prevent this. 970 */ 971 if (maxlvt >= 3) { 972 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 973 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 974 } 975 /* 976 * Careful: we have to set masks only first to deassert 977 * any level-triggered sources. 978 */ 979 v = apic_read(APIC_LVTT); 980 apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 981 v = apic_read(APIC_LVT0); 982 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 983 v = apic_read(APIC_LVT1); 984 apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 985 if (maxlvt >= 4) { 986 v = apic_read(APIC_LVTPC); 987 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 988 } 989 990 /* lets not touch this if we didn't frob it */ 991 #ifdef CONFIG_X86_THERMAL_VECTOR 992 if (maxlvt >= 5) { 993 v = apic_read(APIC_LVTTHMR); 994 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 995 } 996 #endif 997 #ifdef CONFIG_X86_MCE_INTEL 998 if (maxlvt >= 6) { 999 v = apic_read(APIC_LVTCMCI); 1000 if (!(v & APIC_LVT_MASKED)) 1001 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 1002 } 1003 #endif 1004 1005 /* 1006 * Clean APIC state for other OSs: 1007 */ 1008 apic_write(APIC_LVTT, APIC_LVT_MASKED); 1009 apic_write(APIC_LVT0, APIC_LVT_MASKED); 1010 apic_write(APIC_LVT1, APIC_LVT_MASKED); 1011 if (maxlvt >= 3) 1012 apic_write(APIC_LVTERR, APIC_LVT_MASKED); 1013 if (maxlvt >= 4) 1014 apic_write(APIC_LVTPC, APIC_LVT_MASKED); 1015 1016 /* Integrated APIC (!82489DX) ? */ 1017 if (lapic_is_integrated()) { 1018 if (maxlvt > 3) 1019 /* Clear ESR due to Pentium errata 3AP and 11AP */ 1020 apic_write(APIC_ESR, 0); 1021 apic_read(APIC_ESR); 1022 } 1023 } 1024 1025 /** 1026 * disable_local_APIC - clear and disable the local APIC 1027 */ 1028 void disable_local_APIC(void) 1029 { 1030 unsigned int value; 1031 1032 /* APIC hasn't been mapped yet */ 1033 if (!x2apic_mode && !apic_phys) 1034 return; 1035 1036 clear_local_APIC(); 1037 1038 /* 1039 * Disable APIC (implies clearing of registers 1040 * for 82489DX!). 1041 */ 1042 value = apic_read(APIC_SPIV); 1043 value &= ~APIC_SPIV_APIC_ENABLED; 1044 apic_write(APIC_SPIV, value); 1045 1046 #ifdef CONFIG_X86_32 1047 /* 1048 * When LAPIC was disabled by the BIOS and enabled by the kernel, 1049 * restore the disabled state. 1050 */ 1051 if (enabled_via_apicbase) { 1052 unsigned int l, h; 1053 1054 rdmsr(MSR_IA32_APICBASE, l, h); 1055 l &= ~MSR_IA32_APICBASE_ENABLE; 1056 wrmsr(MSR_IA32_APICBASE, l, h); 1057 } 1058 #endif 1059 } 1060 1061 /* 1062 * If Linux enabled the LAPIC against the BIOS default disable it down before 1063 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1064 * not power-off. Additionally clear all LVT entries before disable_local_APIC 1065 * for the case where Linux didn't enable the LAPIC. 1066 */ 1067 void lapic_shutdown(void) 1068 { 1069 unsigned long flags; 1070 1071 if (!cpu_has_apic && !apic_from_smp_config()) 1072 return; 1073 1074 local_irq_save(flags); 1075 1076 #ifdef CONFIG_X86_32 1077 if (!enabled_via_apicbase) 1078 clear_local_APIC(); 1079 else 1080 #endif 1081 disable_local_APIC(); 1082 1083 1084 local_irq_restore(flags); 1085 } 1086 1087 /* 1088 * This is to verify that we're looking at a real local APIC. 1089 * Check these against your board if the CPUs aren't getting 1090 * started for no apparent reason. 1091 */ 1092 int __init verify_local_APIC(void) 1093 { 1094 unsigned int reg0, reg1; 1095 1096 /* 1097 * The version register is read-only in a real APIC. 1098 */ 1099 reg0 = apic_read(APIC_LVR); 1100 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); 1101 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); 1102 reg1 = apic_read(APIC_LVR); 1103 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); 1104 1105 /* 1106 * The two version reads above should print the same 1107 * numbers. If the second one is different, then we 1108 * poke at a non-APIC. 1109 */ 1110 if (reg1 != reg0) 1111 return 0; 1112 1113 /* 1114 * Check if the version looks reasonably. 1115 */ 1116 reg1 = GET_APIC_VERSION(reg0); 1117 if (reg1 == 0x00 || reg1 == 0xff) 1118 return 0; 1119 reg1 = lapic_get_maxlvt(); 1120 if (reg1 < 0x02 || reg1 == 0xff) 1121 return 0; 1122 1123 /* 1124 * The ID register is read/write in a real APIC. 1125 */ 1126 reg0 = apic_read(APIC_ID); 1127 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); 1128 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask); 1129 reg1 = apic_read(APIC_ID); 1130 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); 1131 apic_write(APIC_ID, reg0); 1132 if (reg1 != (reg0 ^ apic->apic_id_mask)) 1133 return 0; 1134 1135 /* 1136 * The next two are just to see if we have sane values. 1137 * They're only really relevant if we're in Virtual Wire 1138 * compatibility mode, but most boxes are anymore. 1139 */ 1140 reg0 = apic_read(APIC_LVT0); 1141 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); 1142 reg1 = apic_read(APIC_LVT1); 1143 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); 1144 1145 return 1; 1146 } 1147 1148 /** 1149 * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1150 */ 1151 void __init sync_Arb_IDs(void) 1152 { 1153 /* 1154 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1155 * needed on AMD. 1156 */ 1157 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1158 return; 1159 1160 /* 1161 * Wait for idle. 1162 */ 1163 apic_wait_icr_idle(); 1164 1165 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1166 apic_write(APIC_ICR, APIC_DEST_ALLINC | 1167 APIC_INT_LEVELTRIG | APIC_DM_INIT); 1168 } 1169 1170 /* 1171 * An initial setup of the virtual wire mode. 1172 */ 1173 void __init init_bsp_APIC(void) 1174 { 1175 unsigned int value; 1176 1177 /* 1178 * Don't do the setup now if we have a SMP BIOS as the 1179 * through-I/O-APIC virtual wire mode might be active. 1180 */ 1181 if (smp_found_config || !cpu_has_apic) 1182 return; 1183 1184 /* 1185 * Do not trust the local APIC being empty at bootup. 1186 */ 1187 clear_local_APIC(); 1188 1189 /* 1190 * Enable APIC. 1191 */ 1192 value = apic_read(APIC_SPIV); 1193 value &= ~APIC_VECTOR_MASK; 1194 value |= APIC_SPIV_APIC_ENABLED; 1195 1196 #ifdef CONFIG_X86_32 1197 /* This bit is reserved on P4/Xeon and should be cleared */ 1198 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1199 (boot_cpu_data.x86 == 15)) 1200 value &= ~APIC_SPIV_FOCUS_DISABLED; 1201 else 1202 #endif 1203 value |= APIC_SPIV_FOCUS_DISABLED; 1204 value |= SPURIOUS_APIC_VECTOR; 1205 apic_write(APIC_SPIV, value); 1206 1207 /* 1208 * Set up the virtual wire mode. 1209 */ 1210 apic_write(APIC_LVT0, APIC_DM_EXTINT); 1211 value = APIC_DM_NMI; 1212 if (!lapic_is_integrated()) /* 82489DX */ 1213 value |= APIC_LVT_LEVEL_TRIGGER; 1214 apic_write(APIC_LVT1, value); 1215 } 1216 1217 static void lapic_setup_esr(void) 1218 { 1219 unsigned int oldvalue, value, maxlvt; 1220 1221 if (!lapic_is_integrated()) { 1222 pr_info("No ESR for 82489DX.\n"); 1223 return; 1224 } 1225 1226 if (apic->disable_esr) { 1227 /* 1228 * Something untraceable is creating bad interrupts on 1229 * secondary quads ... for the moment, just leave the 1230 * ESR disabled - we can't do anything useful with the 1231 * errors anyway - mbligh 1232 */ 1233 pr_info("Leaving ESR disabled.\n"); 1234 return; 1235 } 1236 1237 maxlvt = lapic_get_maxlvt(); 1238 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1239 apic_write(APIC_ESR, 0); 1240 oldvalue = apic_read(APIC_ESR); 1241 1242 /* enables sending errors */ 1243 value = ERROR_APIC_VECTOR; 1244 apic_write(APIC_LVTERR, value); 1245 1246 /* 1247 * spec says clear errors after enabling vector. 1248 */ 1249 if (maxlvt > 3) 1250 apic_write(APIC_ESR, 0); 1251 value = apic_read(APIC_ESR); 1252 if (value != oldvalue) 1253 apic_printk(APIC_VERBOSE, "ESR value before enabling " 1254 "vector: 0x%08x after: 0x%08x\n", 1255 oldvalue, value); 1256 } 1257 1258 /** 1259 * setup_local_APIC - setup the local APIC 1260 * 1261 * Used to setup local APIC while initializing BSP or bringin up APs. 1262 * Always called with preemption disabled. 1263 */ 1264 void setup_local_APIC(void) 1265 { 1266 int cpu = smp_processor_id(); 1267 unsigned int value, queued; 1268 int i, j, acked = 0; 1269 unsigned long long tsc = 0, ntsc; 1270 long long max_loops = cpu_khz ? cpu_khz : 1000000; 1271 1272 if (cpu_has_tsc) 1273 rdtscll(tsc); 1274 1275 if (disable_apic) { 1276 disable_ioapic_support(); 1277 return; 1278 } 1279 1280 #ifdef CONFIG_X86_32 1281 /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1282 if (lapic_is_integrated() && apic->disable_esr) { 1283 apic_write(APIC_ESR, 0); 1284 apic_write(APIC_ESR, 0); 1285 apic_write(APIC_ESR, 0); 1286 apic_write(APIC_ESR, 0); 1287 } 1288 #endif 1289 perf_events_lapic_init(); 1290 1291 /* 1292 * Double-check whether this APIC is really registered. 1293 * This is meaningless in clustered apic mode, so we skip it. 1294 */ 1295 BUG_ON(!apic->apic_id_registered()); 1296 1297 /* 1298 * Intel recommends to set DFR, LDR and TPR before enabling 1299 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1300 * document number 292116). So here it goes... 1301 */ 1302 apic->init_apic_ldr(); 1303 1304 #ifdef CONFIG_X86_32 1305 /* 1306 * APIC LDR is initialized. If logical_apicid mapping was 1307 * initialized during get_smp_config(), make sure it matches the 1308 * actual value. 1309 */ 1310 i = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 1311 WARN_ON(i != BAD_APICID && i != logical_smp_processor_id()); 1312 /* always use the value from LDR */ 1313 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 1314 logical_smp_processor_id(); 1315 #endif 1316 1317 /* 1318 * Set Task Priority to 'accept all'. We never change this 1319 * later on. 1320 */ 1321 value = apic_read(APIC_TASKPRI); 1322 value &= ~APIC_TPRI_MASK; 1323 apic_write(APIC_TASKPRI, value); 1324 1325 /* 1326 * After a crash, we no longer service the interrupts and a pending 1327 * interrupt from previous kernel might still have ISR bit set. 1328 * 1329 * Most probably by now CPU has serviced that pending interrupt and 1330 * it might not have done the ack_APIC_irq() because it thought, 1331 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1332 * does not clear the ISR bit and cpu thinks it has already serivced 1333 * the interrupt. Hence a vector might get locked. It was noticed 1334 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1335 */ 1336 do { 1337 queued = 0; 1338 for (i = APIC_ISR_NR - 1; i >= 0; i--) 1339 queued |= apic_read(APIC_IRR + i*0x10); 1340 1341 for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1342 value = apic_read(APIC_ISR + i*0x10); 1343 for (j = 31; j >= 0; j--) { 1344 if (value & (1<<j)) { 1345 ack_APIC_irq(); 1346 acked++; 1347 } 1348 } 1349 } 1350 if (acked > 256) { 1351 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", 1352 acked); 1353 break; 1354 } 1355 if (queued) { 1356 if (cpu_has_tsc && cpu_khz) { 1357 rdtscll(ntsc); 1358 max_loops = (cpu_khz << 10) - (ntsc - tsc); 1359 } else 1360 max_loops--; 1361 } 1362 } while (queued && max_loops > 0); 1363 WARN_ON(max_loops <= 0); 1364 1365 /* 1366 * Now that we are all set up, enable the APIC 1367 */ 1368 value = apic_read(APIC_SPIV); 1369 value &= ~APIC_VECTOR_MASK; 1370 /* 1371 * Enable APIC 1372 */ 1373 value |= APIC_SPIV_APIC_ENABLED; 1374 1375 #ifdef CONFIG_X86_32 1376 /* 1377 * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1378 * certain networking cards. If high frequency interrupts are 1379 * happening on a particular IOAPIC pin, plus the IOAPIC routing 1380 * entry is masked/unmasked at a high rate as well then sooner or 1381 * later IOAPIC line gets 'stuck', no more interrupts are received 1382 * from the device. If focus CPU is disabled then the hang goes 1383 * away, oh well :-( 1384 * 1385 * [ This bug can be reproduced easily with a level-triggered 1386 * PCI Ne2000 networking cards and PII/PIII processors, dual 1387 * BX chipset. ] 1388 */ 1389 /* 1390 * Actually disabling the focus CPU check just makes the hang less 1391 * frequent as it makes the interrupt distributon model be more 1392 * like LRU than MRU (the short-term load is more even across CPUs). 1393 * See also the comment in end_level_ioapic_irq(). --macro 1394 */ 1395 1396 /* 1397 * - enable focus processor (bit==0) 1398 * - 64bit mode always use processor focus 1399 * so no need to set it 1400 */ 1401 value &= ~APIC_SPIV_FOCUS_DISABLED; 1402 #endif 1403 1404 /* 1405 * Set spurious IRQ vector 1406 */ 1407 value |= SPURIOUS_APIC_VECTOR; 1408 apic_write(APIC_SPIV, value); 1409 1410 /* 1411 * Set up LVT0, LVT1: 1412 * 1413 * set up through-local-APIC on the BP's LINT0. This is not 1414 * strictly necessary in pure symmetric-IO mode, but sometimes 1415 * we delegate interrupts to the 8259A. 1416 */ 1417 /* 1418 * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1419 */ 1420 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1421 if (!cpu && (pic_mode || !value)) { 1422 value = APIC_DM_EXTINT; 1423 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1424 } else { 1425 value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1426 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1427 } 1428 apic_write(APIC_LVT0, value); 1429 1430 /* 1431 * only the BP should see the LINT1 NMI signal, obviously. 1432 */ 1433 if (!cpu) 1434 value = APIC_DM_NMI; 1435 else 1436 value = APIC_DM_NMI | APIC_LVT_MASKED; 1437 if (!lapic_is_integrated()) /* 82489DX */ 1438 value |= APIC_LVT_LEVEL_TRIGGER; 1439 apic_write(APIC_LVT1, value); 1440 1441 #ifdef CONFIG_X86_MCE_INTEL 1442 /* Recheck CMCI information after local APIC is up on CPU #0 */ 1443 if (!cpu) 1444 cmci_recheck(); 1445 #endif 1446 } 1447 1448 static void end_local_APIC_setup(void) 1449 { 1450 lapic_setup_esr(); 1451 1452 #ifdef CONFIG_X86_32 1453 { 1454 unsigned int value; 1455 /* Disable the local apic timer */ 1456 value = apic_read(APIC_LVTT); 1457 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1458 apic_write(APIC_LVTT, value); 1459 } 1460 #endif 1461 1462 apic_pm_activate(); 1463 } 1464 1465 /* 1466 * APIC setup function for application processors. Called from smpboot.c 1467 */ 1468 void apic_ap_setup(void) 1469 { 1470 setup_local_APIC(); 1471 end_local_APIC_setup(); 1472 } 1473 1474 #ifdef CONFIG_X86_X2APIC 1475 int x2apic_mode; 1476 1477 enum { 1478 X2APIC_OFF, 1479 X2APIC_ON, 1480 X2APIC_DISABLED, 1481 }; 1482 static int x2apic_state; 1483 1484 static inline void __x2apic_disable(void) 1485 { 1486 u64 msr; 1487 1488 if (cpu_has_apic) 1489 return; 1490 1491 rdmsrl(MSR_IA32_APICBASE, msr); 1492 if (!(msr & X2APIC_ENABLE)) 1493 return; 1494 /* Disable xapic and x2apic first and then reenable xapic mode */ 1495 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); 1496 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); 1497 printk_once(KERN_INFO "x2apic disabled\n"); 1498 } 1499 1500 static inline void __x2apic_enable(void) 1501 { 1502 u64 msr; 1503 1504 rdmsrl(MSR_IA32_APICBASE, msr); 1505 if (msr & X2APIC_ENABLE) 1506 return; 1507 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); 1508 printk_once(KERN_INFO "x2apic enabled\n"); 1509 } 1510 1511 static int __init setup_nox2apic(char *str) 1512 { 1513 if (x2apic_enabled()) { 1514 int apicid = native_apic_msr_read(APIC_ID); 1515 1516 if (apicid >= 255) { 1517 pr_warning("Apicid: %08x, cannot enforce nox2apic\n", 1518 apicid); 1519 return 0; 1520 } 1521 pr_warning("x2apic already enabled.\n"); 1522 __x2apic_disable(); 1523 } 1524 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 1525 x2apic_state = X2APIC_DISABLED; 1526 x2apic_mode = 0; 1527 return 0; 1528 } 1529 early_param("nox2apic", setup_nox2apic); 1530 1531 /* Called from cpu_init() to enable x2apic on (secondary) cpus */ 1532 void x2apic_setup(void) 1533 { 1534 /* 1535 * If x2apic is not in ON state, disable it if already enabled 1536 * from BIOS. 1537 */ 1538 if (x2apic_state != X2APIC_ON) { 1539 __x2apic_disable(); 1540 return; 1541 } 1542 __x2apic_enable(); 1543 } 1544 1545 static __init void x2apic_disable(void) 1546 { 1547 u32 x2apic_id; 1548 1549 if (x2apic_state != X2APIC_ON) 1550 goto out; 1551 1552 x2apic_id = read_apic_id(); 1553 if (x2apic_id >= 255) 1554 panic("Cannot disable x2apic, id: %08x\n", x2apic_id); 1555 1556 __x2apic_disable(); 1557 register_lapic_address(mp_lapic_addr); 1558 out: 1559 x2apic_state = X2APIC_DISABLED; 1560 x2apic_mode = 0; 1561 } 1562 1563 static __init void x2apic_enable(void) 1564 { 1565 if (x2apic_state != X2APIC_OFF) 1566 return; 1567 1568 x2apic_mode = 1; 1569 x2apic_state = X2APIC_ON; 1570 __x2apic_enable(); 1571 } 1572 1573 static __init void try_to_enable_x2apic(int remap_mode) 1574 { 1575 if (x2apic_state == X2APIC_DISABLED) 1576 return; 1577 1578 if (remap_mode != IRQ_REMAP_X2APIC_MODE) { 1579 /* IR is required if there is APIC ID > 255 even when running 1580 * under KVM 1581 */ 1582 if (max_physical_apicid > 255 || 1583 !hypervisor_x2apic_available()) { 1584 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); 1585 x2apic_disable(); 1586 return; 1587 } 1588 1589 /* 1590 * without IR all CPUs can be addressed by IOAPIC/MSI 1591 * only in physical mode 1592 */ 1593 x2apic_phys = 1; 1594 } 1595 x2apic_enable(); 1596 } 1597 1598 void __init check_x2apic(void) 1599 { 1600 if (x2apic_enabled()) { 1601 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); 1602 x2apic_mode = 1; 1603 x2apic_state = X2APIC_ON; 1604 } else if (!cpu_has_x2apic) { 1605 x2apic_state = X2APIC_DISABLED; 1606 } 1607 } 1608 #else /* CONFIG_X86_X2APIC */ 1609 static int __init validate_x2apic(void) 1610 { 1611 if (!apic_is_x2apic_enabled()) 1612 return 0; 1613 /* 1614 * Checkme: Can we simply turn off x2apic here instead of panic? 1615 */ 1616 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n"); 1617 } 1618 early_initcall(validate_x2apic); 1619 1620 static inline void try_to_enable_x2apic(int remap_mode) { } 1621 static inline void __x2apic_enable(void) { } 1622 #endif /* !CONFIG_X86_X2APIC */ 1623 1624 static int __init try_to_enable_IR(void) 1625 { 1626 #ifdef CONFIG_X86_IO_APIC 1627 if (!x2apic_enabled() && skip_ioapic_setup) { 1628 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); 1629 return -1; 1630 } 1631 #endif 1632 return irq_remapping_enable(); 1633 } 1634 1635 void __init enable_IR_x2apic(void) 1636 { 1637 unsigned long flags; 1638 int ret, ir_stat; 1639 1640 ir_stat = irq_remapping_prepare(); 1641 if (ir_stat < 0 && !x2apic_supported()) 1642 return; 1643 1644 ret = save_ioapic_entries(); 1645 if (ret) { 1646 pr_info("Saving IO-APIC state failed: %d\n", ret); 1647 return; 1648 } 1649 1650 local_irq_save(flags); 1651 legacy_pic->mask_all(); 1652 mask_ioapic_entries(); 1653 1654 /* If irq_remapping_prepare() succeded, try to enable it */ 1655 if (ir_stat >= 0) 1656 ir_stat = try_to_enable_IR(); 1657 /* ir_stat contains the remap mode or an error code */ 1658 try_to_enable_x2apic(ir_stat); 1659 1660 if (ir_stat < 0) 1661 restore_ioapic_entries(); 1662 legacy_pic->restore_mask(); 1663 local_irq_restore(flags); 1664 } 1665 1666 #ifdef CONFIG_X86_64 1667 /* 1668 * Detect and enable local APICs on non-SMP boards. 1669 * Original code written by Keir Fraser. 1670 * On AMD64 we trust the BIOS - if it says no APIC it is likely 1671 * not correctly set up (usually the APIC timer won't work etc.) 1672 */ 1673 static int __init detect_init_APIC(void) 1674 { 1675 if (!cpu_has_apic) { 1676 pr_info("No local APIC present\n"); 1677 return -1; 1678 } 1679 1680 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1681 return 0; 1682 } 1683 #else 1684 1685 static int __init apic_verify(void) 1686 { 1687 u32 features, h, l; 1688 1689 /* 1690 * The APIC feature bit should now be enabled 1691 * in `cpuid' 1692 */ 1693 features = cpuid_edx(1); 1694 if (!(features & (1 << X86_FEATURE_APIC))) { 1695 pr_warning("Could not enable APIC!\n"); 1696 return -1; 1697 } 1698 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1699 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1700 1701 /* The BIOS may have set up the APIC at some other address */ 1702 if (boot_cpu_data.x86 >= 6) { 1703 rdmsr(MSR_IA32_APICBASE, l, h); 1704 if (l & MSR_IA32_APICBASE_ENABLE) 1705 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1706 } 1707 1708 pr_info("Found and enabled local APIC!\n"); 1709 return 0; 1710 } 1711 1712 int __init apic_force_enable(unsigned long addr) 1713 { 1714 u32 h, l; 1715 1716 if (disable_apic) 1717 return -1; 1718 1719 /* 1720 * Some BIOSes disable the local APIC in the APIC_BASE 1721 * MSR. This can only be done in software for Intel P6 or later 1722 * and AMD K7 (Model > 1) or later. 1723 */ 1724 if (boot_cpu_data.x86 >= 6) { 1725 rdmsr(MSR_IA32_APICBASE, l, h); 1726 if (!(l & MSR_IA32_APICBASE_ENABLE)) { 1727 pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 1728 l &= ~MSR_IA32_APICBASE_BASE; 1729 l |= MSR_IA32_APICBASE_ENABLE | addr; 1730 wrmsr(MSR_IA32_APICBASE, l, h); 1731 enabled_via_apicbase = 1; 1732 } 1733 } 1734 return apic_verify(); 1735 } 1736 1737 /* 1738 * Detect and initialize APIC 1739 */ 1740 static int __init detect_init_APIC(void) 1741 { 1742 /* Disabled by kernel option? */ 1743 if (disable_apic) 1744 return -1; 1745 1746 switch (boot_cpu_data.x86_vendor) { 1747 case X86_VENDOR_AMD: 1748 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1749 (boot_cpu_data.x86 >= 15)) 1750 break; 1751 goto no_apic; 1752 case X86_VENDOR_INTEL: 1753 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1754 (boot_cpu_data.x86 == 5 && cpu_has_apic)) 1755 break; 1756 goto no_apic; 1757 default: 1758 goto no_apic; 1759 } 1760 1761 if (!cpu_has_apic) { 1762 /* 1763 * Over-ride BIOS and try to enable the local APIC only if 1764 * "lapic" specified. 1765 */ 1766 if (!force_enable_local_apic) { 1767 pr_info("Local APIC disabled by BIOS -- " 1768 "you can enable it with \"lapic\"\n"); 1769 return -1; 1770 } 1771 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 1772 return -1; 1773 } else { 1774 if (apic_verify()) 1775 return -1; 1776 } 1777 1778 apic_pm_activate(); 1779 1780 return 0; 1781 1782 no_apic: 1783 pr_info("No local APIC present or hardware disabled\n"); 1784 return -1; 1785 } 1786 #endif 1787 1788 /** 1789 * init_apic_mappings - initialize APIC mappings 1790 */ 1791 void __init init_apic_mappings(void) 1792 { 1793 unsigned int new_apicid; 1794 1795 if (x2apic_mode) { 1796 boot_cpu_physical_apicid = read_apic_id(); 1797 return; 1798 } 1799 1800 /* If no local APIC can be found return early */ 1801 if (!smp_found_config && detect_init_APIC()) { 1802 /* lets NOP'ify apic operations */ 1803 pr_info("APIC: disable apic facility\n"); 1804 apic_disable(); 1805 } else { 1806 apic_phys = mp_lapic_addr; 1807 1808 /* 1809 * acpi lapic path already maps that address in 1810 * acpi_register_lapic_address() 1811 */ 1812 if (!acpi_lapic && !smp_found_config) 1813 register_lapic_address(apic_phys); 1814 } 1815 1816 /* 1817 * Fetch the APIC ID of the BSP in case we have a 1818 * default configuration (or the MP table is broken). 1819 */ 1820 new_apicid = read_apic_id(); 1821 if (boot_cpu_physical_apicid != new_apicid) { 1822 boot_cpu_physical_apicid = new_apicid; 1823 /* 1824 * yeah -- we lie about apic_version 1825 * in case if apic was disabled via boot option 1826 * but it's not a problem for SMP compiled kernel 1827 * since smp_sanity_check is prepared for such a case 1828 * and disable smp mode 1829 */ 1830 apic_version[new_apicid] = 1831 GET_APIC_VERSION(apic_read(APIC_LVR)); 1832 } 1833 } 1834 1835 void __init register_lapic_address(unsigned long address) 1836 { 1837 mp_lapic_addr = address; 1838 1839 if (!x2apic_mode) { 1840 set_fixmap_nocache(FIX_APIC_BASE, address); 1841 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 1842 APIC_BASE, mp_lapic_addr); 1843 } 1844 if (boot_cpu_physical_apicid == -1U) { 1845 boot_cpu_physical_apicid = read_apic_id(); 1846 apic_version[boot_cpu_physical_apicid] = 1847 GET_APIC_VERSION(apic_read(APIC_LVR)); 1848 } 1849 } 1850 1851 int apic_version[MAX_LOCAL_APIC]; 1852 1853 /* 1854 * Local APIC interrupts 1855 */ 1856 1857 /* 1858 * This interrupt should _never_ happen with our APIC/SMP architecture 1859 */ 1860 static inline void __smp_spurious_interrupt(u8 vector) 1861 { 1862 u32 v; 1863 1864 /* 1865 * Check if this really is a spurious interrupt and ACK it 1866 * if it is a vectored one. Just in case... 1867 * Spurious interrupts should not be ACKed. 1868 */ 1869 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); 1870 if (v & (1 << (vector & 0x1f))) 1871 ack_APIC_irq(); 1872 1873 inc_irq_stat(irq_spurious_count); 1874 1875 /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 1876 pr_info("spurious APIC interrupt through vector %02x on CPU#%d, " 1877 "should never happen.\n", vector, smp_processor_id()); 1878 } 1879 1880 __visible void smp_spurious_interrupt(struct pt_regs *regs) 1881 { 1882 entering_irq(); 1883 __smp_spurious_interrupt(~regs->orig_ax); 1884 exiting_irq(); 1885 } 1886 1887 __visible void smp_trace_spurious_interrupt(struct pt_regs *regs) 1888 { 1889 u8 vector = ~regs->orig_ax; 1890 1891 entering_irq(); 1892 trace_spurious_apic_entry(vector); 1893 __smp_spurious_interrupt(vector); 1894 trace_spurious_apic_exit(vector); 1895 exiting_irq(); 1896 } 1897 1898 /* 1899 * This interrupt should never happen with our APIC/SMP architecture 1900 */ 1901 static inline void __smp_error_interrupt(struct pt_regs *regs) 1902 { 1903 u32 v; 1904 u32 i = 0; 1905 static const char * const error_interrupt_reason[] = { 1906 "Send CS error", /* APIC Error Bit 0 */ 1907 "Receive CS error", /* APIC Error Bit 1 */ 1908 "Send accept error", /* APIC Error Bit 2 */ 1909 "Receive accept error", /* APIC Error Bit 3 */ 1910 "Redirectable IPI", /* APIC Error Bit 4 */ 1911 "Send illegal vector", /* APIC Error Bit 5 */ 1912 "Received illegal vector", /* APIC Error Bit 6 */ 1913 "Illegal register address", /* APIC Error Bit 7 */ 1914 }; 1915 1916 /* First tickle the hardware, only then report what went on. -- REW */ 1917 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ 1918 apic_write(APIC_ESR, 0); 1919 v = apic_read(APIC_ESR); 1920 ack_APIC_irq(); 1921 atomic_inc(&irq_err_count); 1922 1923 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", 1924 smp_processor_id(), v); 1925 1926 v &= 0xff; 1927 while (v) { 1928 if (v & 0x1) 1929 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 1930 i++; 1931 v >>= 1; 1932 } 1933 1934 apic_printk(APIC_DEBUG, KERN_CONT "\n"); 1935 1936 } 1937 1938 __visible void smp_error_interrupt(struct pt_regs *regs) 1939 { 1940 entering_irq(); 1941 __smp_error_interrupt(regs); 1942 exiting_irq(); 1943 } 1944 1945 __visible void smp_trace_error_interrupt(struct pt_regs *regs) 1946 { 1947 entering_irq(); 1948 trace_error_apic_entry(ERROR_APIC_VECTOR); 1949 __smp_error_interrupt(regs); 1950 trace_error_apic_exit(ERROR_APIC_VECTOR); 1951 exiting_irq(); 1952 } 1953 1954 /** 1955 * connect_bsp_APIC - attach the APIC to the interrupt system 1956 */ 1957 static void __init connect_bsp_APIC(void) 1958 { 1959 #ifdef CONFIG_X86_32 1960 if (pic_mode) { 1961 /* 1962 * Do not trust the local APIC being empty at bootup. 1963 */ 1964 clear_local_APIC(); 1965 /* 1966 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 1967 * local APIC to INT and NMI lines. 1968 */ 1969 apic_printk(APIC_VERBOSE, "leaving PIC mode, " 1970 "enabling APIC mode.\n"); 1971 imcr_pic_to_apic(); 1972 } 1973 #endif 1974 } 1975 1976 /** 1977 * disconnect_bsp_APIC - detach the APIC from the interrupt system 1978 * @virt_wire_setup: indicates, whether virtual wire mode is selected 1979 * 1980 * Virtual wire mode is necessary to deliver legacy interrupts even when the 1981 * APIC is disabled. 1982 */ 1983 void disconnect_bsp_APIC(int virt_wire_setup) 1984 { 1985 unsigned int value; 1986 1987 #ifdef CONFIG_X86_32 1988 if (pic_mode) { 1989 /* 1990 * Put the board back into PIC mode (has an effect only on 1991 * certain older boards). Note that APIC interrupts, including 1992 * IPIs, won't work beyond this point! The only exception are 1993 * INIT IPIs. 1994 */ 1995 apic_printk(APIC_VERBOSE, "disabling APIC mode, " 1996 "entering PIC mode.\n"); 1997 imcr_apic_to_pic(); 1998 return; 1999 } 2000 #endif 2001 2002 /* Go back to Virtual Wire compatibility mode */ 2003 2004 /* For the spurious interrupt use vector F, and enable it */ 2005 value = apic_read(APIC_SPIV); 2006 value &= ~APIC_VECTOR_MASK; 2007 value |= APIC_SPIV_APIC_ENABLED; 2008 value |= 0xf; 2009 apic_write(APIC_SPIV, value); 2010 2011 if (!virt_wire_setup) { 2012 /* 2013 * For LVT0 make it edge triggered, active high, 2014 * external and enabled 2015 */ 2016 value = apic_read(APIC_LVT0); 2017 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2018 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2019 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2020 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2021 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 2022 apic_write(APIC_LVT0, value); 2023 } else { 2024 /* Disable LVT0 */ 2025 apic_write(APIC_LVT0, APIC_LVT_MASKED); 2026 } 2027 2028 /* 2029 * For LVT1 make it edge triggered, active high, 2030 * nmi and enabled 2031 */ 2032 value = apic_read(APIC_LVT1); 2033 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2034 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2035 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2036 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2037 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 2038 apic_write(APIC_LVT1, value); 2039 } 2040 2041 int generic_processor_info(int apicid, int version) 2042 { 2043 int cpu, max = nr_cpu_ids; 2044 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, 2045 phys_cpu_present_map); 2046 2047 /* 2048 * boot_cpu_physical_apicid is designed to have the apicid 2049 * returned by read_apic_id(), i.e, the apicid of the 2050 * currently booting-up processor. However, on some platforms, 2051 * it is temporarily modified by the apicid reported as BSP 2052 * through MP table. Concretely: 2053 * 2054 * - arch/x86/kernel/mpparse.c: MP_processor_info() 2055 * - arch/x86/mm/amdtopology.c: amd_numa_init() 2056 * 2057 * This function is executed with the modified 2058 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel 2059 * parameter doesn't work to disable APs on kdump 2nd kernel. 2060 * 2061 * Since fixing handling of boot_cpu_physical_apicid requires 2062 * another discussion and tests on each platform, we leave it 2063 * for now and here we use read_apic_id() directly in this 2064 * function, generic_processor_info(). 2065 */ 2066 if (disabled_cpu_apicid != BAD_APICID && 2067 disabled_cpu_apicid != read_apic_id() && 2068 disabled_cpu_apicid == apicid) { 2069 int thiscpu = num_processors + disabled_cpus; 2070 2071 pr_warning("APIC: Disabling requested cpu." 2072 " Processor %d/0x%x ignored.\n", 2073 thiscpu, apicid); 2074 2075 disabled_cpus++; 2076 return -ENODEV; 2077 } 2078 2079 /* 2080 * If boot cpu has not been detected yet, then only allow upto 2081 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu 2082 */ 2083 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && 2084 apicid != boot_cpu_physical_apicid) { 2085 int thiscpu = max + disabled_cpus - 1; 2086 2087 pr_warning( 2088 "ACPI: NR_CPUS/possible_cpus limit of %i almost" 2089 " reached. Keeping one slot for boot cpu." 2090 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2091 2092 disabled_cpus++; 2093 return -ENODEV; 2094 } 2095 2096 if (num_processors >= nr_cpu_ids) { 2097 int thiscpu = max + disabled_cpus; 2098 2099 pr_warning( 2100 "ACPI: NR_CPUS/possible_cpus limit of %i reached." 2101 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2102 2103 disabled_cpus++; 2104 return -EINVAL; 2105 } 2106 2107 num_processors++; 2108 if (apicid == boot_cpu_physical_apicid) { 2109 /* 2110 * x86_bios_cpu_apicid is required to have processors listed 2111 * in same order as logical cpu numbers. Hence the first 2112 * entry is BSP, and so on. 2113 * boot_cpu_init() already hold bit 0 in cpu_present_mask 2114 * for BSP. 2115 */ 2116 cpu = 0; 2117 } else 2118 cpu = cpumask_next_zero(-1, cpu_present_mask); 2119 2120 /* 2121 * Validate version 2122 */ 2123 if (version == 0x0) { 2124 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", 2125 cpu, apicid); 2126 version = 0x10; 2127 } 2128 apic_version[apicid] = version; 2129 2130 if (version != apic_version[boot_cpu_physical_apicid]) { 2131 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", 2132 apic_version[boot_cpu_physical_apicid], cpu, version); 2133 } 2134 2135 physid_set(apicid, phys_cpu_present_map); 2136 if (apicid > max_physical_apicid) 2137 max_physical_apicid = apicid; 2138 2139 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 2140 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 2141 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 2142 #endif 2143 #ifdef CONFIG_X86_32 2144 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 2145 apic->x86_32_early_logical_apicid(cpu); 2146 #endif 2147 set_cpu_possible(cpu, true); 2148 set_cpu_present(cpu, true); 2149 2150 return cpu; 2151 } 2152 2153 int hard_smp_processor_id(void) 2154 { 2155 return read_apic_id(); 2156 } 2157 2158 void default_init_apic_ldr(void) 2159 { 2160 unsigned long val; 2161 2162 apic_write(APIC_DFR, APIC_DFR_VALUE); 2163 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; 2164 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); 2165 apic_write(APIC_LDR, val); 2166 } 2167 2168 int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 2169 const struct cpumask *andmask, 2170 unsigned int *apicid) 2171 { 2172 unsigned int cpu; 2173 2174 for_each_cpu_and(cpu, cpumask, andmask) { 2175 if (cpumask_test_cpu(cpu, cpu_online_mask)) 2176 break; 2177 } 2178 2179 if (likely(cpu < nr_cpu_ids)) { 2180 *apicid = per_cpu(x86_cpu_to_apicid, cpu); 2181 return 0; 2182 } 2183 2184 return -EINVAL; 2185 } 2186 2187 /* 2188 * Override the generic EOI implementation with an optimized version. 2189 * Only called during early boot when only one CPU is active and with 2190 * interrupts disabled, so we know this does not race with actual APIC driver 2191 * use. 2192 */ 2193 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) 2194 { 2195 struct apic **drv; 2196 2197 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { 2198 /* Should happen once for each apic */ 2199 WARN_ON((*drv)->eoi_write == eoi_write); 2200 (*drv)->eoi_write = eoi_write; 2201 } 2202 } 2203 2204 static void __init apic_bsp_up_setup(void) 2205 { 2206 #ifdef CONFIG_X86_64 2207 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); 2208 #else 2209 /* 2210 * Hack: In case of kdump, after a crash, kernel might be booting 2211 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 2212 * might be zero if read from MP tables. Get it from LAPIC. 2213 */ 2214 # ifdef CONFIG_CRASH_DUMP 2215 boot_cpu_physical_apicid = read_apic_id(); 2216 # endif 2217 #endif 2218 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 2219 } 2220 2221 /** 2222 * apic_bsp_setup - Setup function for local apic and io-apic 2223 * @upmode: Force UP mode (for APIC_init_uniprocessor) 2224 * 2225 * Returns: 2226 * apic_id of BSP APIC 2227 */ 2228 int __init apic_bsp_setup(bool upmode) 2229 { 2230 int id; 2231 2232 connect_bsp_APIC(); 2233 if (upmode) 2234 apic_bsp_up_setup(); 2235 setup_local_APIC(); 2236 2237 if (x2apic_mode) 2238 id = apic_read(APIC_LDR); 2239 else 2240 id = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 2241 2242 enable_IO_APIC(); 2243 end_local_APIC_setup(); 2244 irq_remap_enable_fault_handling(); 2245 setup_IO_APIC(); 2246 /* Setup local timer */ 2247 x86_init.timers.setup_percpu_clockev(); 2248 return id; 2249 } 2250 2251 /* 2252 * This initializes the IO-APIC and APIC hardware if this is 2253 * a UP kernel. 2254 */ 2255 int __init APIC_init_uniprocessor(void) 2256 { 2257 if (disable_apic) { 2258 pr_info("Apic disabled\n"); 2259 return -1; 2260 } 2261 #ifdef CONFIG_X86_64 2262 if (!cpu_has_apic) { 2263 disable_apic = 1; 2264 pr_info("Apic disabled by BIOS\n"); 2265 return -1; 2266 } 2267 #else 2268 if (!smp_found_config && !cpu_has_apic) 2269 return -1; 2270 2271 /* 2272 * Complain if the BIOS pretends there is one. 2273 */ 2274 if (!cpu_has_apic && 2275 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 2276 pr_err("BIOS bug, local APIC 0x%x not detected!...\n", 2277 boot_cpu_physical_apicid); 2278 return -1; 2279 } 2280 #endif 2281 2282 if (!smp_found_config) 2283 disable_ioapic_support(); 2284 2285 default_setup_apic_routing(); 2286 verify_local_APIC(); 2287 apic_bsp_setup(true); 2288 return 0; 2289 } 2290 2291 #ifdef CONFIG_UP_LATE_INIT 2292 void __init up_late_init(void) 2293 { 2294 APIC_init_uniprocessor(); 2295 } 2296 #endif 2297 2298 /* 2299 * Power management 2300 */ 2301 #ifdef CONFIG_PM 2302 2303 static struct { 2304 /* 2305 * 'active' is true if the local APIC was enabled by us and 2306 * not the BIOS; this signifies that we are also responsible 2307 * for disabling it before entering apm/acpi suspend 2308 */ 2309 int active; 2310 /* r/w apic fields */ 2311 unsigned int apic_id; 2312 unsigned int apic_taskpri; 2313 unsigned int apic_ldr; 2314 unsigned int apic_dfr; 2315 unsigned int apic_spiv; 2316 unsigned int apic_lvtt; 2317 unsigned int apic_lvtpc; 2318 unsigned int apic_lvt0; 2319 unsigned int apic_lvt1; 2320 unsigned int apic_lvterr; 2321 unsigned int apic_tmict; 2322 unsigned int apic_tdcr; 2323 unsigned int apic_thmr; 2324 } apic_pm_state; 2325 2326 static int lapic_suspend(void) 2327 { 2328 unsigned long flags; 2329 int maxlvt; 2330 2331 if (!apic_pm_state.active) 2332 return 0; 2333 2334 maxlvt = lapic_get_maxlvt(); 2335 2336 apic_pm_state.apic_id = apic_read(APIC_ID); 2337 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2338 apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2339 apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2340 apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2341 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2342 if (maxlvt >= 4) 2343 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2344 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2345 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2346 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2347 apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2348 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 2349 #ifdef CONFIG_X86_THERMAL_VECTOR 2350 if (maxlvt >= 5) 2351 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2352 #endif 2353 2354 local_irq_save(flags); 2355 disable_local_APIC(); 2356 2357 irq_remapping_disable(); 2358 2359 local_irq_restore(flags); 2360 return 0; 2361 } 2362 2363 static void lapic_resume(void) 2364 { 2365 unsigned int l, h; 2366 unsigned long flags; 2367 int maxlvt; 2368 2369 if (!apic_pm_state.active) 2370 return; 2371 2372 local_irq_save(flags); 2373 2374 /* 2375 * IO-APIC and PIC have their own resume routines. 2376 * We just mask them here to make sure the interrupt 2377 * subsystem is completely quiet while we enable x2apic 2378 * and interrupt-remapping. 2379 */ 2380 mask_ioapic_entries(); 2381 legacy_pic->mask_all(); 2382 2383 if (x2apic_mode) { 2384 __x2apic_enable(); 2385 } else { 2386 /* 2387 * Make sure the APICBASE points to the right address 2388 * 2389 * FIXME! This will be wrong if we ever support suspend on 2390 * SMP! We'll need to do this as part of the CPU restore! 2391 */ 2392 if (boot_cpu_data.x86 >= 6) { 2393 rdmsr(MSR_IA32_APICBASE, l, h); 2394 l &= ~MSR_IA32_APICBASE_BASE; 2395 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2396 wrmsr(MSR_IA32_APICBASE, l, h); 2397 } 2398 } 2399 2400 maxlvt = lapic_get_maxlvt(); 2401 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2402 apic_write(APIC_ID, apic_pm_state.apic_id); 2403 apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2404 apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2405 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2406 apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2407 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2408 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2409 #if defined(CONFIG_X86_MCE_INTEL) 2410 if (maxlvt >= 5) 2411 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2412 #endif 2413 if (maxlvt >= 4) 2414 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2415 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2416 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2417 apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2418 apic_write(APIC_ESR, 0); 2419 apic_read(APIC_ESR); 2420 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2421 apic_write(APIC_ESR, 0); 2422 apic_read(APIC_ESR); 2423 2424 irq_remapping_reenable(x2apic_mode); 2425 2426 local_irq_restore(flags); 2427 } 2428 2429 /* 2430 * This device has no shutdown method - fully functioning local APICs 2431 * are needed on every CPU up until machine_halt/restart/poweroff. 2432 */ 2433 2434 static struct syscore_ops lapic_syscore_ops = { 2435 .resume = lapic_resume, 2436 .suspend = lapic_suspend, 2437 }; 2438 2439 static void apic_pm_activate(void) 2440 { 2441 apic_pm_state.active = 1; 2442 } 2443 2444 static int __init init_lapic_sysfs(void) 2445 { 2446 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2447 if (cpu_has_apic) 2448 register_syscore_ops(&lapic_syscore_ops); 2449 2450 return 0; 2451 } 2452 2453 /* local apic needs to resume before other devices access its registers. */ 2454 core_initcall(init_lapic_sysfs); 2455 2456 #else /* CONFIG_PM */ 2457 2458 static void apic_pm_activate(void) { } 2459 2460 #endif /* CONFIG_PM */ 2461 2462 #ifdef CONFIG_X86_64 2463 2464 static int multi_checked; 2465 static int multi; 2466 2467 static int set_multi(const struct dmi_system_id *d) 2468 { 2469 if (multi) 2470 return 0; 2471 pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2472 multi = 1; 2473 return 0; 2474 } 2475 2476 static const struct dmi_system_id multi_dmi_table[] = { 2477 { 2478 .callback = set_multi, 2479 .ident = "IBM System Summit2", 2480 .matches = { 2481 DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2482 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2483 }, 2484 }, 2485 {} 2486 }; 2487 2488 static void dmi_check_multi(void) 2489 { 2490 if (multi_checked) 2491 return; 2492 2493 dmi_check_system(multi_dmi_table); 2494 multi_checked = 1; 2495 } 2496 2497 /* 2498 * apic_is_clustered_box() -- Check if we can expect good TSC 2499 * 2500 * Thus far, the major user of this is IBM's Summit2 series: 2501 * Clustered boxes may have unsynced TSC problems if they are 2502 * multi-chassis. 2503 * Use DMI to check them 2504 */ 2505 int apic_is_clustered_box(void) 2506 { 2507 dmi_check_multi(); 2508 return multi; 2509 } 2510 #endif 2511 2512 /* 2513 * APIC command line parameters 2514 */ 2515 static int __init setup_disableapic(char *arg) 2516 { 2517 disable_apic = 1; 2518 setup_clear_cpu_cap(X86_FEATURE_APIC); 2519 return 0; 2520 } 2521 early_param("disableapic", setup_disableapic); 2522 2523 /* same as disableapic, for compatibility */ 2524 static int __init setup_nolapic(char *arg) 2525 { 2526 return setup_disableapic(arg); 2527 } 2528 early_param("nolapic", setup_nolapic); 2529 2530 static int __init parse_lapic_timer_c2_ok(char *arg) 2531 { 2532 local_apic_timer_c2_ok = 1; 2533 return 0; 2534 } 2535 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2536 2537 static int __init parse_disable_apic_timer(char *arg) 2538 { 2539 disable_apic_timer = 1; 2540 return 0; 2541 } 2542 early_param("noapictimer", parse_disable_apic_timer); 2543 2544 static int __init parse_nolapic_timer(char *arg) 2545 { 2546 disable_apic_timer = 1; 2547 return 0; 2548 } 2549 early_param("nolapic_timer", parse_nolapic_timer); 2550 2551 static int __init apic_set_verbosity(char *arg) 2552 { 2553 if (!arg) { 2554 #ifdef CONFIG_X86_64 2555 skip_ioapic_setup = 0; 2556 return 0; 2557 #endif 2558 return -EINVAL; 2559 } 2560 2561 if (strcmp("debug", arg) == 0) 2562 apic_verbosity = APIC_DEBUG; 2563 else if (strcmp("verbose", arg) == 0) 2564 apic_verbosity = APIC_VERBOSE; 2565 else { 2566 pr_warning("APIC Verbosity level %s not recognised" 2567 " use apic=verbose or apic=debug\n", arg); 2568 return -EINVAL; 2569 } 2570 2571 return 0; 2572 } 2573 early_param("apic", apic_set_verbosity); 2574 2575 static int __init lapic_insert_resource(void) 2576 { 2577 if (!apic_phys) 2578 return -1; 2579 2580 /* Put local APIC into the resource map. */ 2581 lapic_resource.start = apic_phys; 2582 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2583 insert_resource(&iomem_resource, &lapic_resource); 2584 2585 return 0; 2586 } 2587 2588 /* 2589 * need call insert after e820_reserve_resources() 2590 * that is using request_resource 2591 */ 2592 late_initcall(lapic_insert_resource); 2593 2594 static int __init apic_set_disabled_cpu_apicid(char *arg) 2595 { 2596 if (!arg || !get_option(&arg, &disabled_cpu_apicid)) 2597 return -EINVAL; 2598 2599 return 0; 2600 } 2601 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); 2602