1 /* 2 * Local APIC handling, local APIC timers 3 * 4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5 * 6 * Fixes 7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8 * thanks to Eric Gilmore 9 * and Rolf G. Tews 10 * for testing these extensively. 11 * Maciej W. Rozycki : Various updates and fixes. 12 * Mikael Pettersson : Power Management for UP-APIC. 13 * Pavel Machek and 14 * Mikael Pettersson : PM converted to driver model. 15 */ 16 17 #include <linux/perf_event.h> 18 #include <linux/kernel_stat.h> 19 #include <linux/mc146818rtc.h> 20 #include <linux/acpi_pmtmr.h> 21 #include <linux/clockchips.h> 22 #include <linux/interrupt.h> 23 #include <linux/bootmem.h> 24 #include <linux/ftrace.h> 25 #include <linux/ioport.h> 26 #include <linux/module.h> 27 #include <linux/sysdev.h> 28 #include <linux/delay.h> 29 #include <linux/timex.h> 30 #include <linux/dmar.h> 31 #include <linux/init.h> 32 #include <linux/cpu.h> 33 #include <linux/dmi.h> 34 #include <linux/smp.h> 35 #include <linux/mm.h> 36 37 #include <asm/perf_event.h> 38 #include <asm/x86_init.h> 39 #include <asm/pgalloc.h> 40 #include <asm/atomic.h> 41 #include <asm/mpspec.h> 42 #include <asm/i8253.h> 43 #include <asm/i8259.h> 44 #include <asm/proto.h> 45 #include <asm/apic.h> 46 #include <asm/io_apic.h> 47 #include <asm/desc.h> 48 #include <asm/hpet.h> 49 #include <asm/idle.h> 50 #include <asm/mtrr.h> 51 #include <asm/smp.h> 52 #include <asm/mce.h> 53 #include <asm/tsc.h> 54 #include <asm/hypervisor.h> 55 56 unsigned int num_processors; 57 58 unsigned disabled_cpus __cpuinitdata; 59 60 /* Processor that is doing the boot up */ 61 unsigned int boot_cpu_physical_apicid = -1U; 62 63 /* 64 * The highest APIC ID seen during enumeration. 65 */ 66 unsigned int max_physical_apicid; 67 68 /* 69 * Bitmask of physically existing CPUs: 70 */ 71 physid_mask_t phys_cpu_present_map; 72 73 /* 74 * Map cpu index to physical APIC ID 75 */ 76 DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID); 77 DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID); 78 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 79 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 80 81 #ifdef CONFIG_X86_32 82 83 /* 84 * On x86_32, the mapping between cpu and logical apicid may vary 85 * depending on apic in use. The following early percpu variable is 86 * used for the mapping. This is where the behaviors of x86_64 and 32 87 * actually diverge. Let's keep it ugly for now. 88 */ 89 DEFINE_EARLY_PER_CPU(int, x86_cpu_to_logical_apicid, BAD_APICID); 90 91 /* 92 * Knob to control our willingness to enable the local APIC. 93 * 94 * +1=force-enable 95 */ 96 static int force_enable_local_apic __initdata; 97 /* 98 * APIC command line parameters 99 */ 100 static int __init parse_lapic(char *arg) 101 { 102 force_enable_local_apic = 1; 103 return 0; 104 } 105 early_param("lapic", parse_lapic); 106 /* Local APIC was disabled by the BIOS and enabled by the kernel */ 107 static int enabled_via_apicbase; 108 109 /* 110 * Handle interrupt mode configuration register (IMCR). 111 * This register controls whether the interrupt signals 112 * that reach the BSP come from the master PIC or from the 113 * local APIC. Before entering Symmetric I/O Mode, either 114 * the BIOS or the operating system must switch out of 115 * PIC Mode by changing the IMCR. 116 */ 117 static inline void imcr_pic_to_apic(void) 118 { 119 /* select IMCR register */ 120 outb(0x70, 0x22); 121 /* NMI and 8259 INTR go through APIC */ 122 outb(0x01, 0x23); 123 } 124 125 static inline void imcr_apic_to_pic(void) 126 { 127 /* select IMCR register */ 128 outb(0x70, 0x22); 129 /* NMI and 8259 INTR go directly to BSP */ 130 outb(0x00, 0x23); 131 } 132 #endif 133 134 #ifdef CONFIG_X86_64 135 static int apic_calibrate_pmtmr __initdata; 136 static __init int setup_apicpmtimer(char *s) 137 { 138 apic_calibrate_pmtmr = 1; 139 notsc_setup(NULL); 140 return 0; 141 } 142 __setup("apicpmtimer", setup_apicpmtimer); 143 #endif 144 145 int x2apic_mode; 146 #ifdef CONFIG_X86_X2APIC 147 /* x2apic enabled before OS handover */ 148 static int x2apic_preenabled; 149 static __init int setup_nox2apic(char *str) 150 { 151 if (x2apic_enabled()) { 152 pr_warning("Bios already enabled x2apic, " 153 "can't enforce nox2apic"); 154 return 0; 155 } 156 157 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 158 return 0; 159 } 160 early_param("nox2apic", setup_nox2apic); 161 #endif 162 163 unsigned long mp_lapic_addr; 164 int disable_apic; 165 /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 166 static int disable_apic_timer __initdata; 167 /* Local APIC timer works in C2 */ 168 int local_apic_timer_c2_ok; 169 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 170 171 int first_system_vector = 0xfe; 172 173 /* 174 * Debug level, exported for io_apic.c 175 */ 176 unsigned int apic_verbosity; 177 178 int pic_mode; 179 180 /* Have we found an MP table */ 181 int smp_found_config; 182 183 static struct resource lapic_resource = { 184 .name = "Local APIC", 185 .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 186 }; 187 188 static unsigned int calibration_result; 189 190 static void apic_pm_activate(void); 191 192 static unsigned long apic_phys; 193 194 /* 195 * Get the LAPIC version 196 */ 197 static inline int lapic_get_version(void) 198 { 199 return GET_APIC_VERSION(apic_read(APIC_LVR)); 200 } 201 202 /* 203 * Check, if the APIC is integrated or a separate chip 204 */ 205 static inline int lapic_is_integrated(void) 206 { 207 #ifdef CONFIG_X86_64 208 return 1; 209 #else 210 return APIC_INTEGRATED(lapic_get_version()); 211 #endif 212 } 213 214 /* 215 * Check, whether this is a modern or a first generation APIC 216 */ 217 static int modern_apic(void) 218 { 219 /* AMD systems use old APIC versions, so check the CPU */ 220 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 221 boot_cpu_data.x86 >= 0xf) 222 return 1; 223 return lapic_get_version() >= 0x14; 224 } 225 226 /* 227 * right after this call apic become NOOP driven 228 * so apic->write/read doesn't do anything 229 */ 230 static void __init apic_disable(void) 231 { 232 pr_info("APIC: switched to apic NOOP\n"); 233 apic = &apic_noop; 234 } 235 236 void native_apic_wait_icr_idle(void) 237 { 238 while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 239 cpu_relax(); 240 } 241 242 u32 native_safe_apic_wait_icr_idle(void) 243 { 244 u32 send_status; 245 int timeout; 246 247 timeout = 0; 248 do { 249 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 250 if (!send_status) 251 break; 252 udelay(100); 253 } while (timeout++ < 1000); 254 255 return send_status; 256 } 257 258 void native_apic_icr_write(u32 low, u32 id) 259 { 260 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 261 apic_write(APIC_ICR, low); 262 } 263 264 u64 native_apic_icr_read(void) 265 { 266 u32 icr1, icr2; 267 268 icr2 = apic_read(APIC_ICR2); 269 icr1 = apic_read(APIC_ICR); 270 271 return icr1 | ((u64)icr2 << 32); 272 } 273 274 #ifdef CONFIG_X86_32 275 /** 276 * get_physical_broadcast - Get number of physical broadcast IDs 277 */ 278 int get_physical_broadcast(void) 279 { 280 return modern_apic() ? 0xff : 0xf; 281 } 282 #endif 283 284 /** 285 * lapic_get_maxlvt - get the maximum number of local vector table entries 286 */ 287 int lapic_get_maxlvt(void) 288 { 289 unsigned int v; 290 291 v = apic_read(APIC_LVR); 292 /* 293 * - we always have APIC integrated on 64bit mode 294 * - 82489DXs do not report # of LVT entries 295 */ 296 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; 297 } 298 299 /* 300 * Local APIC timer 301 */ 302 303 /* Clock divisor */ 304 #define APIC_DIVISOR 16 305 306 /* 307 * This function sets up the local APIC timer, with a timeout of 308 * 'clocks' APIC bus clock. During calibration we actually call 309 * this function twice on the boot CPU, once with a bogus timeout 310 * value, second time for real. The other (noncalibrating) CPUs 311 * call this function only once, with the real, calibrated value. 312 * 313 * We do reads before writes even if unnecessary, to get around the 314 * P5 APIC double write bug. 315 */ 316 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 317 { 318 unsigned int lvtt_value, tmp_value; 319 320 lvtt_value = LOCAL_TIMER_VECTOR; 321 if (!oneshot) 322 lvtt_value |= APIC_LVT_TIMER_PERIODIC; 323 if (!lapic_is_integrated()) 324 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 325 326 if (!irqen) 327 lvtt_value |= APIC_LVT_MASKED; 328 329 apic_write(APIC_LVTT, lvtt_value); 330 331 /* 332 * Divide PICLK by 16 333 */ 334 tmp_value = apic_read(APIC_TDCR); 335 apic_write(APIC_TDCR, 336 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 337 APIC_TDR_DIV_16); 338 339 if (!oneshot) 340 apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 341 } 342 343 /* 344 * Setup extended LVT, AMD specific 345 * 346 * Software should use the LVT offsets the BIOS provides. The offsets 347 * are determined by the subsystems using it like those for MCE 348 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 349 * are supported. Beginning with family 10h at least 4 offsets are 350 * available. 351 * 352 * Since the offsets must be consistent for all cores, we keep track 353 * of the LVT offsets in software and reserve the offset for the same 354 * vector also to be used on other cores. An offset is freed by 355 * setting the entry to APIC_EILVT_MASKED. 356 * 357 * If the BIOS is right, there should be no conflicts. Otherwise a 358 * "[Firmware Bug]: ..." error message is generated. However, if 359 * software does not properly determines the offsets, it is not 360 * necessarily a BIOS bug. 361 */ 362 363 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 364 365 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 366 { 367 return (old & APIC_EILVT_MASKED) 368 || (new == APIC_EILVT_MASKED) 369 || ((new & ~APIC_EILVT_MASKED) == old); 370 } 371 372 static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 373 { 374 unsigned int rsvd; /* 0: uninitialized */ 375 376 if (offset >= APIC_EILVT_NR_MAX) 377 return ~0; 378 379 rsvd = atomic_read(&eilvt_offsets[offset]) & ~APIC_EILVT_MASKED; 380 do { 381 if (rsvd && 382 !eilvt_entry_is_changeable(rsvd, new)) 383 /* may not change if vectors are different */ 384 return rsvd; 385 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 386 } while (rsvd != new); 387 388 return new; 389 } 390 391 /* 392 * If mask=1, the LVT entry does not generate interrupts while mask=0 393 * enables the vector. See also the BKDGs. 394 */ 395 396 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 397 { 398 unsigned long reg = APIC_EILVTn(offset); 399 unsigned int new, old, reserved; 400 401 new = (mask << 16) | (msg_type << 8) | vector; 402 old = apic_read(reg); 403 reserved = reserve_eilvt_offset(offset, new); 404 405 if (reserved != new) { 406 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 407 "vector 0x%x, but the register is already in use for " 408 "vector 0x%x on another cpu\n", 409 smp_processor_id(), reg, offset, new, reserved); 410 return -EINVAL; 411 } 412 413 if (!eilvt_entry_is_changeable(old, new)) { 414 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 415 "vector 0x%x, but the register is already in use for " 416 "vector 0x%x on this cpu\n", 417 smp_processor_id(), reg, offset, new, old); 418 return -EBUSY; 419 } 420 421 apic_write(reg, new); 422 423 return 0; 424 } 425 EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 426 427 /* 428 * Program the next event, relative to now 429 */ 430 static int lapic_next_event(unsigned long delta, 431 struct clock_event_device *evt) 432 { 433 apic_write(APIC_TMICT, delta); 434 return 0; 435 } 436 437 /* 438 * Setup the lapic timer in periodic or oneshot mode 439 */ 440 static void lapic_timer_setup(enum clock_event_mode mode, 441 struct clock_event_device *evt) 442 { 443 unsigned long flags; 444 unsigned int v; 445 446 /* Lapic used as dummy for broadcast ? */ 447 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 448 return; 449 450 local_irq_save(flags); 451 452 switch (mode) { 453 case CLOCK_EVT_MODE_PERIODIC: 454 case CLOCK_EVT_MODE_ONESHOT: 455 __setup_APIC_LVTT(calibration_result, 456 mode != CLOCK_EVT_MODE_PERIODIC, 1); 457 break; 458 case CLOCK_EVT_MODE_UNUSED: 459 case CLOCK_EVT_MODE_SHUTDOWN: 460 v = apic_read(APIC_LVTT); 461 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 462 apic_write(APIC_LVTT, v); 463 apic_write(APIC_TMICT, 0); 464 break; 465 case CLOCK_EVT_MODE_RESUME: 466 /* Nothing to do here */ 467 break; 468 } 469 470 local_irq_restore(flags); 471 } 472 473 /* 474 * Local APIC timer broadcast function 475 */ 476 static void lapic_timer_broadcast(const struct cpumask *mask) 477 { 478 #ifdef CONFIG_SMP 479 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 480 #endif 481 } 482 483 484 /* 485 * The local apic timer can be used for any function which is CPU local. 486 */ 487 static struct clock_event_device lapic_clockevent = { 488 .name = "lapic", 489 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT 490 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, 491 .shift = 32, 492 .set_mode = lapic_timer_setup, 493 .set_next_event = lapic_next_event, 494 .broadcast = lapic_timer_broadcast, 495 .rating = 100, 496 .irq = -1, 497 }; 498 static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 499 500 /* 501 * Setup the local APIC timer for this CPU. Copy the initialized values 502 * of the boot CPU and register the clock event in the framework. 503 */ 504 static void __cpuinit setup_APIC_timer(void) 505 { 506 struct clock_event_device *levt = &__get_cpu_var(lapic_events); 507 508 if (cpu_has(__this_cpu_ptr(&cpu_info), X86_FEATURE_ARAT)) { 509 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 510 /* Make LAPIC timer preferrable over percpu HPET */ 511 lapic_clockevent.rating = 150; 512 } 513 514 memcpy(levt, &lapic_clockevent, sizeof(*levt)); 515 levt->cpumask = cpumask_of(smp_processor_id()); 516 517 clockevents_register_device(levt); 518 } 519 520 /* 521 * In this functions we calibrate APIC bus clocks to the external timer. 522 * 523 * We want to do the calibration only once since we want to have local timer 524 * irqs syncron. CPUs connected by the same APIC bus have the very same bus 525 * frequency. 526 * 527 * This was previously done by reading the PIT/HPET and waiting for a wrap 528 * around to find out, that a tick has elapsed. I have a box, where the PIT 529 * readout is broken, so it never gets out of the wait loop again. This was 530 * also reported by others. 531 * 532 * Monitoring the jiffies value is inaccurate and the clockevents 533 * infrastructure allows us to do a simple substitution of the interrupt 534 * handler. 535 * 536 * The calibration routine also uses the pm_timer when possible, as the PIT 537 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 538 * back to normal later in the boot process). 539 */ 540 541 #define LAPIC_CAL_LOOPS (HZ/10) 542 543 static __initdata int lapic_cal_loops = -1; 544 static __initdata long lapic_cal_t1, lapic_cal_t2; 545 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 546 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 547 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 548 549 /* 550 * Temporary interrupt handler. 551 */ 552 static void __init lapic_cal_handler(struct clock_event_device *dev) 553 { 554 unsigned long long tsc = 0; 555 long tapic = apic_read(APIC_TMCCT); 556 unsigned long pm = acpi_pm_read_early(); 557 558 if (cpu_has_tsc) 559 rdtscll(tsc); 560 561 switch (lapic_cal_loops++) { 562 case 0: 563 lapic_cal_t1 = tapic; 564 lapic_cal_tsc1 = tsc; 565 lapic_cal_pm1 = pm; 566 lapic_cal_j1 = jiffies; 567 break; 568 569 case LAPIC_CAL_LOOPS: 570 lapic_cal_t2 = tapic; 571 lapic_cal_tsc2 = tsc; 572 if (pm < lapic_cal_pm1) 573 pm += ACPI_PM_OVRRUN; 574 lapic_cal_pm2 = pm; 575 lapic_cal_j2 = jiffies; 576 break; 577 } 578 } 579 580 static int __init 581 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 582 { 583 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 584 const long pm_thresh = pm_100ms / 100; 585 unsigned long mult; 586 u64 res; 587 588 #ifndef CONFIG_X86_PM_TIMER 589 return -1; 590 #endif 591 592 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 593 594 /* Check, if the PM timer is available */ 595 if (!deltapm) 596 return -1; 597 598 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 599 600 if (deltapm > (pm_100ms - pm_thresh) && 601 deltapm < (pm_100ms + pm_thresh)) { 602 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 603 return 0; 604 } 605 606 res = (((u64)deltapm) * mult) >> 22; 607 do_div(res, 1000000); 608 pr_warning("APIC calibration not consistent " 609 "with PM-Timer: %ldms instead of 100ms\n",(long)res); 610 611 /* Correct the lapic counter value */ 612 res = (((u64)(*delta)) * pm_100ms); 613 do_div(res, deltapm); 614 pr_info("APIC delta adjusted to PM-Timer: " 615 "%lu (%ld)\n", (unsigned long)res, *delta); 616 *delta = (long)res; 617 618 /* Correct the tsc counter value */ 619 if (cpu_has_tsc) { 620 res = (((u64)(*deltatsc)) * pm_100ms); 621 do_div(res, deltapm); 622 apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 623 "PM-Timer: %lu (%ld)\n", 624 (unsigned long)res, *deltatsc); 625 *deltatsc = (long)res; 626 } 627 628 return 0; 629 } 630 631 static int __init calibrate_APIC_clock(void) 632 { 633 struct clock_event_device *levt = &__get_cpu_var(lapic_events); 634 void (*real_handler)(struct clock_event_device *dev); 635 unsigned long deltaj; 636 long delta, deltatsc; 637 int pm_referenced = 0; 638 639 local_irq_disable(); 640 641 /* Replace the global interrupt handler */ 642 real_handler = global_clock_event->event_handler; 643 global_clock_event->event_handler = lapic_cal_handler; 644 645 /* 646 * Setup the APIC counter to maximum. There is no way the lapic 647 * can underflow in the 100ms detection time frame 648 */ 649 __setup_APIC_LVTT(0xffffffff, 0, 0); 650 651 /* Let the interrupts run */ 652 local_irq_enable(); 653 654 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 655 cpu_relax(); 656 657 local_irq_disable(); 658 659 /* Restore the real event handler */ 660 global_clock_event->event_handler = real_handler; 661 662 /* Build delta t1-t2 as apic timer counts down */ 663 delta = lapic_cal_t1 - lapic_cal_t2; 664 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 665 666 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 667 668 /* we trust the PM based calibration if possible */ 669 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 670 &delta, &deltatsc); 671 672 /* Calculate the scaled math multiplication factor */ 673 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 674 lapic_clockevent.shift); 675 lapic_clockevent.max_delta_ns = 676 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 677 lapic_clockevent.min_delta_ns = 678 clockevent_delta2ns(0xF, &lapic_clockevent); 679 680 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 681 682 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 683 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 684 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 685 calibration_result); 686 687 if (cpu_has_tsc) { 688 apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 689 "%ld.%04ld MHz.\n", 690 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 691 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 692 } 693 694 apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 695 "%u.%04u MHz.\n", 696 calibration_result / (1000000 / HZ), 697 calibration_result % (1000000 / HZ)); 698 699 /* 700 * Do a sanity check on the APIC calibration result 701 */ 702 if (calibration_result < (1000000 / HZ)) { 703 local_irq_enable(); 704 pr_warning("APIC frequency too slow, disabling apic timer\n"); 705 return -1; 706 } 707 708 levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 709 710 /* 711 * PM timer calibration failed or not turned on 712 * so lets try APIC timer based calibration 713 */ 714 if (!pm_referenced) { 715 apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 716 717 /* 718 * Setup the apic timer manually 719 */ 720 levt->event_handler = lapic_cal_handler; 721 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); 722 lapic_cal_loops = -1; 723 724 /* Let the interrupts run */ 725 local_irq_enable(); 726 727 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 728 cpu_relax(); 729 730 /* Stop the lapic timer */ 731 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); 732 733 /* Jiffies delta */ 734 deltaj = lapic_cal_j2 - lapic_cal_j1; 735 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 736 737 /* Check, if the jiffies result is consistent */ 738 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 739 apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 740 else 741 levt->features |= CLOCK_EVT_FEAT_DUMMY; 742 } else 743 local_irq_enable(); 744 745 if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 746 pr_warning("APIC timer disabled due to verification failure\n"); 747 return -1; 748 } 749 750 return 0; 751 } 752 753 /* 754 * Setup the boot APIC 755 * 756 * Calibrate and verify the result. 757 */ 758 void __init setup_boot_APIC_clock(void) 759 { 760 /* 761 * The local apic timer can be disabled via the kernel 762 * commandline or from the CPU detection code. Register the lapic 763 * timer as a dummy clock event source on SMP systems, so the 764 * broadcast mechanism is used. On UP systems simply ignore it. 765 */ 766 if (disable_apic_timer) { 767 pr_info("Disabling APIC timer\n"); 768 /* No broadcast on UP ! */ 769 if (num_possible_cpus() > 1) { 770 lapic_clockevent.mult = 1; 771 setup_APIC_timer(); 772 } 773 return; 774 } 775 776 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 777 "calibrating APIC timer ...\n"); 778 779 if (calibrate_APIC_clock()) { 780 /* No broadcast on UP ! */ 781 if (num_possible_cpus() > 1) 782 setup_APIC_timer(); 783 return; 784 } 785 786 /* 787 * If nmi_watchdog is set to IO_APIC, we need the 788 * PIT/HPET going. Otherwise register lapic as a dummy 789 * device. 790 */ 791 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 792 793 /* Setup the lapic or request the broadcast */ 794 setup_APIC_timer(); 795 } 796 797 void __cpuinit setup_secondary_APIC_clock(void) 798 { 799 setup_APIC_timer(); 800 } 801 802 /* 803 * The guts of the apic timer interrupt 804 */ 805 static void local_apic_timer_interrupt(void) 806 { 807 int cpu = smp_processor_id(); 808 struct clock_event_device *evt = &per_cpu(lapic_events, cpu); 809 810 /* 811 * Normally we should not be here till LAPIC has been initialized but 812 * in some cases like kdump, its possible that there is a pending LAPIC 813 * timer interrupt from previous kernel's context and is delivered in 814 * new kernel the moment interrupts are enabled. 815 * 816 * Interrupts are enabled early and LAPIC is setup much later, hence 817 * its possible that when we get here evt->event_handler is NULL. 818 * Check for event_handler being NULL and discard the interrupt as 819 * spurious. 820 */ 821 if (!evt->event_handler) { 822 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); 823 /* Switch it off */ 824 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); 825 return; 826 } 827 828 /* 829 * the NMI deadlock-detector uses this. 830 */ 831 inc_irq_stat(apic_timer_irqs); 832 833 evt->event_handler(evt); 834 } 835 836 /* 837 * Local APIC timer interrupt. This is the most natural way for doing 838 * local interrupts, but local timer interrupts can be emulated by 839 * broadcast interrupts too. [in case the hw doesn't support APIC timers] 840 * 841 * [ if a single-CPU system runs an SMP kernel then we call the local 842 * interrupt as well. Thus we cannot inline the local irq ... ] 843 */ 844 void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 845 { 846 struct pt_regs *old_regs = set_irq_regs(regs); 847 848 /* 849 * NOTE! We'd better ACK the irq immediately, 850 * because timer handling can be slow. 851 */ 852 ack_APIC_irq(); 853 /* 854 * update_process_times() expects us to have done irq_enter(). 855 * Besides, if we don't timer interrupts ignore the global 856 * interrupt lock, which is the WrongThing (tm) to do. 857 */ 858 exit_idle(); 859 irq_enter(); 860 local_apic_timer_interrupt(); 861 irq_exit(); 862 863 set_irq_regs(old_regs); 864 } 865 866 int setup_profiling_timer(unsigned int multiplier) 867 { 868 return -EINVAL; 869 } 870 871 /* 872 * Local APIC start and shutdown 873 */ 874 875 /** 876 * clear_local_APIC - shutdown the local APIC 877 * 878 * This is called, when a CPU is disabled and before rebooting, so the state of 879 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 880 * leftovers during boot. 881 */ 882 void clear_local_APIC(void) 883 { 884 int maxlvt; 885 u32 v; 886 887 /* APIC hasn't been mapped yet */ 888 if (!x2apic_mode && !apic_phys) 889 return; 890 891 maxlvt = lapic_get_maxlvt(); 892 /* 893 * Masking an LVT entry can trigger a local APIC error 894 * if the vector is zero. Mask LVTERR first to prevent this. 895 */ 896 if (maxlvt >= 3) { 897 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 898 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 899 } 900 /* 901 * Careful: we have to set masks only first to deassert 902 * any level-triggered sources. 903 */ 904 v = apic_read(APIC_LVTT); 905 apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 906 v = apic_read(APIC_LVT0); 907 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 908 v = apic_read(APIC_LVT1); 909 apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 910 if (maxlvt >= 4) { 911 v = apic_read(APIC_LVTPC); 912 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 913 } 914 915 /* lets not touch this if we didn't frob it */ 916 #ifdef CONFIG_X86_THERMAL_VECTOR 917 if (maxlvt >= 5) { 918 v = apic_read(APIC_LVTTHMR); 919 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 920 } 921 #endif 922 #ifdef CONFIG_X86_MCE_INTEL 923 if (maxlvt >= 6) { 924 v = apic_read(APIC_LVTCMCI); 925 if (!(v & APIC_LVT_MASKED)) 926 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 927 } 928 #endif 929 930 /* 931 * Clean APIC state for other OSs: 932 */ 933 apic_write(APIC_LVTT, APIC_LVT_MASKED); 934 apic_write(APIC_LVT0, APIC_LVT_MASKED); 935 apic_write(APIC_LVT1, APIC_LVT_MASKED); 936 if (maxlvt >= 3) 937 apic_write(APIC_LVTERR, APIC_LVT_MASKED); 938 if (maxlvt >= 4) 939 apic_write(APIC_LVTPC, APIC_LVT_MASKED); 940 941 /* Integrated APIC (!82489DX) ? */ 942 if (lapic_is_integrated()) { 943 if (maxlvt > 3) 944 /* Clear ESR due to Pentium errata 3AP and 11AP */ 945 apic_write(APIC_ESR, 0); 946 apic_read(APIC_ESR); 947 } 948 } 949 950 /** 951 * disable_local_APIC - clear and disable the local APIC 952 */ 953 void disable_local_APIC(void) 954 { 955 unsigned int value; 956 957 /* APIC hasn't been mapped yet */ 958 if (!x2apic_mode && !apic_phys) 959 return; 960 961 clear_local_APIC(); 962 963 /* 964 * Disable APIC (implies clearing of registers 965 * for 82489DX!). 966 */ 967 value = apic_read(APIC_SPIV); 968 value &= ~APIC_SPIV_APIC_ENABLED; 969 apic_write(APIC_SPIV, value); 970 971 #ifdef CONFIG_X86_32 972 /* 973 * When LAPIC was disabled by the BIOS and enabled by the kernel, 974 * restore the disabled state. 975 */ 976 if (enabled_via_apicbase) { 977 unsigned int l, h; 978 979 rdmsr(MSR_IA32_APICBASE, l, h); 980 l &= ~MSR_IA32_APICBASE_ENABLE; 981 wrmsr(MSR_IA32_APICBASE, l, h); 982 } 983 #endif 984 } 985 986 /* 987 * If Linux enabled the LAPIC against the BIOS default disable it down before 988 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 989 * not power-off. Additionally clear all LVT entries before disable_local_APIC 990 * for the case where Linux didn't enable the LAPIC. 991 */ 992 void lapic_shutdown(void) 993 { 994 unsigned long flags; 995 996 if (!cpu_has_apic && !apic_from_smp_config()) 997 return; 998 999 local_irq_save(flags); 1000 1001 #ifdef CONFIG_X86_32 1002 if (!enabled_via_apicbase) 1003 clear_local_APIC(); 1004 else 1005 #endif 1006 disable_local_APIC(); 1007 1008 1009 local_irq_restore(flags); 1010 } 1011 1012 /* 1013 * This is to verify that we're looking at a real local APIC. 1014 * Check these against your board if the CPUs aren't getting 1015 * started for no apparent reason. 1016 */ 1017 int __init verify_local_APIC(void) 1018 { 1019 unsigned int reg0, reg1; 1020 1021 /* 1022 * The version register is read-only in a real APIC. 1023 */ 1024 reg0 = apic_read(APIC_LVR); 1025 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); 1026 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); 1027 reg1 = apic_read(APIC_LVR); 1028 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); 1029 1030 /* 1031 * The two version reads above should print the same 1032 * numbers. If the second one is different, then we 1033 * poke at a non-APIC. 1034 */ 1035 if (reg1 != reg0) 1036 return 0; 1037 1038 /* 1039 * Check if the version looks reasonably. 1040 */ 1041 reg1 = GET_APIC_VERSION(reg0); 1042 if (reg1 == 0x00 || reg1 == 0xff) 1043 return 0; 1044 reg1 = lapic_get_maxlvt(); 1045 if (reg1 < 0x02 || reg1 == 0xff) 1046 return 0; 1047 1048 /* 1049 * The ID register is read/write in a real APIC. 1050 */ 1051 reg0 = apic_read(APIC_ID); 1052 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); 1053 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask); 1054 reg1 = apic_read(APIC_ID); 1055 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); 1056 apic_write(APIC_ID, reg0); 1057 if (reg1 != (reg0 ^ apic->apic_id_mask)) 1058 return 0; 1059 1060 /* 1061 * The next two are just to see if we have sane values. 1062 * They're only really relevant if we're in Virtual Wire 1063 * compatibility mode, but most boxes are anymore. 1064 */ 1065 reg0 = apic_read(APIC_LVT0); 1066 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); 1067 reg1 = apic_read(APIC_LVT1); 1068 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); 1069 1070 return 1; 1071 } 1072 1073 /** 1074 * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1075 */ 1076 void __init sync_Arb_IDs(void) 1077 { 1078 /* 1079 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1080 * needed on AMD. 1081 */ 1082 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1083 return; 1084 1085 /* 1086 * Wait for idle. 1087 */ 1088 apic_wait_icr_idle(); 1089 1090 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1091 apic_write(APIC_ICR, APIC_DEST_ALLINC | 1092 APIC_INT_LEVELTRIG | APIC_DM_INIT); 1093 } 1094 1095 /* 1096 * An initial setup of the virtual wire mode. 1097 */ 1098 void __init init_bsp_APIC(void) 1099 { 1100 unsigned int value; 1101 1102 /* 1103 * Don't do the setup now if we have a SMP BIOS as the 1104 * through-I/O-APIC virtual wire mode might be active. 1105 */ 1106 if (smp_found_config || !cpu_has_apic) 1107 return; 1108 1109 /* 1110 * Do not trust the local APIC being empty at bootup. 1111 */ 1112 clear_local_APIC(); 1113 1114 /* 1115 * Enable APIC. 1116 */ 1117 value = apic_read(APIC_SPIV); 1118 value &= ~APIC_VECTOR_MASK; 1119 value |= APIC_SPIV_APIC_ENABLED; 1120 1121 #ifdef CONFIG_X86_32 1122 /* This bit is reserved on P4/Xeon and should be cleared */ 1123 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1124 (boot_cpu_data.x86 == 15)) 1125 value &= ~APIC_SPIV_FOCUS_DISABLED; 1126 else 1127 #endif 1128 value |= APIC_SPIV_FOCUS_DISABLED; 1129 value |= SPURIOUS_APIC_VECTOR; 1130 apic_write(APIC_SPIV, value); 1131 1132 /* 1133 * Set up the virtual wire mode. 1134 */ 1135 apic_write(APIC_LVT0, APIC_DM_EXTINT); 1136 value = APIC_DM_NMI; 1137 if (!lapic_is_integrated()) /* 82489DX */ 1138 value |= APIC_LVT_LEVEL_TRIGGER; 1139 apic_write(APIC_LVT1, value); 1140 } 1141 1142 static void __cpuinit lapic_setup_esr(void) 1143 { 1144 unsigned int oldvalue, value, maxlvt; 1145 1146 if (!lapic_is_integrated()) { 1147 pr_info("No ESR for 82489DX.\n"); 1148 return; 1149 } 1150 1151 if (apic->disable_esr) { 1152 /* 1153 * Something untraceable is creating bad interrupts on 1154 * secondary quads ... for the moment, just leave the 1155 * ESR disabled - we can't do anything useful with the 1156 * errors anyway - mbligh 1157 */ 1158 pr_info("Leaving ESR disabled.\n"); 1159 return; 1160 } 1161 1162 maxlvt = lapic_get_maxlvt(); 1163 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1164 apic_write(APIC_ESR, 0); 1165 oldvalue = apic_read(APIC_ESR); 1166 1167 /* enables sending errors */ 1168 value = ERROR_APIC_VECTOR; 1169 apic_write(APIC_LVTERR, value); 1170 1171 /* 1172 * spec says clear errors after enabling vector. 1173 */ 1174 if (maxlvt > 3) 1175 apic_write(APIC_ESR, 0); 1176 value = apic_read(APIC_ESR); 1177 if (value != oldvalue) 1178 apic_printk(APIC_VERBOSE, "ESR value before enabling " 1179 "vector: 0x%08x after: 0x%08x\n", 1180 oldvalue, value); 1181 } 1182 1183 /** 1184 * setup_local_APIC - setup the local APIC 1185 * 1186 * Used to setup local APIC while initializing BSP or bringin up APs. 1187 * Always called with preemption disabled. 1188 */ 1189 void __cpuinit setup_local_APIC(void) 1190 { 1191 int cpu = smp_processor_id(); 1192 unsigned int value, queued; 1193 int i, j, acked = 0; 1194 unsigned long long tsc = 0, ntsc; 1195 long long max_loops = cpu_khz; 1196 1197 if (cpu_has_tsc) 1198 rdtscll(tsc); 1199 1200 if (disable_apic) { 1201 disable_ioapic_support(); 1202 return; 1203 } 1204 1205 #ifdef CONFIG_X86_32 1206 /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1207 if (lapic_is_integrated() && apic->disable_esr) { 1208 apic_write(APIC_ESR, 0); 1209 apic_write(APIC_ESR, 0); 1210 apic_write(APIC_ESR, 0); 1211 apic_write(APIC_ESR, 0); 1212 } 1213 #endif 1214 perf_events_lapic_init(); 1215 1216 /* 1217 * Double-check whether this APIC is really registered. 1218 * This is meaningless in clustered apic mode, so we skip it. 1219 */ 1220 BUG_ON(!apic->apic_id_registered()); 1221 1222 /* 1223 * Intel recommends to set DFR, LDR and TPR before enabling 1224 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1225 * document number 292116). So here it goes... 1226 */ 1227 apic->init_apic_ldr(); 1228 1229 #ifdef CONFIG_X86_32 1230 /* 1231 * APIC LDR is initialized. If logical_apicid mapping was 1232 * initialized during get_smp_config(), make sure it matches the 1233 * actual value. 1234 */ 1235 i = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 1236 WARN_ON(i != BAD_APICID && i != logical_smp_processor_id()); 1237 /* always use the value from LDR */ 1238 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 1239 logical_smp_processor_id(); 1240 #endif 1241 1242 /* 1243 * Set Task Priority to 'accept all'. We never change this 1244 * later on. 1245 */ 1246 value = apic_read(APIC_TASKPRI); 1247 value &= ~APIC_TPRI_MASK; 1248 apic_write(APIC_TASKPRI, value); 1249 1250 /* 1251 * After a crash, we no longer service the interrupts and a pending 1252 * interrupt from previous kernel might still have ISR bit set. 1253 * 1254 * Most probably by now CPU has serviced that pending interrupt and 1255 * it might not have done the ack_APIC_irq() because it thought, 1256 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1257 * does not clear the ISR bit and cpu thinks it has already serivced 1258 * the interrupt. Hence a vector might get locked. It was noticed 1259 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1260 */ 1261 do { 1262 queued = 0; 1263 for (i = APIC_ISR_NR - 1; i >= 0; i--) 1264 queued |= apic_read(APIC_IRR + i*0x10); 1265 1266 for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1267 value = apic_read(APIC_ISR + i*0x10); 1268 for (j = 31; j >= 0; j--) { 1269 if (value & (1<<j)) { 1270 ack_APIC_irq(); 1271 acked++; 1272 } 1273 } 1274 } 1275 if (acked > 256) { 1276 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", 1277 acked); 1278 break; 1279 } 1280 if (cpu_has_tsc) { 1281 rdtscll(ntsc); 1282 max_loops = (cpu_khz << 10) - (ntsc - tsc); 1283 } else 1284 max_loops--; 1285 } while (queued && max_loops > 0); 1286 WARN_ON(max_loops <= 0); 1287 1288 /* 1289 * Now that we are all set up, enable the APIC 1290 */ 1291 value = apic_read(APIC_SPIV); 1292 value &= ~APIC_VECTOR_MASK; 1293 /* 1294 * Enable APIC 1295 */ 1296 value |= APIC_SPIV_APIC_ENABLED; 1297 1298 #ifdef CONFIG_X86_32 1299 /* 1300 * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1301 * certain networking cards. If high frequency interrupts are 1302 * happening on a particular IOAPIC pin, plus the IOAPIC routing 1303 * entry is masked/unmasked at a high rate as well then sooner or 1304 * later IOAPIC line gets 'stuck', no more interrupts are received 1305 * from the device. If focus CPU is disabled then the hang goes 1306 * away, oh well :-( 1307 * 1308 * [ This bug can be reproduced easily with a level-triggered 1309 * PCI Ne2000 networking cards and PII/PIII processors, dual 1310 * BX chipset. ] 1311 */ 1312 /* 1313 * Actually disabling the focus CPU check just makes the hang less 1314 * frequent as it makes the interrupt distributon model be more 1315 * like LRU than MRU (the short-term load is more even across CPUs). 1316 * See also the comment in end_level_ioapic_irq(). --macro 1317 */ 1318 1319 /* 1320 * - enable focus processor (bit==0) 1321 * - 64bit mode always use processor focus 1322 * so no need to set it 1323 */ 1324 value &= ~APIC_SPIV_FOCUS_DISABLED; 1325 #endif 1326 1327 /* 1328 * Set spurious IRQ vector 1329 */ 1330 value |= SPURIOUS_APIC_VECTOR; 1331 apic_write(APIC_SPIV, value); 1332 1333 /* 1334 * Set up LVT0, LVT1: 1335 * 1336 * set up through-local-APIC on the BP's LINT0. This is not 1337 * strictly necessary in pure symmetric-IO mode, but sometimes 1338 * we delegate interrupts to the 8259A. 1339 */ 1340 /* 1341 * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1342 */ 1343 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1344 if (!cpu && (pic_mode || !value)) { 1345 value = APIC_DM_EXTINT; 1346 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1347 } else { 1348 value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1349 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1350 } 1351 apic_write(APIC_LVT0, value); 1352 1353 /* 1354 * only the BP should see the LINT1 NMI signal, obviously. 1355 */ 1356 if (!cpu) 1357 value = APIC_DM_NMI; 1358 else 1359 value = APIC_DM_NMI | APIC_LVT_MASKED; 1360 if (!lapic_is_integrated()) /* 82489DX */ 1361 value |= APIC_LVT_LEVEL_TRIGGER; 1362 apic_write(APIC_LVT1, value); 1363 1364 #ifdef CONFIG_X86_MCE_INTEL 1365 /* Recheck CMCI information after local APIC is up on CPU #0 */ 1366 if (!cpu) 1367 cmci_recheck(); 1368 #endif 1369 } 1370 1371 void __cpuinit end_local_APIC_setup(void) 1372 { 1373 lapic_setup_esr(); 1374 1375 #ifdef CONFIG_X86_32 1376 { 1377 unsigned int value; 1378 /* Disable the local apic timer */ 1379 value = apic_read(APIC_LVTT); 1380 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1381 apic_write(APIC_LVTT, value); 1382 } 1383 #endif 1384 1385 apic_pm_activate(); 1386 } 1387 1388 void __init bsp_end_local_APIC_setup(void) 1389 { 1390 end_local_APIC_setup(); 1391 1392 /* 1393 * Now that local APIC setup is completed for BP, configure the fault 1394 * handling for interrupt remapping. 1395 */ 1396 if (intr_remapping_enabled) 1397 enable_drhd_fault_handling(); 1398 1399 } 1400 1401 #ifdef CONFIG_X86_X2APIC 1402 void check_x2apic(void) 1403 { 1404 if (x2apic_enabled()) { 1405 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); 1406 x2apic_preenabled = x2apic_mode = 1; 1407 } 1408 } 1409 1410 void enable_x2apic(void) 1411 { 1412 int msr, msr2; 1413 1414 if (!x2apic_mode) 1415 return; 1416 1417 rdmsr(MSR_IA32_APICBASE, msr, msr2); 1418 if (!(msr & X2APIC_ENABLE)) { 1419 printk_once(KERN_INFO "Enabling x2apic\n"); 1420 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); 1421 } 1422 } 1423 #endif /* CONFIG_X86_X2APIC */ 1424 1425 int __init enable_IR(void) 1426 { 1427 #ifdef CONFIG_INTR_REMAP 1428 if (!intr_remapping_supported()) { 1429 pr_debug("intr-remapping not supported\n"); 1430 return 0; 1431 } 1432 1433 if (!x2apic_preenabled && skip_ioapic_setup) { 1434 pr_info("Skipped enabling intr-remap because of skipping " 1435 "io-apic setup\n"); 1436 return 0; 1437 } 1438 1439 if (enable_intr_remapping(x2apic_supported())) 1440 return 0; 1441 1442 pr_info("Enabled Interrupt-remapping\n"); 1443 1444 return 1; 1445 1446 #endif 1447 return 0; 1448 } 1449 1450 void __init enable_IR_x2apic(void) 1451 { 1452 unsigned long flags; 1453 struct IO_APIC_route_entry **ioapic_entries; 1454 int ret, x2apic_enabled = 0; 1455 int dmar_table_init_ret; 1456 1457 dmar_table_init_ret = dmar_table_init(); 1458 if (dmar_table_init_ret && !x2apic_supported()) 1459 return; 1460 1461 ioapic_entries = alloc_ioapic_entries(); 1462 if (!ioapic_entries) { 1463 pr_err("Allocate ioapic_entries failed\n"); 1464 goto out; 1465 } 1466 1467 ret = save_IO_APIC_setup(ioapic_entries); 1468 if (ret) { 1469 pr_info("Saving IO-APIC state failed: %d\n", ret); 1470 goto out; 1471 } 1472 1473 local_irq_save(flags); 1474 legacy_pic->mask_all(); 1475 mask_IO_APIC_setup(ioapic_entries); 1476 1477 if (dmar_table_init_ret) 1478 ret = 0; 1479 else 1480 ret = enable_IR(); 1481 1482 if (!ret) { 1483 /* IR is required if there is APIC ID > 255 even when running 1484 * under KVM 1485 */ 1486 if (max_physical_apicid > 255 || 1487 !hypervisor_x2apic_available()) 1488 goto nox2apic; 1489 /* 1490 * without IR all CPUs can be addressed by IOAPIC/MSI 1491 * only in physical mode 1492 */ 1493 x2apic_force_phys(); 1494 } 1495 1496 x2apic_enabled = 1; 1497 1498 if (x2apic_supported() && !x2apic_mode) { 1499 x2apic_mode = 1; 1500 enable_x2apic(); 1501 pr_info("Enabled x2apic\n"); 1502 } 1503 1504 nox2apic: 1505 if (!ret) /* IR enabling failed */ 1506 restore_IO_APIC_setup(ioapic_entries); 1507 legacy_pic->restore_mask(); 1508 local_irq_restore(flags); 1509 1510 out: 1511 if (ioapic_entries) 1512 free_ioapic_entries(ioapic_entries); 1513 1514 if (x2apic_enabled) 1515 return; 1516 1517 if (x2apic_preenabled) 1518 panic("x2apic: enabled by BIOS but kernel init failed."); 1519 else if (cpu_has_x2apic) 1520 pr_info("Not enabling x2apic, Intr-remapping init failed.\n"); 1521 } 1522 1523 #ifdef CONFIG_X86_64 1524 /* 1525 * Detect and enable local APICs on non-SMP boards. 1526 * Original code written by Keir Fraser. 1527 * On AMD64 we trust the BIOS - if it says no APIC it is likely 1528 * not correctly set up (usually the APIC timer won't work etc.) 1529 */ 1530 static int __init detect_init_APIC(void) 1531 { 1532 if (!cpu_has_apic) { 1533 pr_info("No local APIC present\n"); 1534 return -1; 1535 } 1536 1537 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1538 return 0; 1539 } 1540 #else 1541 1542 static int __init apic_verify(void) 1543 { 1544 u32 features, h, l; 1545 1546 /* 1547 * The APIC feature bit should now be enabled 1548 * in `cpuid' 1549 */ 1550 features = cpuid_edx(1); 1551 if (!(features & (1 << X86_FEATURE_APIC))) { 1552 pr_warning("Could not enable APIC!\n"); 1553 return -1; 1554 } 1555 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1556 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1557 1558 /* The BIOS may have set up the APIC at some other address */ 1559 rdmsr(MSR_IA32_APICBASE, l, h); 1560 if (l & MSR_IA32_APICBASE_ENABLE) 1561 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1562 1563 pr_info("Found and enabled local APIC!\n"); 1564 return 0; 1565 } 1566 1567 int __init apic_force_enable(unsigned long addr) 1568 { 1569 u32 h, l; 1570 1571 if (disable_apic) 1572 return -1; 1573 1574 /* 1575 * Some BIOSes disable the local APIC in the APIC_BASE 1576 * MSR. This can only be done in software for Intel P6 or later 1577 * and AMD K7 (Model > 1) or later. 1578 */ 1579 rdmsr(MSR_IA32_APICBASE, l, h); 1580 if (!(l & MSR_IA32_APICBASE_ENABLE)) { 1581 pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 1582 l &= ~MSR_IA32_APICBASE_BASE; 1583 l |= MSR_IA32_APICBASE_ENABLE | addr; 1584 wrmsr(MSR_IA32_APICBASE, l, h); 1585 enabled_via_apicbase = 1; 1586 } 1587 return apic_verify(); 1588 } 1589 1590 /* 1591 * Detect and initialize APIC 1592 */ 1593 static int __init detect_init_APIC(void) 1594 { 1595 /* Disabled by kernel option? */ 1596 if (disable_apic) 1597 return -1; 1598 1599 switch (boot_cpu_data.x86_vendor) { 1600 case X86_VENDOR_AMD: 1601 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1602 (boot_cpu_data.x86 >= 15)) 1603 break; 1604 goto no_apic; 1605 case X86_VENDOR_INTEL: 1606 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1607 (boot_cpu_data.x86 == 5 && cpu_has_apic)) 1608 break; 1609 goto no_apic; 1610 default: 1611 goto no_apic; 1612 } 1613 1614 if (!cpu_has_apic) { 1615 /* 1616 * Over-ride BIOS and try to enable the local APIC only if 1617 * "lapic" specified. 1618 */ 1619 if (!force_enable_local_apic) { 1620 pr_info("Local APIC disabled by BIOS -- " 1621 "you can enable it with \"lapic\"\n"); 1622 return -1; 1623 } 1624 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 1625 return -1; 1626 } else { 1627 if (apic_verify()) 1628 return -1; 1629 } 1630 1631 apic_pm_activate(); 1632 1633 return 0; 1634 1635 no_apic: 1636 pr_info("No local APIC present or hardware disabled\n"); 1637 return -1; 1638 } 1639 #endif 1640 1641 /** 1642 * init_apic_mappings - initialize APIC mappings 1643 */ 1644 void __init init_apic_mappings(void) 1645 { 1646 unsigned int new_apicid; 1647 1648 if (x2apic_mode) { 1649 boot_cpu_physical_apicid = read_apic_id(); 1650 return; 1651 } 1652 1653 /* If no local APIC can be found return early */ 1654 if (!smp_found_config && detect_init_APIC()) { 1655 /* lets NOP'ify apic operations */ 1656 pr_info("APIC: disable apic facility\n"); 1657 apic_disable(); 1658 } else { 1659 apic_phys = mp_lapic_addr; 1660 1661 /* 1662 * acpi lapic path already maps that address in 1663 * acpi_register_lapic_address() 1664 */ 1665 if (!acpi_lapic && !smp_found_config) 1666 register_lapic_address(apic_phys); 1667 } 1668 1669 /* 1670 * Fetch the APIC ID of the BSP in case we have a 1671 * default configuration (or the MP table is broken). 1672 */ 1673 new_apicid = read_apic_id(); 1674 if (boot_cpu_physical_apicid != new_apicid) { 1675 boot_cpu_physical_apicid = new_apicid; 1676 /* 1677 * yeah -- we lie about apic_version 1678 * in case if apic was disabled via boot option 1679 * but it's not a problem for SMP compiled kernel 1680 * since smp_sanity_check is prepared for such a case 1681 * and disable smp mode 1682 */ 1683 apic_version[new_apicid] = 1684 GET_APIC_VERSION(apic_read(APIC_LVR)); 1685 } 1686 } 1687 1688 void __init register_lapic_address(unsigned long address) 1689 { 1690 mp_lapic_addr = address; 1691 1692 if (!x2apic_mode) { 1693 set_fixmap_nocache(FIX_APIC_BASE, address); 1694 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 1695 APIC_BASE, mp_lapic_addr); 1696 } 1697 if (boot_cpu_physical_apicid == -1U) { 1698 boot_cpu_physical_apicid = read_apic_id(); 1699 apic_version[boot_cpu_physical_apicid] = 1700 GET_APIC_VERSION(apic_read(APIC_LVR)); 1701 } 1702 } 1703 1704 /* 1705 * This initializes the IO-APIC and APIC hardware if this is 1706 * a UP kernel. 1707 */ 1708 int apic_version[MAX_LOCAL_APIC]; 1709 1710 int __init APIC_init_uniprocessor(void) 1711 { 1712 if (disable_apic) { 1713 pr_info("Apic disabled\n"); 1714 return -1; 1715 } 1716 #ifdef CONFIG_X86_64 1717 if (!cpu_has_apic) { 1718 disable_apic = 1; 1719 pr_info("Apic disabled by BIOS\n"); 1720 return -1; 1721 } 1722 #else 1723 if (!smp_found_config && !cpu_has_apic) 1724 return -1; 1725 1726 /* 1727 * Complain if the BIOS pretends there is one. 1728 */ 1729 if (!cpu_has_apic && 1730 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 1731 pr_err("BIOS bug, local APIC 0x%x not detected!...\n", 1732 boot_cpu_physical_apicid); 1733 return -1; 1734 } 1735 #endif 1736 1737 default_setup_apic_routing(); 1738 1739 verify_local_APIC(); 1740 connect_bsp_APIC(); 1741 1742 #ifdef CONFIG_X86_64 1743 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); 1744 #else 1745 /* 1746 * Hack: In case of kdump, after a crash, kernel might be booting 1747 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 1748 * might be zero if read from MP tables. Get it from LAPIC. 1749 */ 1750 # ifdef CONFIG_CRASH_DUMP 1751 boot_cpu_physical_apicid = read_apic_id(); 1752 # endif 1753 #endif 1754 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1755 setup_local_APIC(); 1756 1757 #ifdef CONFIG_X86_IO_APIC 1758 /* 1759 * Now enable IO-APICs, actually call clear_IO_APIC 1760 * We need clear_IO_APIC before enabling error vector 1761 */ 1762 if (!skip_ioapic_setup && nr_ioapics) 1763 enable_IO_APIC(); 1764 #endif 1765 1766 bsp_end_local_APIC_setup(); 1767 1768 #ifdef CONFIG_X86_IO_APIC 1769 if (smp_found_config && !skip_ioapic_setup && nr_ioapics) 1770 setup_IO_APIC(); 1771 else { 1772 nr_ioapics = 0; 1773 } 1774 #endif 1775 1776 x86_init.timers.setup_percpu_clockev(); 1777 return 0; 1778 } 1779 1780 /* 1781 * Local APIC interrupts 1782 */ 1783 1784 /* 1785 * This interrupt should _never_ happen with our APIC/SMP architecture 1786 */ 1787 void smp_spurious_interrupt(struct pt_regs *regs) 1788 { 1789 u32 v; 1790 1791 exit_idle(); 1792 irq_enter(); 1793 /* 1794 * Check if this really is a spurious interrupt and ACK it 1795 * if it is a vectored one. Just in case... 1796 * Spurious interrupts should not be ACKed. 1797 */ 1798 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); 1799 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) 1800 ack_APIC_irq(); 1801 1802 inc_irq_stat(irq_spurious_count); 1803 1804 /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 1805 pr_info("spurious APIC interrupt on CPU#%d, " 1806 "should never happen.\n", smp_processor_id()); 1807 irq_exit(); 1808 } 1809 1810 /* 1811 * This interrupt should never happen with our APIC/SMP architecture 1812 */ 1813 void smp_error_interrupt(struct pt_regs *regs) 1814 { 1815 u32 v, v1; 1816 1817 exit_idle(); 1818 irq_enter(); 1819 /* First tickle the hardware, only then report what went on. -- REW */ 1820 v = apic_read(APIC_ESR); 1821 apic_write(APIC_ESR, 0); 1822 v1 = apic_read(APIC_ESR); 1823 ack_APIC_irq(); 1824 atomic_inc(&irq_err_count); 1825 1826 /* 1827 * Here is what the APIC error bits mean: 1828 * 0: Send CS error 1829 * 1: Receive CS error 1830 * 2: Send accept error 1831 * 3: Receive accept error 1832 * 4: Reserved 1833 * 5: Send illegal vector 1834 * 6: Received illegal vector 1835 * 7: Illegal register address 1836 */ 1837 pr_debug("APIC error on CPU%d: %02x(%02x)\n", 1838 smp_processor_id(), v , v1); 1839 irq_exit(); 1840 } 1841 1842 /** 1843 * connect_bsp_APIC - attach the APIC to the interrupt system 1844 */ 1845 void __init connect_bsp_APIC(void) 1846 { 1847 #ifdef CONFIG_X86_32 1848 if (pic_mode) { 1849 /* 1850 * Do not trust the local APIC being empty at bootup. 1851 */ 1852 clear_local_APIC(); 1853 /* 1854 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 1855 * local APIC to INT and NMI lines. 1856 */ 1857 apic_printk(APIC_VERBOSE, "leaving PIC mode, " 1858 "enabling APIC mode.\n"); 1859 imcr_pic_to_apic(); 1860 } 1861 #endif 1862 if (apic->enable_apic_mode) 1863 apic->enable_apic_mode(); 1864 } 1865 1866 /** 1867 * disconnect_bsp_APIC - detach the APIC from the interrupt system 1868 * @virt_wire_setup: indicates, whether virtual wire mode is selected 1869 * 1870 * Virtual wire mode is necessary to deliver legacy interrupts even when the 1871 * APIC is disabled. 1872 */ 1873 void disconnect_bsp_APIC(int virt_wire_setup) 1874 { 1875 unsigned int value; 1876 1877 #ifdef CONFIG_X86_32 1878 if (pic_mode) { 1879 /* 1880 * Put the board back into PIC mode (has an effect only on 1881 * certain older boards). Note that APIC interrupts, including 1882 * IPIs, won't work beyond this point! The only exception are 1883 * INIT IPIs. 1884 */ 1885 apic_printk(APIC_VERBOSE, "disabling APIC mode, " 1886 "entering PIC mode.\n"); 1887 imcr_apic_to_pic(); 1888 return; 1889 } 1890 #endif 1891 1892 /* Go back to Virtual Wire compatibility mode */ 1893 1894 /* For the spurious interrupt use vector F, and enable it */ 1895 value = apic_read(APIC_SPIV); 1896 value &= ~APIC_VECTOR_MASK; 1897 value |= APIC_SPIV_APIC_ENABLED; 1898 value |= 0xf; 1899 apic_write(APIC_SPIV, value); 1900 1901 if (!virt_wire_setup) { 1902 /* 1903 * For LVT0 make it edge triggered, active high, 1904 * external and enabled 1905 */ 1906 value = apic_read(APIC_LVT0); 1907 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1908 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1909 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1910 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1911 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 1912 apic_write(APIC_LVT0, value); 1913 } else { 1914 /* Disable LVT0 */ 1915 apic_write(APIC_LVT0, APIC_LVT_MASKED); 1916 } 1917 1918 /* 1919 * For LVT1 make it edge triggered, active high, 1920 * nmi and enabled 1921 */ 1922 value = apic_read(APIC_LVT1); 1923 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1924 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1925 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1926 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1927 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 1928 apic_write(APIC_LVT1, value); 1929 } 1930 1931 void __cpuinit generic_processor_info(int apicid, int version) 1932 { 1933 int cpu; 1934 1935 if (num_processors >= nr_cpu_ids) { 1936 int max = nr_cpu_ids; 1937 int thiscpu = max + disabled_cpus; 1938 1939 pr_warning( 1940 "ACPI: NR_CPUS/possible_cpus limit of %i reached." 1941 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 1942 1943 disabled_cpus++; 1944 return; 1945 } 1946 1947 num_processors++; 1948 if (apicid == boot_cpu_physical_apicid) { 1949 /* 1950 * x86_bios_cpu_apicid is required to have processors listed 1951 * in same order as logical cpu numbers. Hence the first 1952 * entry is BSP, and so on. 1953 * boot_cpu_init() already hold bit 0 in cpu_present_mask 1954 * for BSP. 1955 */ 1956 cpu = 0; 1957 } else 1958 cpu = cpumask_next_zero(-1, cpu_present_mask); 1959 1960 /* 1961 * Validate version 1962 */ 1963 if (version == 0x0) { 1964 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", 1965 cpu, apicid); 1966 version = 0x10; 1967 } 1968 apic_version[apicid] = version; 1969 1970 if (version != apic_version[boot_cpu_physical_apicid]) { 1971 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", 1972 apic_version[boot_cpu_physical_apicid], cpu, version); 1973 } 1974 1975 physid_set(apicid, phys_cpu_present_map); 1976 if (apicid > max_physical_apicid) 1977 max_physical_apicid = apicid; 1978 1979 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 1980 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 1981 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 1982 #endif 1983 #ifdef CONFIG_X86_32 1984 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 1985 apic->x86_32_early_logical_apicid(cpu); 1986 #endif 1987 set_cpu_possible(cpu, true); 1988 set_cpu_present(cpu, true); 1989 } 1990 1991 int hard_smp_processor_id(void) 1992 { 1993 return read_apic_id(); 1994 } 1995 1996 void default_init_apic_ldr(void) 1997 { 1998 unsigned long val; 1999 2000 apic_write(APIC_DFR, APIC_DFR_VALUE); 2001 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; 2002 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); 2003 apic_write(APIC_LDR, val); 2004 } 2005 2006 #ifdef CONFIG_X86_32 2007 int default_x86_32_numa_cpu_node(int cpu) 2008 { 2009 #ifdef CONFIG_NUMA 2010 int apicid = early_per_cpu(x86_cpu_to_apicid, cpu); 2011 2012 if (apicid != BAD_APICID) 2013 return __apicid_to_node[apicid]; 2014 return NUMA_NO_NODE; 2015 #else 2016 return 0; 2017 #endif 2018 } 2019 #endif 2020 2021 /* 2022 * Power management 2023 */ 2024 #ifdef CONFIG_PM 2025 2026 static struct { 2027 /* 2028 * 'active' is true if the local APIC was enabled by us and 2029 * not the BIOS; this signifies that we are also responsible 2030 * for disabling it before entering apm/acpi suspend 2031 */ 2032 int active; 2033 /* r/w apic fields */ 2034 unsigned int apic_id; 2035 unsigned int apic_taskpri; 2036 unsigned int apic_ldr; 2037 unsigned int apic_dfr; 2038 unsigned int apic_spiv; 2039 unsigned int apic_lvtt; 2040 unsigned int apic_lvtpc; 2041 unsigned int apic_lvt0; 2042 unsigned int apic_lvt1; 2043 unsigned int apic_lvterr; 2044 unsigned int apic_tmict; 2045 unsigned int apic_tdcr; 2046 unsigned int apic_thmr; 2047 } apic_pm_state; 2048 2049 static int lapic_suspend(struct sys_device *dev, pm_message_t state) 2050 { 2051 unsigned long flags; 2052 int maxlvt; 2053 2054 if (!apic_pm_state.active) 2055 return 0; 2056 2057 maxlvt = lapic_get_maxlvt(); 2058 2059 apic_pm_state.apic_id = apic_read(APIC_ID); 2060 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2061 apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2062 apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2063 apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2064 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2065 if (maxlvt >= 4) 2066 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2067 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2068 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2069 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2070 apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2071 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 2072 #ifdef CONFIG_X86_THERMAL_VECTOR 2073 if (maxlvt >= 5) 2074 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2075 #endif 2076 2077 local_irq_save(flags); 2078 disable_local_APIC(); 2079 2080 if (intr_remapping_enabled) 2081 disable_intr_remapping(); 2082 2083 local_irq_restore(flags); 2084 return 0; 2085 } 2086 2087 static int lapic_resume(struct sys_device *dev) 2088 { 2089 unsigned int l, h; 2090 unsigned long flags; 2091 int maxlvt; 2092 int ret = 0; 2093 struct IO_APIC_route_entry **ioapic_entries = NULL; 2094 2095 if (!apic_pm_state.active) 2096 return 0; 2097 2098 local_irq_save(flags); 2099 if (intr_remapping_enabled) { 2100 ioapic_entries = alloc_ioapic_entries(); 2101 if (!ioapic_entries) { 2102 WARN(1, "Alloc ioapic_entries in lapic resume failed."); 2103 ret = -ENOMEM; 2104 goto restore; 2105 } 2106 2107 ret = save_IO_APIC_setup(ioapic_entries); 2108 if (ret) { 2109 WARN(1, "Saving IO-APIC state failed: %d\n", ret); 2110 free_ioapic_entries(ioapic_entries); 2111 goto restore; 2112 } 2113 2114 mask_IO_APIC_setup(ioapic_entries); 2115 legacy_pic->mask_all(); 2116 } 2117 2118 if (x2apic_mode) 2119 enable_x2apic(); 2120 else { 2121 /* 2122 * Make sure the APICBASE points to the right address 2123 * 2124 * FIXME! This will be wrong if we ever support suspend on 2125 * SMP! We'll need to do this as part of the CPU restore! 2126 */ 2127 rdmsr(MSR_IA32_APICBASE, l, h); 2128 l &= ~MSR_IA32_APICBASE_BASE; 2129 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2130 wrmsr(MSR_IA32_APICBASE, l, h); 2131 } 2132 2133 maxlvt = lapic_get_maxlvt(); 2134 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2135 apic_write(APIC_ID, apic_pm_state.apic_id); 2136 apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2137 apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2138 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2139 apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2140 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2141 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2142 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) 2143 if (maxlvt >= 5) 2144 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2145 #endif 2146 if (maxlvt >= 4) 2147 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2148 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2149 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2150 apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2151 apic_write(APIC_ESR, 0); 2152 apic_read(APIC_ESR); 2153 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2154 apic_write(APIC_ESR, 0); 2155 apic_read(APIC_ESR); 2156 2157 if (intr_remapping_enabled) { 2158 reenable_intr_remapping(x2apic_mode); 2159 legacy_pic->restore_mask(); 2160 restore_IO_APIC_setup(ioapic_entries); 2161 free_ioapic_entries(ioapic_entries); 2162 } 2163 restore: 2164 local_irq_restore(flags); 2165 2166 return ret; 2167 } 2168 2169 /* 2170 * This device has no shutdown method - fully functioning local APICs 2171 * are needed on every CPU up until machine_halt/restart/poweroff. 2172 */ 2173 2174 static struct sysdev_class lapic_sysclass = { 2175 .name = "lapic", 2176 .resume = lapic_resume, 2177 .suspend = lapic_suspend, 2178 }; 2179 2180 static struct sys_device device_lapic = { 2181 .id = 0, 2182 .cls = &lapic_sysclass, 2183 }; 2184 2185 static void __cpuinit apic_pm_activate(void) 2186 { 2187 apic_pm_state.active = 1; 2188 } 2189 2190 static int __init init_lapic_sysfs(void) 2191 { 2192 int error; 2193 2194 if (!cpu_has_apic) 2195 return 0; 2196 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2197 2198 error = sysdev_class_register(&lapic_sysclass); 2199 if (!error) 2200 error = sysdev_register(&device_lapic); 2201 return error; 2202 } 2203 2204 /* local apic needs to resume before other devices access its registers. */ 2205 core_initcall(init_lapic_sysfs); 2206 2207 #else /* CONFIG_PM */ 2208 2209 static void apic_pm_activate(void) { } 2210 2211 #endif /* CONFIG_PM */ 2212 2213 #ifdef CONFIG_X86_64 2214 2215 static int __cpuinit apic_cluster_num(void) 2216 { 2217 int i, clusters, zeros; 2218 unsigned id; 2219 u16 *bios_cpu_apicid; 2220 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); 2221 2222 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); 2223 bitmap_zero(clustermap, NUM_APIC_CLUSTERS); 2224 2225 for (i = 0; i < nr_cpu_ids; i++) { 2226 /* are we being called early in kernel startup? */ 2227 if (bios_cpu_apicid) { 2228 id = bios_cpu_apicid[i]; 2229 } else if (i < nr_cpu_ids) { 2230 if (cpu_present(i)) 2231 id = per_cpu(x86_bios_cpu_apicid, i); 2232 else 2233 continue; 2234 } else 2235 break; 2236 2237 if (id != BAD_APICID) 2238 __set_bit(APIC_CLUSTERID(id), clustermap); 2239 } 2240 2241 /* Problem: Partially populated chassis may not have CPUs in some of 2242 * the APIC clusters they have been allocated. Only present CPUs have 2243 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. 2244 * Since clusters are allocated sequentially, count zeros only if 2245 * they are bounded by ones. 2246 */ 2247 clusters = 0; 2248 zeros = 0; 2249 for (i = 0; i < NUM_APIC_CLUSTERS; i++) { 2250 if (test_bit(i, clustermap)) { 2251 clusters += 1 + zeros; 2252 zeros = 0; 2253 } else 2254 ++zeros; 2255 } 2256 2257 return clusters; 2258 } 2259 2260 static int __cpuinitdata multi_checked; 2261 static int __cpuinitdata multi; 2262 2263 static int __cpuinit set_multi(const struct dmi_system_id *d) 2264 { 2265 if (multi) 2266 return 0; 2267 pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2268 multi = 1; 2269 return 0; 2270 } 2271 2272 static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = { 2273 { 2274 .callback = set_multi, 2275 .ident = "IBM System Summit2", 2276 .matches = { 2277 DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2278 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2279 }, 2280 }, 2281 {} 2282 }; 2283 2284 static void __cpuinit dmi_check_multi(void) 2285 { 2286 if (multi_checked) 2287 return; 2288 2289 dmi_check_system(multi_dmi_table); 2290 multi_checked = 1; 2291 } 2292 2293 /* 2294 * apic_is_clustered_box() -- Check if we can expect good TSC 2295 * 2296 * Thus far, the major user of this is IBM's Summit2 series: 2297 * Clustered boxes may have unsynced TSC problems if they are 2298 * multi-chassis. 2299 * Use DMI to check them 2300 */ 2301 __cpuinit int apic_is_clustered_box(void) 2302 { 2303 dmi_check_multi(); 2304 if (multi) 2305 return 1; 2306 2307 if (!is_vsmp_box()) 2308 return 0; 2309 2310 /* 2311 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are 2312 * not guaranteed to be synced between boards 2313 */ 2314 if (apic_cluster_num() > 1) 2315 return 1; 2316 2317 return 0; 2318 } 2319 #endif 2320 2321 /* 2322 * APIC command line parameters 2323 */ 2324 static int __init setup_disableapic(char *arg) 2325 { 2326 disable_apic = 1; 2327 setup_clear_cpu_cap(X86_FEATURE_APIC); 2328 return 0; 2329 } 2330 early_param("disableapic", setup_disableapic); 2331 2332 /* same as disableapic, for compatibility */ 2333 static int __init setup_nolapic(char *arg) 2334 { 2335 return setup_disableapic(arg); 2336 } 2337 early_param("nolapic", setup_nolapic); 2338 2339 static int __init parse_lapic_timer_c2_ok(char *arg) 2340 { 2341 local_apic_timer_c2_ok = 1; 2342 return 0; 2343 } 2344 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2345 2346 static int __init parse_disable_apic_timer(char *arg) 2347 { 2348 disable_apic_timer = 1; 2349 return 0; 2350 } 2351 early_param("noapictimer", parse_disable_apic_timer); 2352 2353 static int __init parse_nolapic_timer(char *arg) 2354 { 2355 disable_apic_timer = 1; 2356 return 0; 2357 } 2358 early_param("nolapic_timer", parse_nolapic_timer); 2359 2360 static int __init apic_set_verbosity(char *arg) 2361 { 2362 if (!arg) { 2363 #ifdef CONFIG_X86_64 2364 skip_ioapic_setup = 0; 2365 return 0; 2366 #endif 2367 return -EINVAL; 2368 } 2369 2370 if (strcmp("debug", arg) == 0) 2371 apic_verbosity = APIC_DEBUG; 2372 else if (strcmp("verbose", arg) == 0) 2373 apic_verbosity = APIC_VERBOSE; 2374 else { 2375 pr_warning("APIC Verbosity level %s not recognised" 2376 " use apic=verbose or apic=debug\n", arg); 2377 return -EINVAL; 2378 } 2379 2380 return 0; 2381 } 2382 early_param("apic", apic_set_verbosity); 2383 2384 static int __init lapic_insert_resource(void) 2385 { 2386 if (!apic_phys) 2387 return -1; 2388 2389 /* Put local APIC into the resource map. */ 2390 lapic_resource.start = apic_phys; 2391 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2392 insert_resource(&iomem_resource, &lapic_resource); 2393 2394 return 0; 2395 } 2396 2397 /* 2398 * need call insert after e820_reserve_resources() 2399 * that is using request_resource 2400 */ 2401 late_initcall(lapic_insert_resource); 2402