1 /* 2 * Local APIC handling, local APIC timers 3 * 4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5 * 6 * Fixes 7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8 * thanks to Eric Gilmore 9 * and Rolf G. Tews 10 * for testing these extensively. 11 * Maciej W. Rozycki : Various updates and fixes. 12 * Mikael Pettersson : Power Management for UP-APIC. 13 * Pavel Machek and 14 * Mikael Pettersson : PM converted to driver model. 15 */ 16 17 #include <linux/perf_counter.h> 18 #include <linux/kernel_stat.h> 19 #include <linux/mc146818rtc.h> 20 #include <linux/acpi_pmtmr.h> 21 #include <linux/clockchips.h> 22 #include <linux/interrupt.h> 23 #include <linux/bootmem.h> 24 #include <linux/ftrace.h> 25 #include <linux/ioport.h> 26 #include <linux/module.h> 27 #include <linux/sysdev.h> 28 #include <linux/delay.h> 29 #include <linux/timex.h> 30 #include <linux/dmar.h> 31 #include <linux/init.h> 32 #include <linux/cpu.h> 33 #include <linux/dmi.h> 34 #include <linux/nmi.h> 35 #include <linux/smp.h> 36 #include <linux/mm.h> 37 38 #include <asm/perf_counter.h> 39 #include <asm/pgalloc.h> 40 #include <asm/atomic.h> 41 #include <asm/mpspec.h> 42 #include <asm/i8253.h> 43 #include <asm/i8259.h> 44 #include <asm/proto.h> 45 #include <asm/apic.h> 46 #include <asm/desc.h> 47 #include <asm/hpet.h> 48 #include <asm/idle.h> 49 #include <asm/mtrr.h> 50 #include <asm/smp.h> 51 #include <asm/mce.h> 52 53 unsigned int num_processors; 54 55 unsigned disabled_cpus __cpuinitdata; 56 57 /* Processor that is doing the boot up */ 58 unsigned int boot_cpu_physical_apicid = -1U; 59 60 /* 61 * The highest APIC ID seen during enumeration. 62 * 63 * This determines the messaging protocol we can use: if all APIC IDs 64 * are in the 0 ... 7 range, then we can use logical addressing which 65 * has some performance advantages (better broadcasting). 66 * 67 * If there's an APIC ID above 8, we use physical addressing. 68 */ 69 unsigned int max_physical_apicid; 70 71 /* 72 * Bitmask of physically existing CPUs: 73 */ 74 physid_mask_t phys_cpu_present_map; 75 76 /* 77 * Map cpu index to physical APIC ID 78 */ 79 DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID); 80 DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID); 81 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 82 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 83 84 #ifdef CONFIG_X86_32 85 /* 86 * Knob to control our willingness to enable the local APIC. 87 * 88 * +1=force-enable 89 */ 90 static int force_enable_local_apic; 91 /* 92 * APIC command line parameters 93 */ 94 static int __init parse_lapic(char *arg) 95 { 96 force_enable_local_apic = 1; 97 return 0; 98 } 99 early_param("lapic", parse_lapic); 100 /* Local APIC was disabled by the BIOS and enabled by the kernel */ 101 static int enabled_via_apicbase; 102 103 /* 104 * Handle interrupt mode configuration register (IMCR). 105 * This register controls whether the interrupt signals 106 * that reach the BSP come from the master PIC or from the 107 * local APIC. Before entering Symmetric I/O Mode, either 108 * the BIOS or the operating system must switch out of 109 * PIC Mode by changing the IMCR. 110 */ 111 static inline void imcr_pic_to_apic(void) 112 { 113 /* select IMCR register */ 114 outb(0x70, 0x22); 115 /* NMI and 8259 INTR go through APIC */ 116 outb(0x01, 0x23); 117 } 118 119 static inline void imcr_apic_to_pic(void) 120 { 121 /* select IMCR register */ 122 outb(0x70, 0x22); 123 /* NMI and 8259 INTR go directly to BSP */ 124 outb(0x00, 0x23); 125 } 126 #endif 127 128 #ifdef CONFIG_X86_64 129 static int apic_calibrate_pmtmr __initdata; 130 static __init int setup_apicpmtimer(char *s) 131 { 132 apic_calibrate_pmtmr = 1; 133 notsc_setup(NULL); 134 return 0; 135 } 136 __setup("apicpmtimer", setup_apicpmtimer); 137 #endif 138 139 int x2apic_mode; 140 #ifdef CONFIG_X86_X2APIC 141 /* x2apic enabled before OS handover */ 142 static int x2apic_preenabled; 143 static __init int setup_nox2apic(char *str) 144 { 145 if (x2apic_enabled()) { 146 pr_warning("Bios already enabled x2apic, " 147 "can't enforce nox2apic"); 148 return 0; 149 } 150 151 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 152 return 0; 153 } 154 early_param("nox2apic", setup_nox2apic); 155 #endif 156 157 unsigned long mp_lapic_addr; 158 int disable_apic; 159 /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 160 static int disable_apic_timer __cpuinitdata; 161 /* Local APIC timer works in C2 */ 162 int local_apic_timer_c2_ok; 163 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 164 165 int first_system_vector = 0xfe; 166 167 /* 168 * Debug level, exported for io_apic.c 169 */ 170 unsigned int apic_verbosity; 171 172 int pic_mode; 173 174 /* Have we found an MP table */ 175 int smp_found_config; 176 177 static struct resource lapic_resource = { 178 .name = "Local APIC", 179 .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 180 }; 181 182 static unsigned int calibration_result; 183 184 static int lapic_next_event(unsigned long delta, 185 struct clock_event_device *evt); 186 static void lapic_timer_setup(enum clock_event_mode mode, 187 struct clock_event_device *evt); 188 static void lapic_timer_broadcast(const struct cpumask *mask); 189 static void apic_pm_activate(void); 190 191 /* 192 * The local apic timer can be used for any function which is CPU local. 193 */ 194 static struct clock_event_device lapic_clockevent = { 195 .name = "lapic", 196 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT 197 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, 198 .shift = 32, 199 .set_mode = lapic_timer_setup, 200 .set_next_event = lapic_next_event, 201 .broadcast = lapic_timer_broadcast, 202 .rating = 100, 203 .irq = -1, 204 }; 205 static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 206 207 static unsigned long apic_phys; 208 209 /* 210 * Get the LAPIC version 211 */ 212 static inline int lapic_get_version(void) 213 { 214 return GET_APIC_VERSION(apic_read(APIC_LVR)); 215 } 216 217 /* 218 * Check, if the APIC is integrated or a separate chip 219 */ 220 static inline int lapic_is_integrated(void) 221 { 222 #ifdef CONFIG_X86_64 223 return 1; 224 #else 225 return APIC_INTEGRATED(lapic_get_version()); 226 #endif 227 } 228 229 /* 230 * Check, whether this is a modern or a first generation APIC 231 */ 232 static int modern_apic(void) 233 { 234 /* AMD systems use old APIC versions, so check the CPU */ 235 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 236 boot_cpu_data.x86 >= 0xf) 237 return 1; 238 return lapic_get_version() >= 0x14; 239 } 240 241 /* 242 * bare function to substitute write operation 243 * and it's _that_ fast :) 244 */ 245 static void native_apic_write_dummy(u32 reg, u32 v) 246 { 247 WARN_ON_ONCE((cpu_has_apic || !disable_apic)); 248 } 249 250 static u32 native_apic_read_dummy(u32 reg) 251 { 252 WARN_ON_ONCE((cpu_has_apic && !disable_apic)); 253 return 0; 254 } 255 256 /* 257 * right after this call apic->write/read doesn't do anything 258 * note that there is no restore operation it works one way 259 */ 260 void apic_disable(void) 261 { 262 apic->read = native_apic_read_dummy; 263 apic->write = native_apic_write_dummy; 264 } 265 266 void native_apic_wait_icr_idle(void) 267 { 268 while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 269 cpu_relax(); 270 } 271 272 u32 native_safe_apic_wait_icr_idle(void) 273 { 274 u32 send_status; 275 int timeout; 276 277 timeout = 0; 278 do { 279 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 280 if (!send_status) 281 break; 282 udelay(100); 283 } while (timeout++ < 1000); 284 285 return send_status; 286 } 287 288 void native_apic_icr_write(u32 low, u32 id) 289 { 290 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 291 apic_write(APIC_ICR, low); 292 } 293 294 u64 native_apic_icr_read(void) 295 { 296 u32 icr1, icr2; 297 298 icr2 = apic_read(APIC_ICR2); 299 icr1 = apic_read(APIC_ICR); 300 301 return icr1 | ((u64)icr2 << 32); 302 } 303 304 /** 305 * enable_NMI_through_LVT0 - enable NMI through local vector table 0 306 */ 307 void __cpuinit enable_NMI_through_LVT0(void) 308 { 309 unsigned int v; 310 311 /* unmask and set to NMI */ 312 v = APIC_DM_NMI; 313 314 /* Level triggered for 82489DX (32bit mode) */ 315 if (!lapic_is_integrated()) 316 v |= APIC_LVT_LEVEL_TRIGGER; 317 318 apic_write(APIC_LVT0, v); 319 } 320 321 #ifdef CONFIG_X86_32 322 /** 323 * get_physical_broadcast - Get number of physical broadcast IDs 324 */ 325 int get_physical_broadcast(void) 326 { 327 return modern_apic() ? 0xff : 0xf; 328 } 329 #endif 330 331 /** 332 * lapic_get_maxlvt - get the maximum number of local vector table entries 333 */ 334 int lapic_get_maxlvt(void) 335 { 336 unsigned int v; 337 338 v = apic_read(APIC_LVR); 339 /* 340 * - we always have APIC integrated on 64bit mode 341 * - 82489DXs do not report # of LVT entries 342 */ 343 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; 344 } 345 346 /* 347 * Local APIC timer 348 */ 349 350 /* Clock divisor */ 351 #define APIC_DIVISOR 16 352 353 /* 354 * This function sets up the local APIC timer, with a timeout of 355 * 'clocks' APIC bus clock. During calibration we actually call 356 * this function twice on the boot CPU, once with a bogus timeout 357 * value, second time for real. The other (noncalibrating) CPUs 358 * call this function only once, with the real, calibrated value. 359 * 360 * We do reads before writes even if unnecessary, to get around the 361 * P5 APIC double write bug. 362 */ 363 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 364 { 365 unsigned int lvtt_value, tmp_value; 366 367 lvtt_value = LOCAL_TIMER_VECTOR; 368 if (!oneshot) 369 lvtt_value |= APIC_LVT_TIMER_PERIODIC; 370 if (!lapic_is_integrated()) 371 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 372 373 if (!irqen) 374 lvtt_value |= APIC_LVT_MASKED; 375 376 apic_write(APIC_LVTT, lvtt_value); 377 378 /* 379 * Divide PICLK by 16 380 */ 381 tmp_value = apic_read(APIC_TDCR); 382 apic_write(APIC_TDCR, 383 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 384 APIC_TDR_DIV_16); 385 386 if (!oneshot) 387 apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 388 } 389 390 /* 391 * Setup extended LVT, AMD specific (K8, family 10h) 392 * 393 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and 394 * MCE interrupts are supported. Thus MCE offset must be set to 0. 395 * 396 * If mask=1, the LVT entry does not generate interrupts while mask=0 397 * enables the vector. See also the BKDGs. 398 */ 399 400 #define APIC_EILVT_LVTOFF_MCE 0 401 #define APIC_EILVT_LVTOFF_IBS 1 402 403 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) 404 { 405 unsigned long reg = (lvt_off << 4) + APIC_EILVTn(0); 406 unsigned int v = (mask << 16) | (msg_type << 8) | vector; 407 408 apic_write(reg, v); 409 } 410 411 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) 412 { 413 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); 414 return APIC_EILVT_LVTOFF_MCE; 415 } 416 417 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) 418 { 419 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); 420 return APIC_EILVT_LVTOFF_IBS; 421 } 422 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs); 423 424 /* 425 * Program the next event, relative to now 426 */ 427 static int lapic_next_event(unsigned long delta, 428 struct clock_event_device *evt) 429 { 430 apic_write(APIC_TMICT, delta); 431 return 0; 432 } 433 434 /* 435 * Setup the lapic timer in periodic or oneshot mode 436 */ 437 static void lapic_timer_setup(enum clock_event_mode mode, 438 struct clock_event_device *evt) 439 { 440 unsigned long flags; 441 unsigned int v; 442 443 /* Lapic used as dummy for broadcast ? */ 444 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 445 return; 446 447 local_irq_save(flags); 448 449 switch (mode) { 450 case CLOCK_EVT_MODE_PERIODIC: 451 case CLOCK_EVT_MODE_ONESHOT: 452 __setup_APIC_LVTT(calibration_result, 453 mode != CLOCK_EVT_MODE_PERIODIC, 1); 454 break; 455 case CLOCK_EVT_MODE_UNUSED: 456 case CLOCK_EVT_MODE_SHUTDOWN: 457 v = apic_read(APIC_LVTT); 458 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 459 apic_write(APIC_LVTT, v); 460 apic_write(APIC_TMICT, 0xffffffff); 461 break; 462 case CLOCK_EVT_MODE_RESUME: 463 /* Nothing to do here */ 464 break; 465 } 466 467 local_irq_restore(flags); 468 } 469 470 /* 471 * Local APIC timer broadcast function 472 */ 473 static void lapic_timer_broadcast(const struct cpumask *mask) 474 { 475 #ifdef CONFIG_SMP 476 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 477 #endif 478 } 479 480 /* 481 * Setup the local APIC timer for this CPU. Copy the initilized values 482 * of the boot CPU and register the clock event in the framework. 483 */ 484 static void __cpuinit setup_APIC_timer(void) 485 { 486 struct clock_event_device *levt = &__get_cpu_var(lapic_events); 487 488 if (cpu_has(¤t_cpu_data, X86_FEATURE_ARAT)) { 489 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 490 /* Make LAPIC timer preferrable over percpu HPET */ 491 lapic_clockevent.rating = 150; 492 } 493 494 memcpy(levt, &lapic_clockevent, sizeof(*levt)); 495 levt->cpumask = cpumask_of(smp_processor_id()); 496 497 clockevents_register_device(levt); 498 } 499 500 /* 501 * In this functions we calibrate APIC bus clocks to the external timer. 502 * 503 * We want to do the calibration only once since we want to have local timer 504 * irqs syncron. CPUs connected by the same APIC bus have the very same bus 505 * frequency. 506 * 507 * This was previously done by reading the PIT/HPET and waiting for a wrap 508 * around to find out, that a tick has elapsed. I have a box, where the PIT 509 * readout is broken, so it never gets out of the wait loop again. This was 510 * also reported by others. 511 * 512 * Monitoring the jiffies value is inaccurate and the clockevents 513 * infrastructure allows us to do a simple substitution of the interrupt 514 * handler. 515 * 516 * The calibration routine also uses the pm_timer when possible, as the PIT 517 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 518 * back to normal later in the boot process). 519 */ 520 521 #define LAPIC_CAL_LOOPS (HZ/10) 522 523 static __initdata int lapic_cal_loops = -1; 524 static __initdata long lapic_cal_t1, lapic_cal_t2; 525 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 526 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 527 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 528 529 /* 530 * Temporary interrupt handler. 531 */ 532 static void __init lapic_cal_handler(struct clock_event_device *dev) 533 { 534 unsigned long long tsc = 0; 535 long tapic = apic_read(APIC_TMCCT); 536 unsigned long pm = acpi_pm_read_early(); 537 538 if (cpu_has_tsc) 539 rdtscll(tsc); 540 541 switch (lapic_cal_loops++) { 542 case 0: 543 lapic_cal_t1 = tapic; 544 lapic_cal_tsc1 = tsc; 545 lapic_cal_pm1 = pm; 546 lapic_cal_j1 = jiffies; 547 break; 548 549 case LAPIC_CAL_LOOPS: 550 lapic_cal_t2 = tapic; 551 lapic_cal_tsc2 = tsc; 552 if (pm < lapic_cal_pm1) 553 pm += ACPI_PM_OVRRUN; 554 lapic_cal_pm2 = pm; 555 lapic_cal_j2 = jiffies; 556 break; 557 } 558 } 559 560 static int __init 561 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 562 { 563 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 564 const long pm_thresh = pm_100ms / 100; 565 unsigned long mult; 566 u64 res; 567 568 #ifndef CONFIG_X86_PM_TIMER 569 return -1; 570 #endif 571 572 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 573 574 /* Check, if the PM timer is available */ 575 if (!deltapm) 576 return -1; 577 578 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 579 580 if (deltapm > (pm_100ms - pm_thresh) && 581 deltapm < (pm_100ms + pm_thresh)) { 582 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 583 return 0; 584 } 585 586 res = (((u64)deltapm) * mult) >> 22; 587 do_div(res, 1000000); 588 pr_warning("APIC calibration not consistent " 589 "with PM-Timer: %ldms instead of 100ms\n",(long)res); 590 591 /* Correct the lapic counter value */ 592 res = (((u64)(*delta)) * pm_100ms); 593 do_div(res, deltapm); 594 pr_info("APIC delta adjusted to PM-Timer: " 595 "%lu (%ld)\n", (unsigned long)res, *delta); 596 *delta = (long)res; 597 598 /* Correct the tsc counter value */ 599 if (cpu_has_tsc) { 600 res = (((u64)(*deltatsc)) * pm_100ms); 601 do_div(res, deltapm); 602 apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 603 "PM-Timer: %lu (%ld) \n", 604 (unsigned long)res, *deltatsc); 605 *deltatsc = (long)res; 606 } 607 608 return 0; 609 } 610 611 static int __init calibrate_APIC_clock(void) 612 { 613 struct clock_event_device *levt = &__get_cpu_var(lapic_events); 614 void (*real_handler)(struct clock_event_device *dev); 615 unsigned long deltaj; 616 long delta, deltatsc; 617 int pm_referenced = 0; 618 619 local_irq_disable(); 620 621 /* Replace the global interrupt handler */ 622 real_handler = global_clock_event->event_handler; 623 global_clock_event->event_handler = lapic_cal_handler; 624 625 /* 626 * Setup the APIC counter to maximum. There is no way the lapic 627 * can underflow in the 100ms detection time frame 628 */ 629 __setup_APIC_LVTT(0xffffffff, 0, 0); 630 631 /* Let the interrupts run */ 632 local_irq_enable(); 633 634 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 635 cpu_relax(); 636 637 local_irq_disable(); 638 639 /* Restore the real event handler */ 640 global_clock_event->event_handler = real_handler; 641 642 /* Build delta t1-t2 as apic timer counts down */ 643 delta = lapic_cal_t1 - lapic_cal_t2; 644 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 645 646 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 647 648 /* we trust the PM based calibration if possible */ 649 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 650 &delta, &deltatsc); 651 652 /* Calculate the scaled math multiplication factor */ 653 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 654 lapic_clockevent.shift); 655 lapic_clockevent.max_delta_ns = 656 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); 657 lapic_clockevent.min_delta_ns = 658 clockevent_delta2ns(0xF, &lapic_clockevent); 659 660 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 661 662 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 663 apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult); 664 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 665 calibration_result); 666 667 if (cpu_has_tsc) { 668 apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 669 "%ld.%04ld MHz.\n", 670 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 671 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 672 } 673 674 apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 675 "%u.%04u MHz.\n", 676 calibration_result / (1000000 / HZ), 677 calibration_result % (1000000 / HZ)); 678 679 /* 680 * Do a sanity check on the APIC calibration result 681 */ 682 if (calibration_result < (1000000 / HZ)) { 683 local_irq_enable(); 684 pr_warning("APIC frequency too slow, disabling apic timer\n"); 685 return -1; 686 } 687 688 levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 689 690 /* 691 * PM timer calibration failed or not turned on 692 * so lets try APIC timer based calibration 693 */ 694 if (!pm_referenced) { 695 apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 696 697 /* 698 * Setup the apic timer manually 699 */ 700 levt->event_handler = lapic_cal_handler; 701 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); 702 lapic_cal_loops = -1; 703 704 /* Let the interrupts run */ 705 local_irq_enable(); 706 707 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 708 cpu_relax(); 709 710 /* Stop the lapic timer */ 711 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); 712 713 /* Jiffies delta */ 714 deltaj = lapic_cal_j2 - lapic_cal_j1; 715 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 716 717 /* Check, if the jiffies result is consistent */ 718 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 719 apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 720 else 721 levt->features |= CLOCK_EVT_FEAT_DUMMY; 722 } else 723 local_irq_enable(); 724 725 if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 726 pr_warning("APIC timer disabled due to verification failure\n"); 727 return -1; 728 } 729 730 return 0; 731 } 732 733 /* 734 * Setup the boot APIC 735 * 736 * Calibrate and verify the result. 737 */ 738 void __init setup_boot_APIC_clock(void) 739 { 740 /* 741 * The local apic timer can be disabled via the kernel 742 * commandline or from the CPU detection code. Register the lapic 743 * timer as a dummy clock event source on SMP systems, so the 744 * broadcast mechanism is used. On UP systems simply ignore it. 745 */ 746 if (disable_apic_timer) { 747 pr_info("Disabling APIC timer\n"); 748 /* No broadcast on UP ! */ 749 if (num_possible_cpus() > 1) { 750 lapic_clockevent.mult = 1; 751 setup_APIC_timer(); 752 } 753 return; 754 } 755 756 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 757 "calibrating APIC timer ...\n"); 758 759 if (calibrate_APIC_clock()) { 760 /* No broadcast on UP ! */ 761 if (num_possible_cpus() > 1) 762 setup_APIC_timer(); 763 return; 764 } 765 766 /* 767 * If nmi_watchdog is set to IO_APIC, we need the 768 * PIT/HPET going. Otherwise register lapic as a dummy 769 * device. 770 */ 771 if (nmi_watchdog != NMI_IO_APIC) 772 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 773 else 774 pr_warning("APIC timer registered as dummy," 775 " due to nmi_watchdog=%d!\n", nmi_watchdog); 776 777 /* Setup the lapic or request the broadcast */ 778 setup_APIC_timer(); 779 } 780 781 void __cpuinit setup_secondary_APIC_clock(void) 782 { 783 setup_APIC_timer(); 784 } 785 786 /* 787 * The guts of the apic timer interrupt 788 */ 789 static void local_apic_timer_interrupt(void) 790 { 791 int cpu = smp_processor_id(); 792 struct clock_event_device *evt = &per_cpu(lapic_events, cpu); 793 794 /* 795 * Normally we should not be here till LAPIC has been initialized but 796 * in some cases like kdump, its possible that there is a pending LAPIC 797 * timer interrupt from previous kernel's context and is delivered in 798 * new kernel the moment interrupts are enabled. 799 * 800 * Interrupts are enabled early and LAPIC is setup much later, hence 801 * its possible that when we get here evt->event_handler is NULL. 802 * Check for event_handler being NULL and discard the interrupt as 803 * spurious. 804 */ 805 if (!evt->event_handler) { 806 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); 807 /* Switch it off */ 808 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); 809 return; 810 } 811 812 /* 813 * the NMI deadlock-detector uses this. 814 */ 815 inc_irq_stat(apic_timer_irqs); 816 817 evt->event_handler(evt); 818 } 819 820 /* 821 * Local APIC timer interrupt. This is the most natural way for doing 822 * local interrupts, but local timer interrupts can be emulated by 823 * broadcast interrupts too. [in case the hw doesn't support APIC timers] 824 * 825 * [ if a single-CPU system runs an SMP kernel then we call the local 826 * interrupt as well. Thus we cannot inline the local irq ... ] 827 */ 828 void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 829 { 830 struct pt_regs *old_regs = set_irq_regs(regs); 831 832 /* 833 * NOTE! We'd better ACK the irq immediately, 834 * because timer handling can be slow. 835 */ 836 ack_APIC_irq(); 837 /* 838 * update_process_times() expects us to have done irq_enter(). 839 * Besides, if we don't timer interrupts ignore the global 840 * interrupt lock, which is the WrongThing (tm) to do. 841 */ 842 exit_idle(); 843 irq_enter(); 844 local_apic_timer_interrupt(); 845 irq_exit(); 846 847 set_irq_regs(old_regs); 848 } 849 850 int setup_profiling_timer(unsigned int multiplier) 851 { 852 return -EINVAL; 853 } 854 855 /* 856 * Local APIC start and shutdown 857 */ 858 859 /** 860 * clear_local_APIC - shutdown the local APIC 861 * 862 * This is called, when a CPU is disabled and before rebooting, so the state of 863 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 864 * leftovers during boot. 865 */ 866 void clear_local_APIC(void) 867 { 868 int maxlvt; 869 u32 v; 870 871 /* APIC hasn't been mapped yet */ 872 if (!x2apic_mode && !apic_phys) 873 return; 874 875 maxlvt = lapic_get_maxlvt(); 876 /* 877 * Masking an LVT entry can trigger a local APIC error 878 * if the vector is zero. Mask LVTERR first to prevent this. 879 */ 880 if (maxlvt >= 3) { 881 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 882 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 883 } 884 /* 885 * Careful: we have to set masks only first to deassert 886 * any level-triggered sources. 887 */ 888 v = apic_read(APIC_LVTT); 889 apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 890 v = apic_read(APIC_LVT0); 891 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 892 v = apic_read(APIC_LVT1); 893 apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 894 if (maxlvt >= 4) { 895 v = apic_read(APIC_LVTPC); 896 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 897 } 898 899 /* lets not touch this if we didn't frob it */ 900 #ifdef CONFIG_X86_THERMAL_VECTOR 901 if (maxlvt >= 5) { 902 v = apic_read(APIC_LVTTHMR); 903 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 904 } 905 #endif 906 #ifdef CONFIG_X86_MCE_INTEL 907 if (maxlvt >= 6) { 908 v = apic_read(APIC_LVTCMCI); 909 if (!(v & APIC_LVT_MASKED)) 910 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 911 } 912 #endif 913 914 /* 915 * Clean APIC state for other OSs: 916 */ 917 apic_write(APIC_LVTT, APIC_LVT_MASKED); 918 apic_write(APIC_LVT0, APIC_LVT_MASKED); 919 apic_write(APIC_LVT1, APIC_LVT_MASKED); 920 if (maxlvt >= 3) 921 apic_write(APIC_LVTERR, APIC_LVT_MASKED); 922 if (maxlvt >= 4) 923 apic_write(APIC_LVTPC, APIC_LVT_MASKED); 924 925 /* Integrated APIC (!82489DX) ? */ 926 if (lapic_is_integrated()) { 927 if (maxlvt > 3) 928 /* Clear ESR due to Pentium errata 3AP and 11AP */ 929 apic_write(APIC_ESR, 0); 930 apic_read(APIC_ESR); 931 } 932 } 933 934 /** 935 * disable_local_APIC - clear and disable the local APIC 936 */ 937 void disable_local_APIC(void) 938 { 939 unsigned int value; 940 941 /* APIC hasn't been mapped yet */ 942 if (!apic_phys) 943 return; 944 945 clear_local_APIC(); 946 947 /* 948 * Disable APIC (implies clearing of registers 949 * for 82489DX!). 950 */ 951 value = apic_read(APIC_SPIV); 952 value &= ~APIC_SPIV_APIC_ENABLED; 953 apic_write(APIC_SPIV, value); 954 955 #ifdef CONFIG_X86_32 956 /* 957 * When LAPIC was disabled by the BIOS and enabled by the kernel, 958 * restore the disabled state. 959 */ 960 if (enabled_via_apicbase) { 961 unsigned int l, h; 962 963 rdmsr(MSR_IA32_APICBASE, l, h); 964 l &= ~MSR_IA32_APICBASE_ENABLE; 965 wrmsr(MSR_IA32_APICBASE, l, h); 966 } 967 #endif 968 } 969 970 /* 971 * If Linux enabled the LAPIC against the BIOS default disable it down before 972 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 973 * not power-off. Additionally clear all LVT entries before disable_local_APIC 974 * for the case where Linux didn't enable the LAPIC. 975 */ 976 void lapic_shutdown(void) 977 { 978 unsigned long flags; 979 980 if (!cpu_has_apic) 981 return; 982 983 local_irq_save(flags); 984 985 #ifdef CONFIG_X86_32 986 if (!enabled_via_apicbase) 987 clear_local_APIC(); 988 else 989 #endif 990 disable_local_APIC(); 991 992 993 local_irq_restore(flags); 994 } 995 996 /* 997 * This is to verify that we're looking at a real local APIC. 998 * Check these against your board if the CPUs aren't getting 999 * started for no apparent reason. 1000 */ 1001 int __init verify_local_APIC(void) 1002 { 1003 unsigned int reg0, reg1; 1004 1005 /* 1006 * The version register is read-only in a real APIC. 1007 */ 1008 reg0 = apic_read(APIC_LVR); 1009 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); 1010 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); 1011 reg1 = apic_read(APIC_LVR); 1012 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); 1013 1014 /* 1015 * The two version reads above should print the same 1016 * numbers. If the second one is different, then we 1017 * poke at a non-APIC. 1018 */ 1019 if (reg1 != reg0) 1020 return 0; 1021 1022 /* 1023 * Check if the version looks reasonably. 1024 */ 1025 reg1 = GET_APIC_VERSION(reg0); 1026 if (reg1 == 0x00 || reg1 == 0xff) 1027 return 0; 1028 reg1 = lapic_get_maxlvt(); 1029 if (reg1 < 0x02 || reg1 == 0xff) 1030 return 0; 1031 1032 /* 1033 * The ID register is read/write in a real APIC. 1034 */ 1035 reg0 = apic_read(APIC_ID); 1036 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); 1037 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask); 1038 reg1 = apic_read(APIC_ID); 1039 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); 1040 apic_write(APIC_ID, reg0); 1041 if (reg1 != (reg0 ^ apic->apic_id_mask)) 1042 return 0; 1043 1044 /* 1045 * The next two are just to see if we have sane values. 1046 * They're only really relevant if we're in Virtual Wire 1047 * compatibility mode, but most boxes are anymore. 1048 */ 1049 reg0 = apic_read(APIC_LVT0); 1050 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); 1051 reg1 = apic_read(APIC_LVT1); 1052 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); 1053 1054 return 1; 1055 } 1056 1057 /** 1058 * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1059 */ 1060 void __init sync_Arb_IDs(void) 1061 { 1062 /* 1063 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1064 * needed on AMD. 1065 */ 1066 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1067 return; 1068 1069 /* 1070 * Wait for idle. 1071 */ 1072 apic_wait_icr_idle(); 1073 1074 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1075 apic_write(APIC_ICR, APIC_DEST_ALLINC | 1076 APIC_INT_LEVELTRIG | APIC_DM_INIT); 1077 } 1078 1079 /* 1080 * An initial setup of the virtual wire mode. 1081 */ 1082 void __init init_bsp_APIC(void) 1083 { 1084 unsigned int value; 1085 1086 /* 1087 * Don't do the setup now if we have a SMP BIOS as the 1088 * through-I/O-APIC virtual wire mode might be active. 1089 */ 1090 if (smp_found_config || !cpu_has_apic) 1091 return; 1092 1093 /* 1094 * Do not trust the local APIC being empty at bootup. 1095 */ 1096 clear_local_APIC(); 1097 1098 /* 1099 * Enable APIC. 1100 */ 1101 value = apic_read(APIC_SPIV); 1102 value &= ~APIC_VECTOR_MASK; 1103 value |= APIC_SPIV_APIC_ENABLED; 1104 1105 #ifdef CONFIG_X86_32 1106 /* This bit is reserved on P4/Xeon and should be cleared */ 1107 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1108 (boot_cpu_data.x86 == 15)) 1109 value &= ~APIC_SPIV_FOCUS_DISABLED; 1110 else 1111 #endif 1112 value |= APIC_SPIV_FOCUS_DISABLED; 1113 value |= SPURIOUS_APIC_VECTOR; 1114 apic_write(APIC_SPIV, value); 1115 1116 /* 1117 * Set up the virtual wire mode. 1118 */ 1119 apic_write(APIC_LVT0, APIC_DM_EXTINT); 1120 value = APIC_DM_NMI; 1121 if (!lapic_is_integrated()) /* 82489DX */ 1122 value |= APIC_LVT_LEVEL_TRIGGER; 1123 apic_write(APIC_LVT1, value); 1124 } 1125 1126 static void __cpuinit lapic_setup_esr(void) 1127 { 1128 unsigned int oldvalue, value, maxlvt; 1129 1130 if (!lapic_is_integrated()) { 1131 pr_info("No ESR for 82489DX.\n"); 1132 return; 1133 } 1134 1135 if (apic->disable_esr) { 1136 /* 1137 * Something untraceable is creating bad interrupts on 1138 * secondary quads ... for the moment, just leave the 1139 * ESR disabled - we can't do anything useful with the 1140 * errors anyway - mbligh 1141 */ 1142 pr_info("Leaving ESR disabled.\n"); 1143 return; 1144 } 1145 1146 maxlvt = lapic_get_maxlvt(); 1147 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1148 apic_write(APIC_ESR, 0); 1149 oldvalue = apic_read(APIC_ESR); 1150 1151 /* enables sending errors */ 1152 value = ERROR_APIC_VECTOR; 1153 apic_write(APIC_LVTERR, value); 1154 1155 /* 1156 * spec says clear errors after enabling vector. 1157 */ 1158 if (maxlvt > 3) 1159 apic_write(APIC_ESR, 0); 1160 value = apic_read(APIC_ESR); 1161 if (value != oldvalue) 1162 apic_printk(APIC_VERBOSE, "ESR value before enabling " 1163 "vector: 0x%08x after: 0x%08x\n", 1164 oldvalue, value); 1165 } 1166 1167 1168 /** 1169 * setup_local_APIC - setup the local APIC 1170 */ 1171 void __cpuinit setup_local_APIC(void) 1172 { 1173 unsigned int value; 1174 int i, j; 1175 1176 if (disable_apic) { 1177 arch_disable_smp_support(); 1178 return; 1179 } 1180 1181 #ifdef CONFIG_X86_32 1182 /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1183 if (lapic_is_integrated() && apic->disable_esr) { 1184 apic_write(APIC_ESR, 0); 1185 apic_write(APIC_ESR, 0); 1186 apic_write(APIC_ESR, 0); 1187 apic_write(APIC_ESR, 0); 1188 } 1189 #endif 1190 perf_counters_lapic_init(); 1191 1192 preempt_disable(); 1193 1194 /* 1195 * Double-check whether this APIC is really registered. 1196 * This is meaningless in clustered apic mode, so we skip it. 1197 */ 1198 if (!apic->apic_id_registered()) 1199 BUG(); 1200 1201 /* 1202 * Intel recommends to set DFR, LDR and TPR before enabling 1203 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1204 * document number 292116). So here it goes... 1205 */ 1206 apic->init_apic_ldr(); 1207 1208 /* 1209 * Set Task Priority to 'accept all'. We never change this 1210 * later on. 1211 */ 1212 value = apic_read(APIC_TASKPRI); 1213 value &= ~APIC_TPRI_MASK; 1214 apic_write(APIC_TASKPRI, value); 1215 1216 /* 1217 * After a crash, we no longer service the interrupts and a pending 1218 * interrupt from previous kernel might still have ISR bit set. 1219 * 1220 * Most probably by now CPU has serviced that pending interrupt and 1221 * it might not have done the ack_APIC_irq() because it thought, 1222 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1223 * does not clear the ISR bit and cpu thinks it has already serivced 1224 * the interrupt. Hence a vector might get locked. It was noticed 1225 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1226 */ 1227 for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1228 value = apic_read(APIC_ISR + i*0x10); 1229 for (j = 31; j >= 0; j--) { 1230 if (value & (1<<j)) 1231 ack_APIC_irq(); 1232 } 1233 } 1234 1235 /* 1236 * Now that we are all set up, enable the APIC 1237 */ 1238 value = apic_read(APIC_SPIV); 1239 value &= ~APIC_VECTOR_MASK; 1240 /* 1241 * Enable APIC 1242 */ 1243 value |= APIC_SPIV_APIC_ENABLED; 1244 1245 #ifdef CONFIG_X86_32 1246 /* 1247 * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1248 * certain networking cards. If high frequency interrupts are 1249 * happening on a particular IOAPIC pin, plus the IOAPIC routing 1250 * entry is masked/unmasked at a high rate as well then sooner or 1251 * later IOAPIC line gets 'stuck', no more interrupts are received 1252 * from the device. If focus CPU is disabled then the hang goes 1253 * away, oh well :-( 1254 * 1255 * [ This bug can be reproduced easily with a level-triggered 1256 * PCI Ne2000 networking cards and PII/PIII processors, dual 1257 * BX chipset. ] 1258 */ 1259 /* 1260 * Actually disabling the focus CPU check just makes the hang less 1261 * frequent as it makes the interrupt distributon model be more 1262 * like LRU than MRU (the short-term load is more even across CPUs). 1263 * See also the comment in end_level_ioapic_irq(). --macro 1264 */ 1265 1266 /* 1267 * - enable focus processor (bit==0) 1268 * - 64bit mode always use processor focus 1269 * so no need to set it 1270 */ 1271 value &= ~APIC_SPIV_FOCUS_DISABLED; 1272 #endif 1273 1274 /* 1275 * Set spurious IRQ vector 1276 */ 1277 value |= SPURIOUS_APIC_VECTOR; 1278 apic_write(APIC_SPIV, value); 1279 1280 /* 1281 * Set up LVT0, LVT1: 1282 * 1283 * set up through-local-APIC on the BP's LINT0. This is not 1284 * strictly necessary in pure symmetric-IO mode, but sometimes 1285 * we delegate interrupts to the 8259A. 1286 */ 1287 /* 1288 * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1289 */ 1290 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1291 if (!smp_processor_id() && (pic_mode || !value)) { 1292 value = APIC_DM_EXTINT; 1293 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", 1294 smp_processor_id()); 1295 } else { 1296 value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1297 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", 1298 smp_processor_id()); 1299 } 1300 apic_write(APIC_LVT0, value); 1301 1302 /* 1303 * only the BP should see the LINT1 NMI signal, obviously. 1304 */ 1305 if (!smp_processor_id()) 1306 value = APIC_DM_NMI; 1307 else 1308 value = APIC_DM_NMI | APIC_LVT_MASKED; 1309 if (!lapic_is_integrated()) /* 82489DX */ 1310 value |= APIC_LVT_LEVEL_TRIGGER; 1311 apic_write(APIC_LVT1, value); 1312 1313 preempt_enable(); 1314 1315 #ifdef CONFIG_X86_MCE_INTEL 1316 /* Recheck CMCI information after local APIC is up on CPU #0 */ 1317 if (smp_processor_id() == 0) 1318 cmci_recheck(); 1319 #endif 1320 } 1321 1322 void __cpuinit end_local_APIC_setup(void) 1323 { 1324 lapic_setup_esr(); 1325 1326 #ifdef CONFIG_X86_32 1327 { 1328 unsigned int value; 1329 /* Disable the local apic timer */ 1330 value = apic_read(APIC_LVTT); 1331 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1332 apic_write(APIC_LVTT, value); 1333 } 1334 #endif 1335 1336 setup_apic_nmi_watchdog(NULL); 1337 apic_pm_activate(); 1338 } 1339 1340 #ifdef CONFIG_X86_X2APIC 1341 void check_x2apic(void) 1342 { 1343 if (x2apic_enabled()) { 1344 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); 1345 x2apic_preenabled = x2apic_mode = 1; 1346 } 1347 } 1348 1349 void enable_x2apic(void) 1350 { 1351 int msr, msr2; 1352 1353 if (!x2apic_mode) 1354 return; 1355 1356 rdmsr(MSR_IA32_APICBASE, msr, msr2); 1357 if (!(msr & X2APIC_ENABLE)) { 1358 pr_info("Enabling x2apic\n"); 1359 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); 1360 } 1361 } 1362 #endif /* CONFIG_X86_X2APIC */ 1363 1364 void __init enable_IR_x2apic(void) 1365 { 1366 #ifdef CONFIG_INTR_REMAP 1367 int ret; 1368 unsigned long flags; 1369 struct IO_APIC_route_entry **ioapic_entries = NULL; 1370 1371 ret = dmar_table_init(); 1372 if (ret) { 1373 pr_debug("dmar_table_init() failed with %d:\n", ret); 1374 goto ir_failed; 1375 } 1376 1377 if (!intr_remapping_supported()) { 1378 pr_debug("intr-remapping not supported\n"); 1379 goto ir_failed; 1380 } 1381 1382 1383 if (!x2apic_preenabled && skip_ioapic_setup) { 1384 pr_info("Skipped enabling intr-remap because of skipping " 1385 "io-apic setup\n"); 1386 return; 1387 } 1388 1389 ioapic_entries = alloc_ioapic_entries(); 1390 if (!ioapic_entries) { 1391 pr_info("Allocate ioapic_entries failed: %d\n", ret); 1392 goto end; 1393 } 1394 1395 ret = save_IO_APIC_setup(ioapic_entries); 1396 if (ret) { 1397 pr_info("Saving IO-APIC state failed: %d\n", ret); 1398 goto end; 1399 } 1400 1401 local_irq_save(flags); 1402 mask_IO_APIC_setup(ioapic_entries); 1403 mask_8259A(); 1404 1405 ret = enable_intr_remapping(x2apic_supported()); 1406 if (ret) 1407 goto end_restore; 1408 1409 pr_info("Enabled Interrupt-remapping\n"); 1410 1411 if (x2apic_supported() && !x2apic_mode) { 1412 x2apic_mode = 1; 1413 enable_x2apic(); 1414 pr_info("Enabled x2apic\n"); 1415 } 1416 1417 end_restore: 1418 if (ret) 1419 /* 1420 * IR enabling failed 1421 */ 1422 restore_IO_APIC_setup(ioapic_entries); 1423 1424 unmask_8259A(); 1425 local_irq_restore(flags); 1426 1427 end: 1428 if (ioapic_entries) 1429 free_ioapic_entries(ioapic_entries); 1430 1431 if (!ret) 1432 return; 1433 1434 ir_failed: 1435 if (x2apic_preenabled) 1436 panic("x2apic enabled by bios. But IR enabling failed"); 1437 else if (cpu_has_x2apic) 1438 pr_info("Not enabling x2apic,Intr-remapping\n"); 1439 #else 1440 if (!cpu_has_x2apic) 1441 return; 1442 1443 if (x2apic_preenabled) 1444 panic("x2apic enabled prior OS handover," 1445 " enable CONFIG_X86_X2APIC, CONFIG_INTR_REMAP"); 1446 #endif 1447 1448 return; 1449 } 1450 1451 1452 #ifdef CONFIG_X86_64 1453 /* 1454 * Detect and enable local APICs on non-SMP boards. 1455 * Original code written by Keir Fraser. 1456 * On AMD64 we trust the BIOS - if it says no APIC it is likely 1457 * not correctly set up (usually the APIC timer won't work etc.) 1458 */ 1459 static int __init detect_init_APIC(void) 1460 { 1461 if (!cpu_has_apic) { 1462 pr_info("No local APIC present\n"); 1463 return -1; 1464 } 1465 1466 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1467 return 0; 1468 } 1469 #else 1470 /* 1471 * Detect and initialize APIC 1472 */ 1473 static int __init detect_init_APIC(void) 1474 { 1475 u32 h, l, features; 1476 1477 /* Disabled by kernel option? */ 1478 if (disable_apic) 1479 return -1; 1480 1481 switch (boot_cpu_data.x86_vendor) { 1482 case X86_VENDOR_AMD: 1483 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1484 (boot_cpu_data.x86 >= 15)) 1485 break; 1486 goto no_apic; 1487 case X86_VENDOR_INTEL: 1488 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1489 (boot_cpu_data.x86 == 5 && cpu_has_apic)) 1490 break; 1491 goto no_apic; 1492 default: 1493 goto no_apic; 1494 } 1495 1496 if (!cpu_has_apic) { 1497 /* 1498 * Over-ride BIOS and try to enable the local APIC only if 1499 * "lapic" specified. 1500 */ 1501 if (!force_enable_local_apic) { 1502 pr_info("Local APIC disabled by BIOS -- " 1503 "you can enable it with \"lapic\"\n"); 1504 return -1; 1505 } 1506 /* 1507 * Some BIOSes disable the local APIC in the APIC_BASE 1508 * MSR. This can only be done in software for Intel P6 or later 1509 * and AMD K7 (Model > 1) or later. 1510 */ 1511 rdmsr(MSR_IA32_APICBASE, l, h); 1512 if (!(l & MSR_IA32_APICBASE_ENABLE)) { 1513 pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 1514 l &= ~MSR_IA32_APICBASE_BASE; 1515 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; 1516 wrmsr(MSR_IA32_APICBASE, l, h); 1517 enabled_via_apicbase = 1; 1518 } 1519 } 1520 /* 1521 * The APIC feature bit should now be enabled 1522 * in `cpuid' 1523 */ 1524 features = cpuid_edx(1); 1525 if (!(features & (1 << X86_FEATURE_APIC))) { 1526 pr_warning("Could not enable APIC!\n"); 1527 return -1; 1528 } 1529 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1530 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1531 1532 /* The BIOS may have set up the APIC at some other address */ 1533 rdmsr(MSR_IA32_APICBASE, l, h); 1534 if (l & MSR_IA32_APICBASE_ENABLE) 1535 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1536 1537 pr_info("Found and enabled local APIC!\n"); 1538 1539 apic_pm_activate(); 1540 1541 return 0; 1542 1543 no_apic: 1544 pr_info("No local APIC present or hardware disabled\n"); 1545 return -1; 1546 } 1547 #endif 1548 1549 #ifdef CONFIG_X86_64 1550 void __init early_init_lapic_mapping(void) 1551 { 1552 unsigned long phys_addr; 1553 1554 /* 1555 * If no local APIC can be found then go out 1556 * : it means there is no mpatable and MADT 1557 */ 1558 if (!smp_found_config) 1559 return; 1560 1561 phys_addr = mp_lapic_addr; 1562 1563 set_fixmap_nocache(FIX_APIC_BASE, phys_addr); 1564 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 1565 APIC_BASE, phys_addr); 1566 1567 /* 1568 * Fetch the APIC ID of the BSP in case we have a 1569 * default configuration (or the MP table is broken). 1570 */ 1571 boot_cpu_physical_apicid = read_apic_id(); 1572 } 1573 #endif 1574 1575 /** 1576 * init_apic_mappings - initialize APIC mappings 1577 */ 1578 void __init init_apic_mappings(void) 1579 { 1580 unsigned int new_apicid; 1581 1582 if (x2apic_mode) { 1583 boot_cpu_physical_apicid = read_apic_id(); 1584 return; 1585 } 1586 1587 /* If no local APIC can be found return early */ 1588 if (!smp_found_config && detect_init_APIC()) { 1589 /* lets NOP'ify apic operations */ 1590 pr_info("APIC: disable apic facility\n"); 1591 apic_disable(); 1592 } else { 1593 apic_phys = mp_lapic_addr; 1594 1595 /* 1596 * acpi lapic path already maps that address in 1597 * acpi_register_lapic_address() 1598 */ 1599 if (!acpi_lapic) 1600 set_fixmap_nocache(FIX_APIC_BASE, apic_phys); 1601 1602 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", 1603 APIC_BASE, apic_phys); 1604 } 1605 1606 /* 1607 * Fetch the APIC ID of the BSP in case we have a 1608 * default configuration (or the MP table is broken). 1609 */ 1610 new_apicid = read_apic_id(); 1611 if (boot_cpu_physical_apicid != new_apicid) { 1612 boot_cpu_physical_apicid = new_apicid; 1613 /* 1614 * yeah -- we lie about apic_version 1615 * in case if apic was disabled via boot option 1616 * but it's not a problem for SMP compiled kernel 1617 * since smp_sanity_check is prepared for such a case 1618 * and disable smp mode 1619 */ 1620 apic_version[new_apicid] = 1621 GET_APIC_VERSION(apic_read(APIC_LVR)); 1622 } 1623 } 1624 1625 /* 1626 * This initializes the IO-APIC and APIC hardware if this is 1627 * a UP kernel. 1628 */ 1629 int apic_version[MAX_APICS]; 1630 1631 int __init APIC_init_uniprocessor(void) 1632 { 1633 if (disable_apic) { 1634 pr_info("Apic disabled\n"); 1635 return -1; 1636 } 1637 #ifdef CONFIG_X86_64 1638 if (!cpu_has_apic) { 1639 disable_apic = 1; 1640 pr_info("Apic disabled by BIOS\n"); 1641 return -1; 1642 } 1643 #else 1644 if (!smp_found_config && !cpu_has_apic) 1645 return -1; 1646 1647 /* 1648 * Complain if the BIOS pretends there is one. 1649 */ 1650 if (!cpu_has_apic && 1651 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 1652 pr_err("BIOS bug, local APIC 0x%x not detected!...\n", 1653 boot_cpu_physical_apicid); 1654 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1655 return -1; 1656 } 1657 #endif 1658 1659 enable_IR_x2apic(); 1660 #ifdef CONFIG_X86_64 1661 default_setup_apic_routing(); 1662 #endif 1663 1664 verify_local_APIC(); 1665 connect_bsp_APIC(); 1666 1667 #ifdef CONFIG_X86_64 1668 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); 1669 #else 1670 /* 1671 * Hack: In case of kdump, after a crash, kernel might be booting 1672 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 1673 * might be zero if read from MP tables. Get it from LAPIC. 1674 */ 1675 # ifdef CONFIG_CRASH_DUMP 1676 boot_cpu_physical_apicid = read_apic_id(); 1677 # endif 1678 #endif 1679 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1680 setup_local_APIC(); 1681 1682 #ifdef CONFIG_X86_IO_APIC 1683 /* 1684 * Now enable IO-APICs, actually call clear_IO_APIC 1685 * We need clear_IO_APIC before enabling error vector 1686 */ 1687 if (!skip_ioapic_setup && nr_ioapics) 1688 enable_IO_APIC(); 1689 #endif 1690 1691 end_local_APIC_setup(); 1692 1693 #ifdef CONFIG_X86_IO_APIC 1694 if (smp_found_config && !skip_ioapic_setup && nr_ioapics) 1695 setup_IO_APIC(); 1696 else { 1697 nr_ioapics = 0; 1698 localise_nmi_watchdog(); 1699 } 1700 #else 1701 localise_nmi_watchdog(); 1702 #endif 1703 1704 setup_boot_clock(); 1705 #ifdef CONFIG_X86_64 1706 check_nmi_watchdog(); 1707 #endif 1708 1709 return 0; 1710 } 1711 1712 /* 1713 * Local APIC interrupts 1714 */ 1715 1716 /* 1717 * This interrupt should _never_ happen with our APIC/SMP architecture 1718 */ 1719 void smp_spurious_interrupt(struct pt_regs *regs) 1720 { 1721 u32 v; 1722 1723 exit_idle(); 1724 irq_enter(); 1725 /* 1726 * Check if this really is a spurious interrupt and ACK it 1727 * if it is a vectored one. Just in case... 1728 * Spurious interrupts should not be ACKed. 1729 */ 1730 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); 1731 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) 1732 ack_APIC_irq(); 1733 1734 inc_irq_stat(irq_spurious_count); 1735 1736 /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 1737 pr_info("spurious APIC interrupt on CPU#%d, " 1738 "should never happen.\n", smp_processor_id()); 1739 irq_exit(); 1740 } 1741 1742 /* 1743 * This interrupt should never happen with our APIC/SMP architecture 1744 */ 1745 void smp_error_interrupt(struct pt_regs *regs) 1746 { 1747 u32 v, v1; 1748 1749 exit_idle(); 1750 irq_enter(); 1751 /* First tickle the hardware, only then report what went on. -- REW */ 1752 v = apic_read(APIC_ESR); 1753 apic_write(APIC_ESR, 0); 1754 v1 = apic_read(APIC_ESR); 1755 ack_APIC_irq(); 1756 atomic_inc(&irq_err_count); 1757 1758 /* 1759 * Here is what the APIC error bits mean: 1760 * 0: Send CS error 1761 * 1: Receive CS error 1762 * 2: Send accept error 1763 * 3: Receive accept error 1764 * 4: Reserved 1765 * 5: Send illegal vector 1766 * 6: Received illegal vector 1767 * 7: Illegal register address 1768 */ 1769 pr_debug("APIC error on CPU%d: %02x(%02x)\n", 1770 smp_processor_id(), v , v1); 1771 irq_exit(); 1772 } 1773 1774 /** 1775 * connect_bsp_APIC - attach the APIC to the interrupt system 1776 */ 1777 void __init connect_bsp_APIC(void) 1778 { 1779 #ifdef CONFIG_X86_32 1780 if (pic_mode) { 1781 /* 1782 * Do not trust the local APIC being empty at bootup. 1783 */ 1784 clear_local_APIC(); 1785 /* 1786 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 1787 * local APIC to INT and NMI lines. 1788 */ 1789 apic_printk(APIC_VERBOSE, "leaving PIC mode, " 1790 "enabling APIC mode.\n"); 1791 imcr_pic_to_apic(); 1792 } 1793 #endif 1794 if (apic->enable_apic_mode) 1795 apic->enable_apic_mode(); 1796 } 1797 1798 /** 1799 * disconnect_bsp_APIC - detach the APIC from the interrupt system 1800 * @virt_wire_setup: indicates, whether virtual wire mode is selected 1801 * 1802 * Virtual wire mode is necessary to deliver legacy interrupts even when the 1803 * APIC is disabled. 1804 */ 1805 void disconnect_bsp_APIC(int virt_wire_setup) 1806 { 1807 unsigned int value; 1808 1809 #ifdef CONFIG_X86_32 1810 if (pic_mode) { 1811 /* 1812 * Put the board back into PIC mode (has an effect only on 1813 * certain older boards). Note that APIC interrupts, including 1814 * IPIs, won't work beyond this point! The only exception are 1815 * INIT IPIs. 1816 */ 1817 apic_printk(APIC_VERBOSE, "disabling APIC mode, " 1818 "entering PIC mode.\n"); 1819 imcr_apic_to_pic(); 1820 return; 1821 } 1822 #endif 1823 1824 /* Go back to Virtual Wire compatibility mode */ 1825 1826 /* For the spurious interrupt use vector F, and enable it */ 1827 value = apic_read(APIC_SPIV); 1828 value &= ~APIC_VECTOR_MASK; 1829 value |= APIC_SPIV_APIC_ENABLED; 1830 value |= 0xf; 1831 apic_write(APIC_SPIV, value); 1832 1833 if (!virt_wire_setup) { 1834 /* 1835 * For LVT0 make it edge triggered, active high, 1836 * external and enabled 1837 */ 1838 value = apic_read(APIC_LVT0); 1839 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1840 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1841 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1842 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1843 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 1844 apic_write(APIC_LVT0, value); 1845 } else { 1846 /* Disable LVT0 */ 1847 apic_write(APIC_LVT0, APIC_LVT_MASKED); 1848 } 1849 1850 /* 1851 * For LVT1 make it edge triggered, active high, 1852 * nmi and enabled 1853 */ 1854 value = apic_read(APIC_LVT1); 1855 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1856 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1857 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1858 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1859 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 1860 apic_write(APIC_LVT1, value); 1861 } 1862 1863 void __cpuinit generic_processor_info(int apicid, int version) 1864 { 1865 int cpu; 1866 1867 /* 1868 * Validate version 1869 */ 1870 if (version == 0x0) { 1871 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! " 1872 "fixing up to 0x10. (tell your hw vendor)\n", 1873 version); 1874 version = 0x10; 1875 } 1876 apic_version[apicid] = version; 1877 1878 if (num_processors >= nr_cpu_ids) { 1879 int max = nr_cpu_ids; 1880 int thiscpu = max + disabled_cpus; 1881 1882 pr_warning( 1883 "ACPI: NR_CPUS/possible_cpus limit of %i reached." 1884 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 1885 1886 disabled_cpus++; 1887 return; 1888 } 1889 1890 num_processors++; 1891 cpu = cpumask_next_zero(-1, cpu_present_mask); 1892 1893 if (version != apic_version[boot_cpu_physical_apicid]) 1894 WARN_ONCE(1, 1895 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n", 1896 apic_version[boot_cpu_physical_apicid], cpu, version); 1897 1898 physid_set(apicid, phys_cpu_present_map); 1899 if (apicid == boot_cpu_physical_apicid) { 1900 /* 1901 * x86_bios_cpu_apicid is required to have processors listed 1902 * in same order as logical cpu numbers. Hence the first 1903 * entry is BSP, and so on. 1904 */ 1905 cpu = 0; 1906 } 1907 if (apicid > max_physical_apicid) 1908 max_physical_apicid = apicid; 1909 1910 #ifdef CONFIG_X86_32 1911 /* 1912 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y 1913 * but we need to work other dependencies like SMP_SUSPEND etc 1914 * before this can be done without some confusion. 1915 * if (CPU_HOTPLUG_ENABLED || num_processors > 8) 1916 * - Ashok Raj <ashok.raj@intel.com> 1917 */ 1918 if (max_physical_apicid >= 8) { 1919 switch (boot_cpu_data.x86_vendor) { 1920 case X86_VENDOR_INTEL: 1921 if (!APIC_XAPIC(version)) { 1922 def_to_bigsmp = 0; 1923 break; 1924 } 1925 /* If P4 and above fall through */ 1926 case X86_VENDOR_AMD: 1927 def_to_bigsmp = 1; 1928 } 1929 } 1930 #endif 1931 1932 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 1933 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 1934 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 1935 #endif 1936 1937 set_cpu_possible(cpu, true); 1938 set_cpu_present(cpu, true); 1939 } 1940 1941 int hard_smp_processor_id(void) 1942 { 1943 return read_apic_id(); 1944 } 1945 1946 void default_init_apic_ldr(void) 1947 { 1948 unsigned long val; 1949 1950 apic_write(APIC_DFR, APIC_DFR_VALUE); 1951 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; 1952 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); 1953 apic_write(APIC_LDR, val); 1954 } 1955 1956 #ifdef CONFIG_X86_32 1957 int default_apicid_to_node(int logical_apicid) 1958 { 1959 #ifdef CONFIG_SMP 1960 return apicid_2_node[hard_smp_processor_id()]; 1961 #else 1962 return 0; 1963 #endif 1964 } 1965 #endif 1966 1967 /* 1968 * Power management 1969 */ 1970 #ifdef CONFIG_PM 1971 1972 static struct { 1973 /* 1974 * 'active' is true if the local APIC was enabled by us and 1975 * not the BIOS; this signifies that we are also responsible 1976 * for disabling it before entering apm/acpi suspend 1977 */ 1978 int active; 1979 /* r/w apic fields */ 1980 unsigned int apic_id; 1981 unsigned int apic_taskpri; 1982 unsigned int apic_ldr; 1983 unsigned int apic_dfr; 1984 unsigned int apic_spiv; 1985 unsigned int apic_lvtt; 1986 unsigned int apic_lvtpc; 1987 unsigned int apic_lvt0; 1988 unsigned int apic_lvt1; 1989 unsigned int apic_lvterr; 1990 unsigned int apic_tmict; 1991 unsigned int apic_tdcr; 1992 unsigned int apic_thmr; 1993 } apic_pm_state; 1994 1995 static int lapic_suspend(struct sys_device *dev, pm_message_t state) 1996 { 1997 unsigned long flags; 1998 int maxlvt; 1999 2000 if (!apic_pm_state.active) 2001 return 0; 2002 2003 maxlvt = lapic_get_maxlvt(); 2004 2005 apic_pm_state.apic_id = apic_read(APIC_ID); 2006 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2007 apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2008 apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2009 apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2010 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2011 if (maxlvt >= 4) 2012 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2013 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2014 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2015 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2016 apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2017 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 2018 #ifdef CONFIG_X86_THERMAL_VECTOR 2019 if (maxlvt >= 5) 2020 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2021 #endif 2022 2023 local_irq_save(flags); 2024 disable_local_APIC(); 2025 2026 if (intr_remapping_enabled) 2027 disable_intr_remapping(); 2028 2029 local_irq_restore(flags); 2030 return 0; 2031 } 2032 2033 static int lapic_resume(struct sys_device *dev) 2034 { 2035 unsigned int l, h; 2036 unsigned long flags; 2037 int maxlvt; 2038 int ret = 0; 2039 struct IO_APIC_route_entry **ioapic_entries = NULL; 2040 2041 if (!apic_pm_state.active) 2042 return 0; 2043 2044 local_irq_save(flags); 2045 if (intr_remapping_enabled) { 2046 ioapic_entries = alloc_ioapic_entries(); 2047 if (!ioapic_entries) { 2048 WARN(1, "Alloc ioapic_entries in lapic resume failed."); 2049 ret = -ENOMEM; 2050 goto restore; 2051 } 2052 2053 ret = save_IO_APIC_setup(ioapic_entries); 2054 if (ret) { 2055 WARN(1, "Saving IO-APIC state failed: %d\n", ret); 2056 free_ioapic_entries(ioapic_entries); 2057 goto restore; 2058 } 2059 2060 mask_IO_APIC_setup(ioapic_entries); 2061 mask_8259A(); 2062 } 2063 2064 if (x2apic_mode) 2065 enable_x2apic(); 2066 else { 2067 /* 2068 * Make sure the APICBASE points to the right address 2069 * 2070 * FIXME! This will be wrong if we ever support suspend on 2071 * SMP! We'll need to do this as part of the CPU restore! 2072 */ 2073 rdmsr(MSR_IA32_APICBASE, l, h); 2074 l &= ~MSR_IA32_APICBASE_BASE; 2075 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2076 wrmsr(MSR_IA32_APICBASE, l, h); 2077 } 2078 2079 maxlvt = lapic_get_maxlvt(); 2080 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2081 apic_write(APIC_ID, apic_pm_state.apic_id); 2082 apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2083 apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2084 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2085 apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2086 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2087 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2088 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) 2089 if (maxlvt >= 5) 2090 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2091 #endif 2092 if (maxlvt >= 4) 2093 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2094 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2095 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2096 apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2097 apic_write(APIC_ESR, 0); 2098 apic_read(APIC_ESR); 2099 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2100 apic_write(APIC_ESR, 0); 2101 apic_read(APIC_ESR); 2102 2103 if (intr_remapping_enabled) { 2104 reenable_intr_remapping(x2apic_mode); 2105 unmask_8259A(); 2106 restore_IO_APIC_setup(ioapic_entries); 2107 free_ioapic_entries(ioapic_entries); 2108 } 2109 restore: 2110 local_irq_restore(flags); 2111 2112 return ret; 2113 } 2114 2115 /* 2116 * This device has no shutdown method - fully functioning local APICs 2117 * are needed on every CPU up until machine_halt/restart/poweroff. 2118 */ 2119 2120 static struct sysdev_class lapic_sysclass = { 2121 .name = "lapic", 2122 .resume = lapic_resume, 2123 .suspend = lapic_suspend, 2124 }; 2125 2126 static struct sys_device device_lapic = { 2127 .id = 0, 2128 .cls = &lapic_sysclass, 2129 }; 2130 2131 static void __cpuinit apic_pm_activate(void) 2132 { 2133 apic_pm_state.active = 1; 2134 } 2135 2136 static int __init init_lapic_sysfs(void) 2137 { 2138 int error; 2139 2140 if (!cpu_has_apic) 2141 return 0; 2142 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2143 2144 error = sysdev_class_register(&lapic_sysclass); 2145 if (!error) 2146 error = sysdev_register(&device_lapic); 2147 return error; 2148 } 2149 2150 /* local apic needs to resume before other devices access its registers. */ 2151 core_initcall(init_lapic_sysfs); 2152 2153 #else /* CONFIG_PM */ 2154 2155 static void apic_pm_activate(void) { } 2156 2157 #endif /* CONFIG_PM */ 2158 2159 #ifdef CONFIG_X86_64 2160 2161 static int __cpuinit apic_cluster_num(void) 2162 { 2163 int i, clusters, zeros; 2164 unsigned id; 2165 u16 *bios_cpu_apicid; 2166 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); 2167 2168 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); 2169 bitmap_zero(clustermap, NUM_APIC_CLUSTERS); 2170 2171 for (i = 0; i < nr_cpu_ids; i++) { 2172 /* are we being called early in kernel startup? */ 2173 if (bios_cpu_apicid) { 2174 id = bios_cpu_apicid[i]; 2175 } else if (i < nr_cpu_ids) { 2176 if (cpu_present(i)) 2177 id = per_cpu(x86_bios_cpu_apicid, i); 2178 else 2179 continue; 2180 } else 2181 break; 2182 2183 if (id != BAD_APICID) 2184 __set_bit(APIC_CLUSTERID(id), clustermap); 2185 } 2186 2187 /* Problem: Partially populated chassis may not have CPUs in some of 2188 * the APIC clusters they have been allocated. Only present CPUs have 2189 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. 2190 * Since clusters are allocated sequentially, count zeros only if 2191 * they are bounded by ones. 2192 */ 2193 clusters = 0; 2194 zeros = 0; 2195 for (i = 0; i < NUM_APIC_CLUSTERS; i++) { 2196 if (test_bit(i, clustermap)) { 2197 clusters += 1 + zeros; 2198 zeros = 0; 2199 } else 2200 ++zeros; 2201 } 2202 2203 return clusters; 2204 } 2205 2206 static int __cpuinitdata multi_checked; 2207 static int __cpuinitdata multi; 2208 2209 static int __cpuinit set_multi(const struct dmi_system_id *d) 2210 { 2211 if (multi) 2212 return 0; 2213 pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2214 multi = 1; 2215 return 0; 2216 } 2217 2218 static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = { 2219 { 2220 .callback = set_multi, 2221 .ident = "IBM System Summit2", 2222 .matches = { 2223 DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2224 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2225 }, 2226 }, 2227 {} 2228 }; 2229 2230 static void __cpuinit dmi_check_multi(void) 2231 { 2232 if (multi_checked) 2233 return; 2234 2235 dmi_check_system(multi_dmi_table); 2236 multi_checked = 1; 2237 } 2238 2239 /* 2240 * apic_is_clustered_box() -- Check if we can expect good TSC 2241 * 2242 * Thus far, the major user of this is IBM's Summit2 series: 2243 * Clustered boxes may have unsynced TSC problems if they are 2244 * multi-chassis. 2245 * Use DMI to check them 2246 */ 2247 __cpuinit int apic_is_clustered_box(void) 2248 { 2249 dmi_check_multi(); 2250 if (multi) 2251 return 1; 2252 2253 if (!is_vsmp_box()) 2254 return 0; 2255 2256 /* 2257 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are 2258 * not guaranteed to be synced between boards 2259 */ 2260 if (apic_cluster_num() > 1) 2261 return 1; 2262 2263 return 0; 2264 } 2265 #endif 2266 2267 /* 2268 * APIC command line parameters 2269 */ 2270 static int __init setup_disableapic(char *arg) 2271 { 2272 disable_apic = 1; 2273 setup_clear_cpu_cap(X86_FEATURE_APIC); 2274 return 0; 2275 } 2276 early_param("disableapic", setup_disableapic); 2277 2278 /* same as disableapic, for compatibility */ 2279 static int __init setup_nolapic(char *arg) 2280 { 2281 return setup_disableapic(arg); 2282 } 2283 early_param("nolapic", setup_nolapic); 2284 2285 static int __init parse_lapic_timer_c2_ok(char *arg) 2286 { 2287 local_apic_timer_c2_ok = 1; 2288 return 0; 2289 } 2290 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2291 2292 static int __init parse_disable_apic_timer(char *arg) 2293 { 2294 disable_apic_timer = 1; 2295 return 0; 2296 } 2297 early_param("noapictimer", parse_disable_apic_timer); 2298 2299 static int __init parse_nolapic_timer(char *arg) 2300 { 2301 disable_apic_timer = 1; 2302 return 0; 2303 } 2304 early_param("nolapic_timer", parse_nolapic_timer); 2305 2306 static int __init apic_set_verbosity(char *arg) 2307 { 2308 if (!arg) { 2309 #ifdef CONFIG_X86_64 2310 skip_ioapic_setup = 0; 2311 return 0; 2312 #endif 2313 return -EINVAL; 2314 } 2315 2316 if (strcmp("debug", arg) == 0) 2317 apic_verbosity = APIC_DEBUG; 2318 else if (strcmp("verbose", arg) == 0) 2319 apic_verbosity = APIC_VERBOSE; 2320 else { 2321 pr_warning("APIC Verbosity level %s not recognised" 2322 " use apic=verbose or apic=debug\n", arg); 2323 return -EINVAL; 2324 } 2325 2326 return 0; 2327 } 2328 early_param("apic", apic_set_verbosity); 2329 2330 static int __init lapic_insert_resource(void) 2331 { 2332 if (!apic_phys) 2333 return -1; 2334 2335 /* Put local APIC into the resource map. */ 2336 lapic_resource.start = apic_phys; 2337 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2338 insert_resource(&iomem_resource, &lapic_resource); 2339 2340 return 0; 2341 } 2342 2343 /* 2344 * need call insert after e820_reserve_resources() 2345 * that is using request_resource 2346 */ 2347 late_initcall(lapic_insert_resource); 2348