1 /* 2 * Local APIC handling, local APIC timers 3 * 4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5 * 6 * Fixes 7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8 * thanks to Eric Gilmore 9 * and Rolf G. Tews 10 * for testing these extensively. 11 * Maciej W. Rozycki : Various updates and fixes. 12 * Mikael Pettersson : Power Management for UP-APIC. 13 * Pavel Machek and 14 * Mikael Pettersson : PM converted to driver model. 15 */ 16 17 #include <linux/perf_event.h> 18 #include <linux/kernel_stat.h> 19 #include <linux/mc146818rtc.h> 20 #include <linux/acpi_pmtmr.h> 21 #include <linux/clockchips.h> 22 #include <linux/interrupt.h> 23 #include <linux/bootmem.h> 24 #include <linux/ftrace.h> 25 #include <linux/ioport.h> 26 #include <linux/module.h> 27 #include <linux/sysdev.h> 28 #include <linux/delay.h> 29 #include <linux/timex.h> 30 #include <linux/dmar.h> 31 #include <linux/init.h> 32 #include <linux/cpu.h> 33 #include <linux/dmi.h> 34 #include <linux/nmi.h> 35 #include <linux/smp.h> 36 #include <linux/mm.h> 37 38 #include <asm/perf_event.h> 39 #include <asm/x86_init.h> 40 #include <asm/pgalloc.h> 41 #include <asm/atomic.h> 42 #include <asm/mpspec.h> 43 #include <asm/i8253.h> 44 #include <asm/i8259.h> 45 #include <asm/proto.h> 46 #include <asm/apic.h> 47 #include <asm/desc.h> 48 #include <asm/hpet.h> 49 #include <asm/idle.h> 50 #include <asm/mtrr.h> 51 #include <asm/smp.h> 52 #include <asm/mce.h> 53 #include <asm/kvm_para.h> 54 #include <asm/tsc.h> 55 #include <asm/atomic.h> 56 57 unsigned int num_processors; 58 59 unsigned disabled_cpus __cpuinitdata; 60 61 /* Processor that is doing the boot up */ 62 unsigned int boot_cpu_physical_apicid = -1U; 63 64 /* 65 * The highest APIC ID seen during enumeration. 66 */ 67 unsigned int max_physical_apicid; 68 69 /* 70 * Bitmask of physically existing CPUs: 71 */ 72 physid_mask_t phys_cpu_present_map; 73 74 /* 75 * Map cpu index to physical APIC ID 76 */ 77 DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID); 78 DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID); 79 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 80 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 81 82 #ifdef CONFIG_X86_32 83 /* 84 * Knob to control our willingness to enable the local APIC. 85 * 86 * +1=force-enable 87 */ 88 static int force_enable_local_apic; 89 /* 90 * APIC command line parameters 91 */ 92 static int __init parse_lapic(char *arg) 93 { 94 force_enable_local_apic = 1; 95 return 0; 96 } 97 early_param("lapic", parse_lapic); 98 /* Local APIC was disabled by the BIOS and enabled by the kernel */ 99 static int enabled_via_apicbase; 100 101 /* 102 * Handle interrupt mode configuration register (IMCR). 103 * This register controls whether the interrupt signals 104 * that reach the BSP come from the master PIC or from the 105 * local APIC. Before entering Symmetric I/O Mode, either 106 * the BIOS or the operating system must switch out of 107 * PIC Mode by changing the IMCR. 108 */ 109 static inline void imcr_pic_to_apic(void) 110 { 111 /* select IMCR register */ 112 outb(0x70, 0x22); 113 /* NMI and 8259 INTR go through APIC */ 114 outb(0x01, 0x23); 115 } 116 117 static inline void imcr_apic_to_pic(void) 118 { 119 /* select IMCR register */ 120 outb(0x70, 0x22); 121 /* NMI and 8259 INTR go directly to BSP */ 122 outb(0x00, 0x23); 123 } 124 #endif 125 126 #ifdef CONFIG_X86_64 127 static int apic_calibrate_pmtmr __initdata; 128 static __init int setup_apicpmtimer(char *s) 129 { 130 apic_calibrate_pmtmr = 1; 131 notsc_setup(NULL); 132 return 0; 133 } 134 __setup("apicpmtimer", setup_apicpmtimer); 135 #endif 136 137 int x2apic_mode; 138 #ifdef CONFIG_X86_X2APIC 139 /* x2apic enabled before OS handover */ 140 static int x2apic_preenabled; 141 static __init int setup_nox2apic(char *str) 142 { 143 if (x2apic_enabled()) { 144 pr_warning("Bios already enabled x2apic, " 145 "can't enforce nox2apic"); 146 return 0; 147 } 148 149 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 150 return 0; 151 } 152 early_param("nox2apic", setup_nox2apic); 153 #endif 154 155 unsigned long mp_lapic_addr; 156 int disable_apic; 157 /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 158 static int disable_apic_timer __cpuinitdata; 159 /* Local APIC timer works in C2 */ 160 int local_apic_timer_c2_ok; 161 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 162 163 int first_system_vector = 0xfe; 164 165 /* 166 * Debug level, exported for io_apic.c 167 */ 168 unsigned int apic_verbosity; 169 170 int pic_mode; 171 172 /* Have we found an MP table */ 173 int smp_found_config; 174 175 static struct resource lapic_resource = { 176 .name = "Local APIC", 177 .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 178 }; 179 180 static unsigned int calibration_result; 181 182 static int lapic_next_event(unsigned long delta, 183 struct clock_event_device *evt); 184 static void lapic_timer_setup(enum clock_event_mode mode, 185 struct clock_event_device *evt); 186 static void lapic_timer_broadcast(const struct cpumask *mask); 187 static void apic_pm_activate(void); 188 189 /* 190 * The local apic timer can be used for any function which is CPU local. 191 */ 192 static struct clock_event_device lapic_clockevent = { 193 .name = "lapic", 194 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT 195 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, 196 .shift = 32, 197 .set_mode = lapic_timer_setup, 198 .set_next_event = lapic_next_event, 199 .broadcast = lapic_timer_broadcast, 200 .rating = 100, 201 .irq = -1, 202 }; 203 static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 204 205 static unsigned long apic_phys; 206 207 /* 208 * Get the LAPIC version 209 */ 210 static inline int lapic_get_version(void) 211 { 212 return GET_APIC_VERSION(apic_read(APIC_LVR)); 213 } 214 215 /* 216 * Check, if the APIC is integrated or a separate chip 217 */ 218 static inline int lapic_is_integrated(void) 219 { 220 #ifdef CONFIG_X86_64 221 return 1; 222 #else 223 return APIC_INTEGRATED(lapic_get_version()); 224 #endif 225 } 226 227 /* 228 * Check, whether this is a modern or a first generation APIC 229 */ 230 static int modern_apic(void) 231 { 232 /* AMD systems use old APIC versions, so check the CPU */ 233 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 234 boot_cpu_data.x86 >= 0xf) 235 return 1; 236 return lapic_get_version() >= 0x14; 237 } 238 239 /* 240 * right after this call apic become NOOP driven 241 * so apic->write/read doesn't do anything 242 */ 243 void apic_disable(void) 244 { 245 pr_info("APIC: switched to apic NOOP\n"); 246 apic = &apic_noop; 247 } 248 249 void native_apic_wait_icr_idle(void) 250 { 251 while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 252 cpu_relax(); 253 } 254 255 u32 native_safe_apic_wait_icr_idle(void) 256 { 257 u32 send_status; 258 int timeout; 259 260 timeout = 0; 261 do { 262 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 263 if (!send_status) 264 break; 265 udelay(100); 266 } while (timeout++ < 1000); 267 268 return send_status; 269 } 270 271 void native_apic_icr_write(u32 low, u32 id) 272 { 273 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 274 apic_write(APIC_ICR, low); 275 } 276 277 u64 native_apic_icr_read(void) 278 { 279 u32 icr1, icr2; 280 281 icr2 = apic_read(APIC_ICR2); 282 icr1 = apic_read(APIC_ICR); 283 284 return icr1 | ((u64)icr2 << 32); 285 } 286 287 /** 288 * enable_NMI_through_LVT0 - enable NMI through local vector table 0 289 */ 290 void __cpuinit enable_NMI_through_LVT0(void) 291 { 292 unsigned int v; 293 294 /* unmask and set to NMI */ 295 v = APIC_DM_NMI; 296 297 /* Level triggered for 82489DX (32bit mode) */ 298 if (!lapic_is_integrated()) 299 v |= APIC_LVT_LEVEL_TRIGGER; 300 301 apic_write(APIC_LVT0, v); 302 } 303 304 #ifdef CONFIG_X86_32 305 /** 306 * get_physical_broadcast - Get number of physical broadcast IDs 307 */ 308 int get_physical_broadcast(void) 309 { 310 return modern_apic() ? 0xff : 0xf; 311 } 312 #endif 313 314 /** 315 * lapic_get_maxlvt - get the maximum number of local vector table entries 316 */ 317 int lapic_get_maxlvt(void) 318 { 319 unsigned int v; 320 321 v = apic_read(APIC_LVR); 322 /* 323 * - we always have APIC integrated on 64bit mode 324 * - 82489DXs do not report # of LVT entries 325 */ 326 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; 327 } 328 329 /* 330 * Local APIC timer 331 */ 332 333 /* Clock divisor */ 334 #define APIC_DIVISOR 16 335 336 /* 337 * This function sets up the local APIC timer, with a timeout of 338 * 'clocks' APIC bus clock. During calibration we actually call 339 * this function twice on the boot CPU, once with a bogus timeout 340 * value, second time for real. The other (noncalibrating) CPUs 341 * call this function only once, with the real, calibrated value. 342 * 343 * We do reads before writes even if unnecessary, to get around the 344 * P5 APIC double write bug. 345 */ 346 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 347 { 348 unsigned int lvtt_value, tmp_value; 349 350 lvtt_value = LOCAL_TIMER_VECTOR; 351 if (!oneshot) 352 lvtt_value |= APIC_LVT_TIMER_PERIODIC; 353 if (!lapic_is_integrated()) 354 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 355 356 if (!irqen) 357 lvtt_value |= APIC_LVT_MASKED; 358 359 apic_write(APIC_LVTT, lvtt_value); 360 361 /* 362 * Divide PICLK by 16 363 */ 364 tmp_value = apic_read(APIC_TDCR); 365 apic_write(APIC_TDCR, 366 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 367 APIC_TDR_DIV_16); 368 369 if (!oneshot) 370 apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 371 } 372 373 /* 374 * Setup extended LVT, AMD specific 375 * 376 * Software should use the LVT offsets the BIOS provides. The offsets 377 * are determined by the subsystems using it like those for MCE 378 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 379 * are supported. Beginning with family 10h at least 4 offsets are 380 * available. 381 * 382 * Since the offsets must be consistent for all cores, we keep track 383 * of the LVT offsets in software and reserve the offset for the same 384 * vector also to be used on other cores. An offset is freed by 385 * setting the entry to APIC_EILVT_MASKED. 386 * 387 * If the BIOS is right, there should be no conflicts. Otherwise a 388 * "[Firmware Bug]: ..." error message is generated. However, if 389 * software does not properly determines the offsets, it is not 390 * necessarily a BIOS bug. 391 */ 392 393 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 394 395 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 396 { 397 return (old & APIC_EILVT_MASKED) 398 || (new == APIC_EILVT_MASKED) 399 || ((new & ~APIC_EILVT_MASKED) == old); 400 } 401 402 static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 403 { 404 unsigned int rsvd; /* 0: uninitialized */ 405 406 if (offset >= APIC_EILVT_NR_MAX) 407 return ~0; 408 409 rsvd = atomic_read(&eilvt_offsets[offset]) & ~APIC_EILVT_MASKED; 410 do { 411 if (rsvd && 412 !eilvt_entry_is_changeable(rsvd, new)) 413 /* may not change if vectors are different */ 414 return rsvd; 415 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 416 } while (rsvd != new); 417 418 return new; 419 } 420 421 /* 422 * If mask=1, the LVT entry does not generate interrupts while mask=0 423 * enables the vector. See also the BKDGs. 424 */ 425 426 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 427 { 428 unsigned long reg = APIC_EILVTn(offset); 429 unsigned int new, old, reserved; 430 431 new = (mask << 16) | (msg_type << 8) | vector; 432 old = apic_read(reg); 433 reserved = reserve_eilvt_offset(offset, new); 434 435 if (reserved != new) { 436 pr_err(FW_BUG "cpu %d, try to setup vector 0x%x, but " 437 "vector 0x%x was already reserved by another core, " 438 "APIC%lX=0x%x\n", 439 smp_processor_id(), new, reserved, reg, old); 440 return -EINVAL; 441 } 442 443 if (!eilvt_entry_is_changeable(old, new)) { 444 pr_err(FW_BUG "cpu %d, try to setup vector 0x%x but " 445 "register already in use, APIC%lX=0x%x\n", 446 smp_processor_id(), new, reg, old); 447 return -EBUSY; 448 } 449 450 apic_write(reg, new); 451 452 return 0; 453 } 454 EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 455 456 /* 457 * Program the next event, relative to now 458 */ 459 static int lapic_next_event(unsigned long delta, 460 struct clock_event_device *evt) 461 { 462 apic_write(APIC_TMICT, delta); 463 return 0; 464 } 465 466 /* 467 * Setup the lapic timer in periodic or oneshot mode 468 */ 469 static void lapic_timer_setup(enum clock_event_mode mode, 470 struct clock_event_device *evt) 471 { 472 unsigned long flags; 473 unsigned int v; 474 475 /* Lapic used as dummy for broadcast ? */ 476 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 477 return; 478 479 local_irq_save(flags); 480 481 switch (mode) { 482 case CLOCK_EVT_MODE_PERIODIC: 483 case CLOCK_EVT_MODE_ONESHOT: 484 __setup_APIC_LVTT(calibration_result, 485 mode != CLOCK_EVT_MODE_PERIODIC, 1); 486 break; 487 case CLOCK_EVT_MODE_UNUSED: 488 case CLOCK_EVT_MODE_SHUTDOWN: 489 v = apic_read(APIC_LVTT); 490 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 491 apic_write(APIC_LVTT, v); 492 apic_write(APIC_TMICT, 0); 493 break; 494 case CLOCK_EVT_MODE_RESUME: 495 /* Nothing to do here */ 496 break; 497 } 498 499 local_irq_restore(flags); 500 } 501 502 /* 503 * Local APIC timer broadcast function 504 */ 505 static void lapic_timer_broadcast(const struct cpumask *mask) 506 { 507 #ifdef CONFIG_SMP 508 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 509 #endif 510 } 511 512 /* 513 * Setup the local APIC timer for this CPU. Copy the initialized values 514 * of the boot CPU and register the clock event in the framework. 515 */ 516 static void __cpuinit setup_APIC_timer(void) 517 { 518 struct clock_event_device *levt = &__get_cpu_var(lapic_events); 519 520 if (cpu_has(¤t_cpu_data, X86_FEATURE_ARAT)) { 521 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 522 /* Make LAPIC timer preferrable over percpu HPET */ 523 lapic_clockevent.rating = 150; 524 } 525 526 memcpy(levt, &lapic_clockevent, sizeof(*levt)); 527 levt->cpumask = cpumask_of(smp_processor_id()); 528 529 clockevents_register_device(levt); 530 } 531 532 /* 533 * In this functions we calibrate APIC bus clocks to the external timer. 534 * 535 * We want to do the calibration only once since we want to have local timer 536 * irqs syncron. CPUs connected by the same APIC bus have the very same bus 537 * frequency. 538 * 539 * This was previously done by reading the PIT/HPET and waiting for a wrap 540 * around to find out, that a tick has elapsed. I have a box, where the PIT 541 * readout is broken, so it never gets out of the wait loop again. This was 542 * also reported by others. 543 * 544 * Monitoring the jiffies value is inaccurate and the clockevents 545 * infrastructure allows us to do a simple substitution of the interrupt 546 * handler. 547 * 548 * The calibration routine also uses the pm_timer when possible, as the PIT 549 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 550 * back to normal later in the boot process). 551 */ 552 553 #define LAPIC_CAL_LOOPS (HZ/10) 554 555 static __initdata int lapic_cal_loops = -1; 556 static __initdata long lapic_cal_t1, lapic_cal_t2; 557 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 558 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 559 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 560 561 /* 562 * Temporary interrupt handler. 563 */ 564 static void __init lapic_cal_handler(struct clock_event_device *dev) 565 { 566 unsigned long long tsc = 0; 567 long tapic = apic_read(APIC_TMCCT); 568 unsigned long pm = acpi_pm_read_early(); 569 570 if (cpu_has_tsc) 571 rdtscll(tsc); 572 573 switch (lapic_cal_loops++) { 574 case 0: 575 lapic_cal_t1 = tapic; 576 lapic_cal_tsc1 = tsc; 577 lapic_cal_pm1 = pm; 578 lapic_cal_j1 = jiffies; 579 break; 580 581 case LAPIC_CAL_LOOPS: 582 lapic_cal_t2 = tapic; 583 lapic_cal_tsc2 = tsc; 584 if (pm < lapic_cal_pm1) 585 pm += ACPI_PM_OVRRUN; 586 lapic_cal_pm2 = pm; 587 lapic_cal_j2 = jiffies; 588 break; 589 } 590 } 591 592 static int __init 593 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 594 { 595 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 596 const long pm_thresh = pm_100ms / 100; 597 unsigned long mult; 598 u64 res; 599 600 #ifndef CONFIG_X86_PM_TIMER 601 return -1; 602 #endif 603 604 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 605 606 /* Check, if the PM timer is available */ 607 if (!deltapm) 608 return -1; 609 610 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 611 612 if (deltapm > (pm_100ms - pm_thresh) && 613 deltapm < (pm_100ms + pm_thresh)) { 614 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 615 return 0; 616 } 617 618 res = (((u64)deltapm) * mult) >> 22; 619 do_div(res, 1000000); 620 pr_warning("APIC calibration not consistent " 621 "with PM-Timer: %ldms instead of 100ms\n",(long)res); 622 623 /* Correct the lapic counter value */ 624 res = (((u64)(*delta)) * pm_100ms); 625 do_div(res, deltapm); 626 pr_info("APIC delta adjusted to PM-Timer: " 627 "%lu (%ld)\n", (unsigned long)res, *delta); 628 *delta = (long)res; 629 630 /* Correct the tsc counter value */ 631 if (cpu_has_tsc) { 632 res = (((u64)(*deltatsc)) * pm_100ms); 633 do_div(res, deltapm); 634 apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 635 "PM-Timer: %lu (%ld)\n", 636 (unsigned long)res, *deltatsc); 637 *deltatsc = (long)res; 638 } 639 640 return 0; 641 } 642 643 static int __init calibrate_APIC_clock(void) 644 { 645 struct clock_event_device *levt = &__get_cpu_var(lapic_events); 646 void (*real_handler)(struct clock_event_device *dev); 647 unsigned long deltaj; 648 long delta, deltatsc; 649 int pm_referenced = 0; 650 651 local_irq_disable(); 652 653 /* Replace the global interrupt handler */ 654 real_handler = global_clock_event->event_handler; 655 global_clock_event->event_handler = lapic_cal_handler; 656 657 /* 658 * Setup the APIC counter to maximum. There is no way the lapic 659 * can underflow in the 100ms detection time frame 660 */ 661 __setup_APIC_LVTT(0xffffffff, 0, 0); 662 663 /* Let the interrupts run */ 664 local_irq_enable(); 665 666 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 667 cpu_relax(); 668 669 local_irq_disable(); 670 671 /* Restore the real event handler */ 672 global_clock_event->event_handler = real_handler; 673 674 /* Build delta t1-t2 as apic timer counts down */ 675 delta = lapic_cal_t1 - lapic_cal_t2; 676 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 677 678 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 679 680 /* we trust the PM based calibration if possible */ 681 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 682 &delta, &deltatsc); 683 684 /* Calculate the scaled math multiplication factor */ 685 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 686 lapic_clockevent.shift); 687 lapic_clockevent.max_delta_ns = 688 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); 689 lapic_clockevent.min_delta_ns = 690 clockevent_delta2ns(0xF, &lapic_clockevent); 691 692 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 693 694 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 695 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 696 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 697 calibration_result); 698 699 if (cpu_has_tsc) { 700 apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 701 "%ld.%04ld MHz.\n", 702 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 703 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 704 } 705 706 apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 707 "%u.%04u MHz.\n", 708 calibration_result / (1000000 / HZ), 709 calibration_result % (1000000 / HZ)); 710 711 /* 712 * Do a sanity check on the APIC calibration result 713 */ 714 if (calibration_result < (1000000 / HZ)) { 715 local_irq_enable(); 716 pr_warning("APIC frequency too slow, disabling apic timer\n"); 717 return -1; 718 } 719 720 levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 721 722 /* 723 * PM timer calibration failed or not turned on 724 * so lets try APIC timer based calibration 725 */ 726 if (!pm_referenced) { 727 apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 728 729 /* 730 * Setup the apic timer manually 731 */ 732 levt->event_handler = lapic_cal_handler; 733 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); 734 lapic_cal_loops = -1; 735 736 /* Let the interrupts run */ 737 local_irq_enable(); 738 739 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 740 cpu_relax(); 741 742 /* Stop the lapic timer */ 743 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); 744 745 /* Jiffies delta */ 746 deltaj = lapic_cal_j2 - lapic_cal_j1; 747 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 748 749 /* Check, if the jiffies result is consistent */ 750 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 751 apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 752 else 753 levt->features |= CLOCK_EVT_FEAT_DUMMY; 754 } else 755 local_irq_enable(); 756 757 if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 758 pr_warning("APIC timer disabled due to verification failure\n"); 759 return -1; 760 } 761 762 return 0; 763 } 764 765 /* 766 * Setup the boot APIC 767 * 768 * Calibrate and verify the result. 769 */ 770 void __init setup_boot_APIC_clock(void) 771 { 772 /* 773 * The local apic timer can be disabled via the kernel 774 * commandline or from the CPU detection code. Register the lapic 775 * timer as a dummy clock event source on SMP systems, so the 776 * broadcast mechanism is used. On UP systems simply ignore it. 777 */ 778 if (disable_apic_timer) { 779 pr_info("Disabling APIC timer\n"); 780 /* No broadcast on UP ! */ 781 if (num_possible_cpus() > 1) { 782 lapic_clockevent.mult = 1; 783 setup_APIC_timer(); 784 } 785 return; 786 } 787 788 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 789 "calibrating APIC timer ...\n"); 790 791 if (calibrate_APIC_clock()) { 792 /* No broadcast on UP ! */ 793 if (num_possible_cpus() > 1) 794 setup_APIC_timer(); 795 return; 796 } 797 798 /* 799 * If nmi_watchdog is set to IO_APIC, we need the 800 * PIT/HPET going. Otherwise register lapic as a dummy 801 * device. 802 */ 803 if (nmi_watchdog != NMI_IO_APIC) 804 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 805 else 806 pr_warning("APIC timer registered as dummy," 807 " due to nmi_watchdog=%d!\n", nmi_watchdog); 808 809 /* Setup the lapic or request the broadcast */ 810 setup_APIC_timer(); 811 } 812 813 void __cpuinit setup_secondary_APIC_clock(void) 814 { 815 setup_APIC_timer(); 816 } 817 818 /* 819 * The guts of the apic timer interrupt 820 */ 821 static void local_apic_timer_interrupt(void) 822 { 823 int cpu = smp_processor_id(); 824 struct clock_event_device *evt = &per_cpu(lapic_events, cpu); 825 826 /* 827 * Normally we should not be here till LAPIC has been initialized but 828 * in some cases like kdump, its possible that there is a pending LAPIC 829 * timer interrupt from previous kernel's context and is delivered in 830 * new kernel the moment interrupts are enabled. 831 * 832 * Interrupts are enabled early and LAPIC is setup much later, hence 833 * its possible that when we get here evt->event_handler is NULL. 834 * Check for event_handler being NULL and discard the interrupt as 835 * spurious. 836 */ 837 if (!evt->event_handler) { 838 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); 839 /* Switch it off */ 840 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); 841 return; 842 } 843 844 /* 845 * the NMI deadlock-detector uses this. 846 */ 847 inc_irq_stat(apic_timer_irqs); 848 849 evt->event_handler(evt); 850 } 851 852 /* 853 * Local APIC timer interrupt. This is the most natural way for doing 854 * local interrupts, but local timer interrupts can be emulated by 855 * broadcast interrupts too. [in case the hw doesn't support APIC timers] 856 * 857 * [ if a single-CPU system runs an SMP kernel then we call the local 858 * interrupt as well. Thus we cannot inline the local irq ... ] 859 */ 860 void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 861 { 862 struct pt_regs *old_regs = set_irq_regs(regs); 863 864 /* 865 * NOTE! We'd better ACK the irq immediately, 866 * because timer handling can be slow. 867 */ 868 ack_APIC_irq(); 869 /* 870 * update_process_times() expects us to have done irq_enter(). 871 * Besides, if we don't timer interrupts ignore the global 872 * interrupt lock, which is the WrongThing (tm) to do. 873 */ 874 exit_idle(); 875 irq_enter(); 876 local_apic_timer_interrupt(); 877 irq_exit(); 878 879 set_irq_regs(old_regs); 880 } 881 882 int setup_profiling_timer(unsigned int multiplier) 883 { 884 return -EINVAL; 885 } 886 887 /* 888 * Local APIC start and shutdown 889 */ 890 891 /** 892 * clear_local_APIC - shutdown the local APIC 893 * 894 * This is called, when a CPU is disabled and before rebooting, so the state of 895 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 896 * leftovers during boot. 897 */ 898 void clear_local_APIC(void) 899 { 900 int maxlvt; 901 u32 v; 902 903 /* APIC hasn't been mapped yet */ 904 if (!x2apic_mode && !apic_phys) 905 return; 906 907 maxlvt = lapic_get_maxlvt(); 908 /* 909 * Masking an LVT entry can trigger a local APIC error 910 * if the vector is zero. Mask LVTERR first to prevent this. 911 */ 912 if (maxlvt >= 3) { 913 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 914 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 915 } 916 /* 917 * Careful: we have to set masks only first to deassert 918 * any level-triggered sources. 919 */ 920 v = apic_read(APIC_LVTT); 921 apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 922 v = apic_read(APIC_LVT0); 923 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 924 v = apic_read(APIC_LVT1); 925 apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 926 if (maxlvt >= 4) { 927 v = apic_read(APIC_LVTPC); 928 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 929 } 930 931 /* lets not touch this if we didn't frob it */ 932 #ifdef CONFIG_X86_THERMAL_VECTOR 933 if (maxlvt >= 5) { 934 v = apic_read(APIC_LVTTHMR); 935 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 936 } 937 #endif 938 #ifdef CONFIG_X86_MCE_INTEL 939 if (maxlvt >= 6) { 940 v = apic_read(APIC_LVTCMCI); 941 if (!(v & APIC_LVT_MASKED)) 942 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 943 } 944 #endif 945 946 /* 947 * Clean APIC state for other OSs: 948 */ 949 apic_write(APIC_LVTT, APIC_LVT_MASKED); 950 apic_write(APIC_LVT0, APIC_LVT_MASKED); 951 apic_write(APIC_LVT1, APIC_LVT_MASKED); 952 if (maxlvt >= 3) 953 apic_write(APIC_LVTERR, APIC_LVT_MASKED); 954 if (maxlvt >= 4) 955 apic_write(APIC_LVTPC, APIC_LVT_MASKED); 956 957 /* Integrated APIC (!82489DX) ? */ 958 if (lapic_is_integrated()) { 959 if (maxlvt > 3) 960 /* Clear ESR due to Pentium errata 3AP and 11AP */ 961 apic_write(APIC_ESR, 0); 962 apic_read(APIC_ESR); 963 } 964 } 965 966 /** 967 * disable_local_APIC - clear and disable the local APIC 968 */ 969 void disable_local_APIC(void) 970 { 971 unsigned int value; 972 973 /* APIC hasn't been mapped yet */ 974 if (!x2apic_mode && !apic_phys) 975 return; 976 977 clear_local_APIC(); 978 979 /* 980 * Disable APIC (implies clearing of registers 981 * for 82489DX!). 982 */ 983 value = apic_read(APIC_SPIV); 984 value &= ~APIC_SPIV_APIC_ENABLED; 985 apic_write(APIC_SPIV, value); 986 987 #ifdef CONFIG_X86_32 988 /* 989 * When LAPIC was disabled by the BIOS and enabled by the kernel, 990 * restore the disabled state. 991 */ 992 if (enabled_via_apicbase) { 993 unsigned int l, h; 994 995 rdmsr(MSR_IA32_APICBASE, l, h); 996 l &= ~MSR_IA32_APICBASE_ENABLE; 997 wrmsr(MSR_IA32_APICBASE, l, h); 998 } 999 #endif 1000 } 1001 1002 /* 1003 * If Linux enabled the LAPIC against the BIOS default disable it down before 1004 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1005 * not power-off. Additionally clear all LVT entries before disable_local_APIC 1006 * for the case where Linux didn't enable the LAPIC. 1007 */ 1008 void lapic_shutdown(void) 1009 { 1010 unsigned long flags; 1011 1012 if (!cpu_has_apic && !apic_from_smp_config()) 1013 return; 1014 1015 local_irq_save(flags); 1016 1017 #ifdef CONFIG_X86_32 1018 if (!enabled_via_apicbase) 1019 clear_local_APIC(); 1020 else 1021 #endif 1022 disable_local_APIC(); 1023 1024 1025 local_irq_restore(flags); 1026 } 1027 1028 /* 1029 * This is to verify that we're looking at a real local APIC. 1030 * Check these against your board if the CPUs aren't getting 1031 * started for no apparent reason. 1032 */ 1033 int __init verify_local_APIC(void) 1034 { 1035 unsigned int reg0, reg1; 1036 1037 /* 1038 * The version register is read-only in a real APIC. 1039 */ 1040 reg0 = apic_read(APIC_LVR); 1041 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); 1042 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); 1043 reg1 = apic_read(APIC_LVR); 1044 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); 1045 1046 /* 1047 * The two version reads above should print the same 1048 * numbers. If the second one is different, then we 1049 * poke at a non-APIC. 1050 */ 1051 if (reg1 != reg0) 1052 return 0; 1053 1054 /* 1055 * Check if the version looks reasonably. 1056 */ 1057 reg1 = GET_APIC_VERSION(reg0); 1058 if (reg1 == 0x00 || reg1 == 0xff) 1059 return 0; 1060 reg1 = lapic_get_maxlvt(); 1061 if (reg1 < 0x02 || reg1 == 0xff) 1062 return 0; 1063 1064 /* 1065 * The ID register is read/write in a real APIC. 1066 */ 1067 reg0 = apic_read(APIC_ID); 1068 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); 1069 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask); 1070 reg1 = apic_read(APIC_ID); 1071 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); 1072 apic_write(APIC_ID, reg0); 1073 if (reg1 != (reg0 ^ apic->apic_id_mask)) 1074 return 0; 1075 1076 /* 1077 * The next two are just to see if we have sane values. 1078 * They're only really relevant if we're in Virtual Wire 1079 * compatibility mode, but most boxes are anymore. 1080 */ 1081 reg0 = apic_read(APIC_LVT0); 1082 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); 1083 reg1 = apic_read(APIC_LVT1); 1084 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); 1085 1086 return 1; 1087 } 1088 1089 /** 1090 * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1091 */ 1092 void __init sync_Arb_IDs(void) 1093 { 1094 /* 1095 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1096 * needed on AMD. 1097 */ 1098 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1099 return; 1100 1101 /* 1102 * Wait for idle. 1103 */ 1104 apic_wait_icr_idle(); 1105 1106 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1107 apic_write(APIC_ICR, APIC_DEST_ALLINC | 1108 APIC_INT_LEVELTRIG | APIC_DM_INIT); 1109 } 1110 1111 /* 1112 * An initial setup of the virtual wire mode. 1113 */ 1114 void __init init_bsp_APIC(void) 1115 { 1116 unsigned int value; 1117 1118 /* 1119 * Don't do the setup now if we have a SMP BIOS as the 1120 * through-I/O-APIC virtual wire mode might be active. 1121 */ 1122 if (smp_found_config || !cpu_has_apic) 1123 return; 1124 1125 /* 1126 * Do not trust the local APIC being empty at bootup. 1127 */ 1128 clear_local_APIC(); 1129 1130 /* 1131 * Enable APIC. 1132 */ 1133 value = apic_read(APIC_SPIV); 1134 value &= ~APIC_VECTOR_MASK; 1135 value |= APIC_SPIV_APIC_ENABLED; 1136 1137 #ifdef CONFIG_X86_32 1138 /* This bit is reserved on P4/Xeon and should be cleared */ 1139 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1140 (boot_cpu_data.x86 == 15)) 1141 value &= ~APIC_SPIV_FOCUS_DISABLED; 1142 else 1143 #endif 1144 value |= APIC_SPIV_FOCUS_DISABLED; 1145 value |= SPURIOUS_APIC_VECTOR; 1146 apic_write(APIC_SPIV, value); 1147 1148 /* 1149 * Set up the virtual wire mode. 1150 */ 1151 apic_write(APIC_LVT0, APIC_DM_EXTINT); 1152 value = APIC_DM_NMI; 1153 if (!lapic_is_integrated()) /* 82489DX */ 1154 value |= APIC_LVT_LEVEL_TRIGGER; 1155 apic_write(APIC_LVT1, value); 1156 } 1157 1158 static void __cpuinit lapic_setup_esr(void) 1159 { 1160 unsigned int oldvalue, value, maxlvt; 1161 1162 if (!lapic_is_integrated()) { 1163 pr_info("No ESR for 82489DX.\n"); 1164 return; 1165 } 1166 1167 if (apic->disable_esr) { 1168 /* 1169 * Something untraceable is creating bad interrupts on 1170 * secondary quads ... for the moment, just leave the 1171 * ESR disabled - we can't do anything useful with the 1172 * errors anyway - mbligh 1173 */ 1174 pr_info("Leaving ESR disabled.\n"); 1175 return; 1176 } 1177 1178 maxlvt = lapic_get_maxlvt(); 1179 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1180 apic_write(APIC_ESR, 0); 1181 oldvalue = apic_read(APIC_ESR); 1182 1183 /* enables sending errors */ 1184 value = ERROR_APIC_VECTOR; 1185 apic_write(APIC_LVTERR, value); 1186 1187 /* 1188 * spec says clear errors after enabling vector. 1189 */ 1190 if (maxlvt > 3) 1191 apic_write(APIC_ESR, 0); 1192 value = apic_read(APIC_ESR); 1193 if (value != oldvalue) 1194 apic_printk(APIC_VERBOSE, "ESR value before enabling " 1195 "vector: 0x%08x after: 0x%08x\n", 1196 oldvalue, value); 1197 } 1198 1199 1200 /** 1201 * setup_local_APIC - setup the local APIC 1202 */ 1203 void __cpuinit setup_local_APIC(void) 1204 { 1205 unsigned int value, queued; 1206 int i, j, acked = 0; 1207 unsigned long long tsc = 0, ntsc; 1208 long long max_loops = cpu_khz; 1209 1210 if (cpu_has_tsc) 1211 rdtscll(tsc); 1212 1213 if (disable_apic) { 1214 arch_disable_smp_support(); 1215 return; 1216 } 1217 1218 #ifdef CONFIG_X86_32 1219 /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1220 if (lapic_is_integrated() && apic->disable_esr) { 1221 apic_write(APIC_ESR, 0); 1222 apic_write(APIC_ESR, 0); 1223 apic_write(APIC_ESR, 0); 1224 apic_write(APIC_ESR, 0); 1225 } 1226 #endif 1227 perf_events_lapic_init(); 1228 1229 preempt_disable(); 1230 1231 /* 1232 * Double-check whether this APIC is really registered. 1233 * This is meaningless in clustered apic mode, so we skip it. 1234 */ 1235 BUG_ON(!apic->apic_id_registered()); 1236 1237 /* 1238 * Intel recommends to set DFR, LDR and TPR before enabling 1239 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1240 * document number 292116). So here it goes... 1241 */ 1242 apic->init_apic_ldr(); 1243 1244 /* 1245 * Set Task Priority to 'accept all'. We never change this 1246 * later on. 1247 */ 1248 value = apic_read(APIC_TASKPRI); 1249 value &= ~APIC_TPRI_MASK; 1250 apic_write(APIC_TASKPRI, value); 1251 1252 /* 1253 * After a crash, we no longer service the interrupts and a pending 1254 * interrupt from previous kernel might still have ISR bit set. 1255 * 1256 * Most probably by now CPU has serviced that pending interrupt and 1257 * it might not have done the ack_APIC_irq() because it thought, 1258 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1259 * does not clear the ISR bit and cpu thinks it has already serivced 1260 * the interrupt. Hence a vector might get locked. It was noticed 1261 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1262 */ 1263 do { 1264 queued = 0; 1265 for (i = APIC_ISR_NR - 1; i >= 0; i--) 1266 queued |= apic_read(APIC_IRR + i*0x10); 1267 1268 for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1269 value = apic_read(APIC_ISR + i*0x10); 1270 for (j = 31; j >= 0; j--) { 1271 if (value & (1<<j)) { 1272 ack_APIC_irq(); 1273 acked++; 1274 } 1275 } 1276 } 1277 if (acked > 256) { 1278 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", 1279 acked); 1280 break; 1281 } 1282 if (cpu_has_tsc) { 1283 rdtscll(ntsc); 1284 max_loops = (cpu_khz << 10) - (ntsc - tsc); 1285 } else 1286 max_loops--; 1287 } while (queued && max_loops > 0); 1288 WARN_ON(max_loops <= 0); 1289 1290 /* 1291 * Now that we are all set up, enable the APIC 1292 */ 1293 value = apic_read(APIC_SPIV); 1294 value &= ~APIC_VECTOR_MASK; 1295 /* 1296 * Enable APIC 1297 */ 1298 value |= APIC_SPIV_APIC_ENABLED; 1299 1300 #ifdef CONFIG_X86_32 1301 /* 1302 * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1303 * certain networking cards. If high frequency interrupts are 1304 * happening on a particular IOAPIC pin, plus the IOAPIC routing 1305 * entry is masked/unmasked at a high rate as well then sooner or 1306 * later IOAPIC line gets 'stuck', no more interrupts are received 1307 * from the device. If focus CPU is disabled then the hang goes 1308 * away, oh well :-( 1309 * 1310 * [ This bug can be reproduced easily with a level-triggered 1311 * PCI Ne2000 networking cards and PII/PIII processors, dual 1312 * BX chipset. ] 1313 */ 1314 /* 1315 * Actually disabling the focus CPU check just makes the hang less 1316 * frequent as it makes the interrupt distributon model be more 1317 * like LRU than MRU (the short-term load is more even across CPUs). 1318 * See also the comment in end_level_ioapic_irq(). --macro 1319 */ 1320 1321 /* 1322 * - enable focus processor (bit==0) 1323 * - 64bit mode always use processor focus 1324 * so no need to set it 1325 */ 1326 value &= ~APIC_SPIV_FOCUS_DISABLED; 1327 #endif 1328 1329 /* 1330 * Set spurious IRQ vector 1331 */ 1332 value |= SPURIOUS_APIC_VECTOR; 1333 apic_write(APIC_SPIV, value); 1334 1335 /* 1336 * Set up LVT0, LVT1: 1337 * 1338 * set up through-local-APIC on the BP's LINT0. This is not 1339 * strictly necessary in pure symmetric-IO mode, but sometimes 1340 * we delegate interrupts to the 8259A. 1341 */ 1342 /* 1343 * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1344 */ 1345 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1346 if (!smp_processor_id() && (pic_mode || !value)) { 1347 value = APIC_DM_EXTINT; 1348 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", 1349 smp_processor_id()); 1350 } else { 1351 value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1352 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", 1353 smp_processor_id()); 1354 } 1355 apic_write(APIC_LVT0, value); 1356 1357 /* 1358 * only the BP should see the LINT1 NMI signal, obviously. 1359 */ 1360 if (!smp_processor_id()) 1361 value = APIC_DM_NMI; 1362 else 1363 value = APIC_DM_NMI | APIC_LVT_MASKED; 1364 if (!lapic_is_integrated()) /* 82489DX */ 1365 value |= APIC_LVT_LEVEL_TRIGGER; 1366 apic_write(APIC_LVT1, value); 1367 1368 preempt_enable(); 1369 1370 #ifdef CONFIG_X86_MCE_INTEL 1371 /* Recheck CMCI information after local APIC is up on CPU #0 */ 1372 if (smp_processor_id() == 0) 1373 cmci_recheck(); 1374 #endif 1375 } 1376 1377 void __cpuinit end_local_APIC_setup(void) 1378 { 1379 lapic_setup_esr(); 1380 1381 #ifdef CONFIG_X86_32 1382 { 1383 unsigned int value; 1384 /* Disable the local apic timer */ 1385 value = apic_read(APIC_LVTT); 1386 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1387 apic_write(APIC_LVTT, value); 1388 } 1389 #endif 1390 1391 setup_apic_nmi_watchdog(NULL); 1392 apic_pm_activate(); 1393 } 1394 1395 #ifdef CONFIG_X86_X2APIC 1396 void check_x2apic(void) 1397 { 1398 if (x2apic_enabled()) { 1399 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); 1400 x2apic_preenabled = x2apic_mode = 1; 1401 } 1402 } 1403 1404 void enable_x2apic(void) 1405 { 1406 int msr, msr2; 1407 1408 if (!x2apic_mode) 1409 return; 1410 1411 rdmsr(MSR_IA32_APICBASE, msr, msr2); 1412 if (!(msr & X2APIC_ENABLE)) { 1413 printk_once(KERN_INFO "Enabling x2apic\n"); 1414 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); 1415 } 1416 } 1417 #endif /* CONFIG_X86_X2APIC */ 1418 1419 int __init enable_IR(void) 1420 { 1421 #ifdef CONFIG_INTR_REMAP 1422 if (!intr_remapping_supported()) { 1423 pr_debug("intr-remapping not supported\n"); 1424 return 0; 1425 } 1426 1427 if (!x2apic_preenabled && skip_ioapic_setup) { 1428 pr_info("Skipped enabling intr-remap because of skipping " 1429 "io-apic setup\n"); 1430 return 0; 1431 } 1432 1433 if (enable_intr_remapping(x2apic_supported())) 1434 return 0; 1435 1436 pr_info("Enabled Interrupt-remapping\n"); 1437 1438 return 1; 1439 1440 #endif 1441 return 0; 1442 } 1443 1444 void __init enable_IR_x2apic(void) 1445 { 1446 unsigned long flags; 1447 struct IO_APIC_route_entry **ioapic_entries = NULL; 1448 int ret, x2apic_enabled = 0; 1449 int dmar_table_init_ret; 1450 1451 dmar_table_init_ret = dmar_table_init(); 1452 if (dmar_table_init_ret && !x2apic_supported()) 1453 return; 1454 1455 ioapic_entries = alloc_ioapic_entries(); 1456 if (!ioapic_entries) { 1457 pr_err("Allocate ioapic_entries failed\n"); 1458 goto out; 1459 } 1460 1461 ret = save_IO_APIC_setup(ioapic_entries); 1462 if (ret) { 1463 pr_info("Saving IO-APIC state failed: %d\n", ret); 1464 goto out; 1465 } 1466 1467 local_irq_save(flags); 1468 legacy_pic->mask_all(); 1469 mask_IO_APIC_setup(ioapic_entries); 1470 1471 if (dmar_table_init_ret) 1472 ret = 0; 1473 else 1474 ret = enable_IR(); 1475 1476 if (!ret) { 1477 /* IR is required if there is APIC ID > 255 even when running 1478 * under KVM 1479 */ 1480 if (max_physical_apicid > 255 || !kvm_para_available()) 1481 goto nox2apic; 1482 /* 1483 * without IR all CPUs can be addressed by IOAPIC/MSI 1484 * only in physical mode 1485 */ 1486 x2apic_force_phys(); 1487 } 1488 1489 x2apic_enabled = 1; 1490 1491 if (x2apic_supported() && !x2apic_mode) { 1492 x2apic_mode = 1; 1493 enable_x2apic(); 1494 pr_info("Enabled x2apic\n"); 1495 } 1496 1497 nox2apic: 1498 if (!ret) /* IR enabling failed */ 1499 restore_IO_APIC_setup(ioapic_entries); 1500 legacy_pic->restore_mask(); 1501 local_irq_restore(flags); 1502 1503 out: 1504 if (ioapic_entries) 1505 free_ioapic_entries(ioapic_entries); 1506 1507 if (x2apic_enabled) 1508 return; 1509 1510 if (x2apic_preenabled) 1511 panic("x2apic: enabled by BIOS but kernel init failed."); 1512 else if (cpu_has_x2apic) 1513 pr_info("Not enabling x2apic, Intr-remapping init failed.\n"); 1514 } 1515 1516 #ifdef CONFIG_X86_64 1517 /* 1518 * Detect and enable local APICs on non-SMP boards. 1519 * Original code written by Keir Fraser. 1520 * On AMD64 we trust the BIOS - if it says no APIC it is likely 1521 * not correctly set up (usually the APIC timer won't work etc.) 1522 */ 1523 static int __init detect_init_APIC(void) 1524 { 1525 if (!cpu_has_apic) { 1526 pr_info("No local APIC present\n"); 1527 return -1; 1528 } 1529 1530 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1531 return 0; 1532 } 1533 #else 1534 /* 1535 * Detect and initialize APIC 1536 */ 1537 static int __init detect_init_APIC(void) 1538 { 1539 u32 h, l, features; 1540 1541 /* Disabled by kernel option? */ 1542 if (disable_apic) 1543 return -1; 1544 1545 switch (boot_cpu_data.x86_vendor) { 1546 case X86_VENDOR_AMD: 1547 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1548 (boot_cpu_data.x86 >= 15)) 1549 break; 1550 goto no_apic; 1551 case X86_VENDOR_INTEL: 1552 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1553 (boot_cpu_data.x86 == 5 && cpu_has_apic)) 1554 break; 1555 goto no_apic; 1556 default: 1557 goto no_apic; 1558 } 1559 1560 if (!cpu_has_apic) { 1561 /* 1562 * Over-ride BIOS and try to enable the local APIC only if 1563 * "lapic" specified. 1564 */ 1565 if (!force_enable_local_apic) { 1566 pr_info("Local APIC disabled by BIOS -- " 1567 "you can enable it with \"lapic\"\n"); 1568 return -1; 1569 } 1570 /* 1571 * Some BIOSes disable the local APIC in the APIC_BASE 1572 * MSR. This can only be done in software for Intel P6 or later 1573 * and AMD K7 (Model > 1) or later. 1574 */ 1575 rdmsr(MSR_IA32_APICBASE, l, h); 1576 if (!(l & MSR_IA32_APICBASE_ENABLE)) { 1577 pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 1578 l &= ~MSR_IA32_APICBASE_BASE; 1579 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; 1580 wrmsr(MSR_IA32_APICBASE, l, h); 1581 enabled_via_apicbase = 1; 1582 } 1583 } 1584 /* 1585 * The APIC feature bit should now be enabled 1586 * in `cpuid' 1587 */ 1588 features = cpuid_edx(1); 1589 if (!(features & (1 << X86_FEATURE_APIC))) { 1590 pr_warning("Could not enable APIC!\n"); 1591 return -1; 1592 } 1593 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1594 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1595 1596 /* The BIOS may have set up the APIC at some other address */ 1597 rdmsr(MSR_IA32_APICBASE, l, h); 1598 if (l & MSR_IA32_APICBASE_ENABLE) 1599 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1600 1601 pr_info("Found and enabled local APIC!\n"); 1602 1603 apic_pm_activate(); 1604 1605 return 0; 1606 1607 no_apic: 1608 pr_info("No local APIC present or hardware disabled\n"); 1609 return -1; 1610 } 1611 #endif 1612 1613 #ifdef CONFIG_X86_64 1614 void __init early_init_lapic_mapping(void) 1615 { 1616 /* 1617 * If no local APIC can be found then go out 1618 * : it means there is no mpatable and MADT 1619 */ 1620 if (!smp_found_config) 1621 return; 1622 1623 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); 1624 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 1625 APIC_BASE, mp_lapic_addr); 1626 1627 /* 1628 * Fetch the APIC ID of the BSP in case we have a 1629 * default configuration (or the MP table is broken). 1630 */ 1631 boot_cpu_physical_apicid = read_apic_id(); 1632 } 1633 #endif 1634 1635 /** 1636 * init_apic_mappings - initialize APIC mappings 1637 */ 1638 void __init init_apic_mappings(void) 1639 { 1640 unsigned int new_apicid; 1641 1642 if (x2apic_mode) { 1643 boot_cpu_physical_apicid = read_apic_id(); 1644 return; 1645 } 1646 1647 /* If no local APIC can be found return early */ 1648 if (!smp_found_config && detect_init_APIC()) { 1649 /* lets NOP'ify apic operations */ 1650 pr_info("APIC: disable apic facility\n"); 1651 apic_disable(); 1652 } else { 1653 apic_phys = mp_lapic_addr; 1654 1655 /* 1656 * acpi lapic path already maps that address in 1657 * acpi_register_lapic_address() 1658 */ 1659 if (!acpi_lapic && !smp_found_config) 1660 set_fixmap_nocache(FIX_APIC_BASE, apic_phys); 1661 1662 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", 1663 APIC_BASE, apic_phys); 1664 } 1665 1666 /* 1667 * Fetch the APIC ID of the BSP in case we have a 1668 * default configuration (or the MP table is broken). 1669 */ 1670 new_apicid = read_apic_id(); 1671 if (boot_cpu_physical_apicid != new_apicid) { 1672 boot_cpu_physical_apicid = new_apicid; 1673 /* 1674 * yeah -- we lie about apic_version 1675 * in case if apic was disabled via boot option 1676 * but it's not a problem for SMP compiled kernel 1677 * since smp_sanity_check is prepared for such a case 1678 * and disable smp mode 1679 */ 1680 apic_version[new_apicid] = 1681 GET_APIC_VERSION(apic_read(APIC_LVR)); 1682 } 1683 } 1684 1685 /* 1686 * This initializes the IO-APIC and APIC hardware if this is 1687 * a UP kernel. 1688 */ 1689 int apic_version[MAX_APICS]; 1690 1691 int __init APIC_init_uniprocessor(void) 1692 { 1693 if (disable_apic) { 1694 pr_info("Apic disabled\n"); 1695 return -1; 1696 } 1697 #ifdef CONFIG_X86_64 1698 if (!cpu_has_apic) { 1699 disable_apic = 1; 1700 pr_info("Apic disabled by BIOS\n"); 1701 return -1; 1702 } 1703 #else 1704 if (!smp_found_config && !cpu_has_apic) 1705 return -1; 1706 1707 /* 1708 * Complain if the BIOS pretends there is one. 1709 */ 1710 if (!cpu_has_apic && 1711 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 1712 pr_err("BIOS bug, local APIC 0x%x not detected!...\n", 1713 boot_cpu_physical_apicid); 1714 return -1; 1715 } 1716 #endif 1717 1718 default_setup_apic_routing(); 1719 1720 verify_local_APIC(); 1721 connect_bsp_APIC(); 1722 1723 #ifdef CONFIG_X86_64 1724 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); 1725 #else 1726 /* 1727 * Hack: In case of kdump, after a crash, kernel might be booting 1728 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 1729 * might be zero if read from MP tables. Get it from LAPIC. 1730 */ 1731 # ifdef CONFIG_CRASH_DUMP 1732 boot_cpu_physical_apicid = read_apic_id(); 1733 # endif 1734 #endif 1735 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1736 setup_local_APIC(); 1737 1738 #ifdef CONFIG_X86_IO_APIC 1739 /* 1740 * Now enable IO-APICs, actually call clear_IO_APIC 1741 * We need clear_IO_APIC before enabling error vector 1742 */ 1743 if (!skip_ioapic_setup && nr_ioapics) 1744 enable_IO_APIC(); 1745 #endif 1746 1747 end_local_APIC_setup(); 1748 1749 #ifdef CONFIG_X86_IO_APIC 1750 if (smp_found_config && !skip_ioapic_setup && nr_ioapics) 1751 setup_IO_APIC(); 1752 else { 1753 nr_ioapics = 0; 1754 localise_nmi_watchdog(); 1755 } 1756 #else 1757 localise_nmi_watchdog(); 1758 #endif 1759 1760 x86_init.timers.setup_percpu_clockev(); 1761 #ifdef CONFIG_X86_64 1762 check_nmi_watchdog(); 1763 #endif 1764 1765 return 0; 1766 } 1767 1768 /* 1769 * Local APIC interrupts 1770 */ 1771 1772 /* 1773 * This interrupt should _never_ happen with our APIC/SMP architecture 1774 */ 1775 void smp_spurious_interrupt(struct pt_regs *regs) 1776 { 1777 u32 v; 1778 1779 exit_idle(); 1780 irq_enter(); 1781 /* 1782 * Check if this really is a spurious interrupt and ACK it 1783 * if it is a vectored one. Just in case... 1784 * Spurious interrupts should not be ACKed. 1785 */ 1786 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); 1787 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) 1788 ack_APIC_irq(); 1789 1790 inc_irq_stat(irq_spurious_count); 1791 1792 /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 1793 pr_info("spurious APIC interrupt on CPU#%d, " 1794 "should never happen.\n", smp_processor_id()); 1795 irq_exit(); 1796 } 1797 1798 /* 1799 * This interrupt should never happen with our APIC/SMP architecture 1800 */ 1801 void smp_error_interrupt(struct pt_regs *regs) 1802 { 1803 u32 v, v1; 1804 1805 exit_idle(); 1806 irq_enter(); 1807 /* First tickle the hardware, only then report what went on. -- REW */ 1808 v = apic_read(APIC_ESR); 1809 apic_write(APIC_ESR, 0); 1810 v1 = apic_read(APIC_ESR); 1811 ack_APIC_irq(); 1812 atomic_inc(&irq_err_count); 1813 1814 /* 1815 * Here is what the APIC error bits mean: 1816 * 0: Send CS error 1817 * 1: Receive CS error 1818 * 2: Send accept error 1819 * 3: Receive accept error 1820 * 4: Reserved 1821 * 5: Send illegal vector 1822 * 6: Received illegal vector 1823 * 7: Illegal register address 1824 */ 1825 pr_debug("APIC error on CPU%d: %02x(%02x)\n", 1826 smp_processor_id(), v , v1); 1827 irq_exit(); 1828 } 1829 1830 /** 1831 * connect_bsp_APIC - attach the APIC to the interrupt system 1832 */ 1833 void __init connect_bsp_APIC(void) 1834 { 1835 #ifdef CONFIG_X86_32 1836 if (pic_mode) { 1837 /* 1838 * Do not trust the local APIC being empty at bootup. 1839 */ 1840 clear_local_APIC(); 1841 /* 1842 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 1843 * local APIC to INT and NMI lines. 1844 */ 1845 apic_printk(APIC_VERBOSE, "leaving PIC mode, " 1846 "enabling APIC mode.\n"); 1847 imcr_pic_to_apic(); 1848 } 1849 #endif 1850 if (apic->enable_apic_mode) 1851 apic->enable_apic_mode(); 1852 } 1853 1854 /** 1855 * disconnect_bsp_APIC - detach the APIC from the interrupt system 1856 * @virt_wire_setup: indicates, whether virtual wire mode is selected 1857 * 1858 * Virtual wire mode is necessary to deliver legacy interrupts even when the 1859 * APIC is disabled. 1860 */ 1861 void disconnect_bsp_APIC(int virt_wire_setup) 1862 { 1863 unsigned int value; 1864 1865 #ifdef CONFIG_X86_32 1866 if (pic_mode) { 1867 /* 1868 * Put the board back into PIC mode (has an effect only on 1869 * certain older boards). Note that APIC interrupts, including 1870 * IPIs, won't work beyond this point! The only exception are 1871 * INIT IPIs. 1872 */ 1873 apic_printk(APIC_VERBOSE, "disabling APIC mode, " 1874 "entering PIC mode.\n"); 1875 imcr_apic_to_pic(); 1876 return; 1877 } 1878 #endif 1879 1880 /* Go back to Virtual Wire compatibility mode */ 1881 1882 /* For the spurious interrupt use vector F, and enable it */ 1883 value = apic_read(APIC_SPIV); 1884 value &= ~APIC_VECTOR_MASK; 1885 value |= APIC_SPIV_APIC_ENABLED; 1886 value |= 0xf; 1887 apic_write(APIC_SPIV, value); 1888 1889 if (!virt_wire_setup) { 1890 /* 1891 * For LVT0 make it edge triggered, active high, 1892 * external and enabled 1893 */ 1894 value = apic_read(APIC_LVT0); 1895 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1896 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1897 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1898 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1899 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 1900 apic_write(APIC_LVT0, value); 1901 } else { 1902 /* Disable LVT0 */ 1903 apic_write(APIC_LVT0, APIC_LVT_MASKED); 1904 } 1905 1906 /* 1907 * For LVT1 make it edge triggered, active high, 1908 * nmi and enabled 1909 */ 1910 value = apic_read(APIC_LVT1); 1911 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1912 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1913 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1914 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1915 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 1916 apic_write(APIC_LVT1, value); 1917 } 1918 1919 void __cpuinit generic_processor_info(int apicid, int version) 1920 { 1921 int cpu; 1922 1923 /* 1924 * Validate version 1925 */ 1926 if (version == 0x0) { 1927 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! " 1928 "fixing up to 0x10. (tell your hw vendor)\n", 1929 version); 1930 version = 0x10; 1931 } 1932 apic_version[apicid] = version; 1933 1934 if (num_processors >= nr_cpu_ids) { 1935 int max = nr_cpu_ids; 1936 int thiscpu = max + disabled_cpus; 1937 1938 pr_warning( 1939 "ACPI: NR_CPUS/possible_cpus limit of %i reached." 1940 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 1941 1942 disabled_cpus++; 1943 return; 1944 } 1945 1946 num_processors++; 1947 cpu = cpumask_next_zero(-1, cpu_present_mask); 1948 1949 if (version != apic_version[boot_cpu_physical_apicid]) 1950 WARN_ONCE(1, 1951 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n", 1952 apic_version[boot_cpu_physical_apicid], cpu, version); 1953 1954 physid_set(apicid, phys_cpu_present_map); 1955 if (apicid == boot_cpu_physical_apicid) { 1956 /* 1957 * x86_bios_cpu_apicid is required to have processors listed 1958 * in same order as logical cpu numbers. Hence the first 1959 * entry is BSP, and so on. 1960 */ 1961 cpu = 0; 1962 } 1963 if (apicid > max_physical_apicid) 1964 max_physical_apicid = apicid; 1965 1966 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 1967 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 1968 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 1969 #endif 1970 1971 set_cpu_possible(cpu, true); 1972 set_cpu_present(cpu, true); 1973 } 1974 1975 int hard_smp_processor_id(void) 1976 { 1977 return read_apic_id(); 1978 } 1979 1980 void default_init_apic_ldr(void) 1981 { 1982 unsigned long val; 1983 1984 apic_write(APIC_DFR, APIC_DFR_VALUE); 1985 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; 1986 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); 1987 apic_write(APIC_LDR, val); 1988 } 1989 1990 #ifdef CONFIG_X86_32 1991 int default_apicid_to_node(int logical_apicid) 1992 { 1993 #ifdef CONFIG_SMP 1994 return apicid_2_node[hard_smp_processor_id()]; 1995 #else 1996 return 0; 1997 #endif 1998 } 1999 #endif 2000 2001 /* 2002 * Power management 2003 */ 2004 #ifdef CONFIG_PM 2005 2006 static struct { 2007 /* 2008 * 'active' is true if the local APIC was enabled by us and 2009 * not the BIOS; this signifies that we are also responsible 2010 * for disabling it before entering apm/acpi suspend 2011 */ 2012 int active; 2013 /* r/w apic fields */ 2014 unsigned int apic_id; 2015 unsigned int apic_taskpri; 2016 unsigned int apic_ldr; 2017 unsigned int apic_dfr; 2018 unsigned int apic_spiv; 2019 unsigned int apic_lvtt; 2020 unsigned int apic_lvtpc; 2021 unsigned int apic_lvt0; 2022 unsigned int apic_lvt1; 2023 unsigned int apic_lvterr; 2024 unsigned int apic_tmict; 2025 unsigned int apic_tdcr; 2026 unsigned int apic_thmr; 2027 } apic_pm_state; 2028 2029 static int lapic_suspend(struct sys_device *dev, pm_message_t state) 2030 { 2031 unsigned long flags; 2032 int maxlvt; 2033 2034 if (!apic_pm_state.active) 2035 return 0; 2036 2037 maxlvt = lapic_get_maxlvt(); 2038 2039 apic_pm_state.apic_id = apic_read(APIC_ID); 2040 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2041 apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2042 apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2043 apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2044 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2045 if (maxlvt >= 4) 2046 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2047 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2048 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2049 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2050 apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2051 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 2052 #ifdef CONFIG_X86_THERMAL_VECTOR 2053 if (maxlvt >= 5) 2054 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2055 #endif 2056 2057 local_irq_save(flags); 2058 disable_local_APIC(); 2059 2060 if (intr_remapping_enabled) 2061 disable_intr_remapping(); 2062 2063 local_irq_restore(flags); 2064 return 0; 2065 } 2066 2067 static int lapic_resume(struct sys_device *dev) 2068 { 2069 unsigned int l, h; 2070 unsigned long flags; 2071 int maxlvt; 2072 int ret = 0; 2073 struct IO_APIC_route_entry **ioapic_entries = NULL; 2074 2075 if (!apic_pm_state.active) 2076 return 0; 2077 2078 local_irq_save(flags); 2079 if (intr_remapping_enabled) { 2080 ioapic_entries = alloc_ioapic_entries(); 2081 if (!ioapic_entries) { 2082 WARN(1, "Alloc ioapic_entries in lapic resume failed."); 2083 ret = -ENOMEM; 2084 goto restore; 2085 } 2086 2087 ret = save_IO_APIC_setup(ioapic_entries); 2088 if (ret) { 2089 WARN(1, "Saving IO-APIC state failed: %d\n", ret); 2090 free_ioapic_entries(ioapic_entries); 2091 goto restore; 2092 } 2093 2094 mask_IO_APIC_setup(ioapic_entries); 2095 legacy_pic->mask_all(); 2096 } 2097 2098 if (x2apic_mode) 2099 enable_x2apic(); 2100 else { 2101 /* 2102 * Make sure the APICBASE points to the right address 2103 * 2104 * FIXME! This will be wrong if we ever support suspend on 2105 * SMP! We'll need to do this as part of the CPU restore! 2106 */ 2107 rdmsr(MSR_IA32_APICBASE, l, h); 2108 l &= ~MSR_IA32_APICBASE_BASE; 2109 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2110 wrmsr(MSR_IA32_APICBASE, l, h); 2111 } 2112 2113 maxlvt = lapic_get_maxlvt(); 2114 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2115 apic_write(APIC_ID, apic_pm_state.apic_id); 2116 apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2117 apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2118 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2119 apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2120 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2121 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2122 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) 2123 if (maxlvt >= 5) 2124 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2125 #endif 2126 if (maxlvt >= 4) 2127 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2128 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2129 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2130 apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2131 apic_write(APIC_ESR, 0); 2132 apic_read(APIC_ESR); 2133 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2134 apic_write(APIC_ESR, 0); 2135 apic_read(APIC_ESR); 2136 2137 if (intr_remapping_enabled) { 2138 reenable_intr_remapping(x2apic_mode); 2139 legacy_pic->restore_mask(); 2140 restore_IO_APIC_setup(ioapic_entries); 2141 free_ioapic_entries(ioapic_entries); 2142 } 2143 restore: 2144 local_irq_restore(flags); 2145 2146 return ret; 2147 } 2148 2149 /* 2150 * This device has no shutdown method - fully functioning local APICs 2151 * are needed on every CPU up until machine_halt/restart/poweroff. 2152 */ 2153 2154 static struct sysdev_class lapic_sysclass = { 2155 .name = "lapic", 2156 .resume = lapic_resume, 2157 .suspend = lapic_suspend, 2158 }; 2159 2160 static struct sys_device device_lapic = { 2161 .id = 0, 2162 .cls = &lapic_sysclass, 2163 }; 2164 2165 static void __cpuinit apic_pm_activate(void) 2166 { 2167 apic_pm_state.active = 1; 2168 } 2169 2170 static int __init init_lapic_sysfs(void) 2171 { 2172 int error; 2173 2174 if (!cpu_has_apic) 2175 return 0; 2176 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2177 2178 error = sysdev_class_register(&lapic_sysclass); 2179 if (!error) 2180 error = sysdev_register(&device_lapic); 2181 return error; 2182 } 2183 2184 /* local apic needs to resume before other devices access its registers. */ 2185 core_initcall(init_lapic_sysfs); 2186 2187 #else /* CONFIG_PM */ 2188 2189 static void apic_pm_activate(void) { } 2190 2191 #endif /* CONFIG_PM */ 2192 2193 #ifdef CONFIG_X86_64 2194 2195 static int __cpuinit apic_cluster_num(void) 2196 { 2197 int i, clusters, zeros; 2198 unsigned id; 2199 u16 *bios_cpu_apicid; 2200 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); 2201 2202 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); 2203 bitmap_zero(clustermap, NUM_APIC_CLUSTERS); 2204 2205 for (i = 0; i < nr_cpu_ids; i++) { 2206 /* are we being called early in kernel startup? */ 2207 if (bios_cpu_apicid) { 2208 id = bios_cpu_apicid[i]; 2209 } else if (i < nr_cpu_ids) { 2210 if (cpu_present(i)) 2211 id = per_cpu(x86_bios_cpu_apicid, i); 2212 else 2213 continue; 2214 } else 2215 break; 2216 2217 if (id != BAD_APICID) 2218 __set_bit(APIC_CLUSTERID(id), clustermap); 2219 } 2220 2221 /* Problem: Partially populated chassis may not have CPUs in some of 2222 * the APIC clusters they have been allocated. Only present CPUs have 2223 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. 2224 * Since clusters are allocated sequentially, count zeros only if 2225 * they are bounded by ones. 2226 */ 2227 clusters = 0; 2228 zeros = 0; 2229 for (i = 0; i < NUM_APIC_CLUSTERS; i++) { 2230 if (test_bit(i, clustermap)) { 2231 clusters += 1 + zeros; 2232 zeros = 0; 2233 } else 2234 ++zeros; 2235 } 2236 2237 return clusters; 2238 } 2239 2240 static int __cpuinitdata multi_checked; 2241 static int __cpuinitdata multi; 2242 2243 static int __cpuinit set_multi(const struct dmi_system_id *d) 2244 { 2245 if (multi) 2246 return 0; 2247 pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2248 multi = 1; 2249 return 0; 2250 } 2251 2252 static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = { 2253 { 2254 .callback = set_multi, 2255 .ident = "IBM System Summit2", 2256 .matches = { 2257 DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2258 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2259 }, 2260 }, 2261 {} 2262 }; 2263 2264 static void __cpuinit dmi_check_multi(void) 2265 { 2266 if (multi_checked) 2267 return; 2268 2269 dmi_check_system(multi_dmi_table); 2270 multi_checked = 1; 2271 } 2272 2273 /* 2274 * apic_is_clustered_box() -- Check if we can expect good TSC 2275 * 2276 * Thus far, the major user of this is IBM's Summit2 series: 2277 * Clustered boxes may have unsynced TSC problems if they are 2278 * multi-chassis. 2279 * Use DMI to check them 2280 */ 2281 __cpuinit int apic_is_clustered_box(void) 2282 { 2283 dmi_check_multi(); 2284 if (multi) 2285 return 1; 2286 2287 if (!is_vsmp_box()) 2288 return 0; 2289 2290 /* 2291 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are 2292 * not guaranteed to be synced between boards 2293 */ 2294 if (apic_cluster_num() > 1) 2295 return 1; 2296 2297 return 0; 2298 } 2299 #endif 2300 2301 /* 2302 * APIC command line parameters 2303 */ 2304 static int __init setup_disableapic(char *arg) 2305 { 2306 disable_apic = 1; 2307 setup_clear_cpu_cap(X86_FEATURE_APIC); 2308 return 0; 2309 } 2310 early_param("disableapic", setup_disableapic); 2311 2312 /* same as disableapic, for compatibility */ 2313 static int __init setup_nolapic(char *arg) 2314 { 2315 return setup_disableapic(arg); 2316 } 2317 early_param("nolapic", setup_nolapic); 2318 2319 static int __init parse_lapic_timer_c2_ok(char *arg) 2320 { 2321 local_apic_timer_c2_ok = 1; 2322 return 0; 2323 } 2324 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2325 2326 static int __init parse_disable_apic_timer(char *arg) 2327 { 2328 disable_apic_timer = 1; 2329 return 0; 2330 } 2331 early_param("noapictimer", parse_disable_apic_timer); 2332 2333 static int __init parse_nolapic_timer(char *arg) 2334 { 2335 disable_apic_timer = 1; 2336 return 0; 2337 } 2338 early_param("nolapic_timer", parse_nolapic_timer); 2339 2340 static int __init apic_set_verbosity(char *arg) 2341 { 2342 if (!arg) { 2343 #ifdef CONFIG_X86_64 2344 skip_ioapic_setup = 0; 2345 return 0; 2346 #endif 2347 return -EINVAL; 2348 } 2349 2350 if (strcmp("debug", arg) == 0) 2351 apic_verbosity = APIC_DEBUG; 2352 else if (strcmp("verbose", arg) == 0) 2353 apic_verbosity = APIC_VERBOSE; 2354 else { 2355 pr_warning("APIC Verbosity level %s not recognised" 2356 " use apic=verbose or apic=debug\n", arg); 2357 return -EINVAL; 2358 } 2359 2360 return 0; 2361 } 2362 early_param("apic", apic_set_verbosity); 2363 2364 static int __init lapic_insert_resource(void) 2365 { 2366 if (!apic_phys) 2367 return -1; 2368 2369 /* Put local APIC into the resource map. */ 2370 lapic_resource.start = apic_phys; 2371 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2372 insert_resource(&iomem_resource, &lapic_resource); 2373 2374 return 0; 2375 } 2376 2377 /* 2378 * need call insert after e820_reserve_resources() 2379 * that is using request_resource 2380 */ 2381 late_initcall(lapic_insert_resource); 2382