1 /* 2 * Firmware replacement code. 3 * 4 * Work around broken BIOSes that don't set an aperture or only set the 5 * aperture in the AGP bridge. 6 * If all fails map the aperture over some low memory. This is cheaper than 7 * doing bounce buffering. The memory is lost. This is done at early boot 8 * because only the bootmem allocator can allocate 32+MB. 9 * 10 * Copyright 2002 Andi Kleen, SuSE Labs. 11 */ 12 #include <linux/kernel.h> 13 #include <linux/types.h> 14 #include <linux/init.h> 15 #include <linux/bootmem.h> 16 #include <linux/mmzone.h> 17 #include <linux/pci_ids.h> 18 #include <linux/pci.h> 19 #include <linux/bitops.h> 20 #include <linux/ioport.h> 21 #include <asm/e820.h> 22 #include <asm/io.h> 23 #include <asm/gart.h> 24 #include <asm/pci-direct.h> 25 #include <asm/dma.h> 26 #include <asm/k8.h> 27 28 int gart_iommu_aperture; 29 int gart_iommu_aperture_disabled __initdata = 0; 30 int gart_iommu_aperture_allowed __initdata = 0; 31 32 int fallback_aper_order __initdata = 1; /* 64MB */ 33 int fallback_aper_force __initdata = 0; 34 35 int fix_aperture __initdata = 1; 36 37 static struct resource gart_resource = { 38 .name = "GART", 39 .flags = IORESOURCE_MEM, 40 }; 41 42 static void __init insert_aperture_resource(u32 aper_base, u32 aper_size) 43 { 44 gart_resource.start = aper_base; 45 gart_resource.end = aper_base + aper_size - 1; 46 insert_resource(&iomem_resource, &gart_resource); 47 } 48 49 /* This code runs before the PCI subsystem is initialized, so just 50 access the northbridge directly. */ 51 52 static u32 __init allocate_aperture(void) 53 { 54 u32 aper_size; 55 void *p; 56 57 if (fallback_aper_order > 7) 58 fallback_aper_order = 7; 59 aper_size = (32 * 1024 * 1024) << fallback_aper_order; 60 61 /* 62 * Aperture has to be naturally aligned. This means a 2GB aperture 63 * won't have much chance of finding a place in the lower 4GB of 64 * memory. Unfortunately we cannot move it up because that would 65 * make the IOMMU useless. 66 */ 67 p = __alloc_bootmem_nopanic(aper_size, aper_size, 0); 68 if (!p || __pa(p)+aper_size > 0xffffffff) { 69 printk(KERN_ERR 70 "Cannot allocate aperture memory hole (%p,%uK)\n", 71 p, aper_size>>10); 72 if (p) 73 free_bootmem(__pa(p), aper_size); 74 return 0; 75 } 76 printk(KERN_INFO "Mapping aperture over %d KB of RAM @ %lx\n", 77 aper_size >> 10, __pa(p)); 78 insert_aperture_resource((u32)__pa(p), aper_size); 79 80 return (u32)__pa(p); 81 } 82 83 static int __init aperture_valid(u64 aper_base, u32 aper_size) 84 { 85 if (!aper_base) 86 return 0; 87 88 if (aper_base + aper_size > 0x100000000UL) { 89 printk(KERN_ERR "Aperture beyond 4GB. Ignoring.\n"); 90 return 0; 91 } 92 if (e820_any_mapped(aper_base, aper_base + aper_size, E820_RAM)) { 93 printk(KERN_ERR "Aperture pointing to e820 RAM. Ignoring.\n"); 94 return 0; 95 } 96 if (aper_size < 64*1024*1024) { 97 printk(KERN_ERR "Aperture too small (%d MB)\n", aper_size>>20); 98 return 0; 99 } 100 101 return 1; 102 } 103 104 /* Find a PCI capability */ 105 static __u32 __init find_cap(int num, int slot, int func, int cap) 106 { 107 int bytes; 108 u8 pos; 109 110 if (!(read_pci_config_16(num, slot, func, PCI_STATUS) & 111 PCI_STATUS_CAP_LIST)) 112 return 0; 113 114 pos = read_pci_config_byte(num, slot, func, PCI_CAPABILITY_LIST); 115 for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) { 116 u8 id; 117 118 pos &= ~3; 119 id = read_pci_config_byte(num, slot, func, pos+PCI_CAP_LIST_ID); 120 if (id == 0xff) 121 break; 122 if (id == cap) 123 return pos; 124 pos = read_pci_config_byte(num, slot, func, 125 pos+PCI_CAP_LIST_NEXT); 126 } 127 return 0; 128 } 129 130 /* Read a standard AGPv3 bridge header */ 131 static __u32 __init read_agp(int num, int slot, int func, int cap, u32 *order) 132 { 133 u32 apsize; 134 u32 apsizereg; 135 int nbits; 136 u32 aper_low, aper_hi; 137 u64 aper; 138 139 printk(KERN_INFO "AGP bridge at %02x:%02x:%02x\n", num, slot, func); 140 apsizereg = read_pci_config_16(num, slot, func, cap + 0x14); 141 if (apsizereg == 0xffffffff) { 142 printk(KERN_ERR "APSIZE in AGP bridge unreadable\n"); 143 return 0; 144 } 145 146 apsize = apsizereg & 0xfff; 147 /* Some BIOS use weird encodings not in the AGPv3 table. */ 148 if (apsize & 0xff) 149 apsize |= 0xf00; 150 nbits = hweight16(apsize); 151 *order = 7 - nbits; 152 if ((int)*order < 0) /* < 32MB */ 153 *order = 0; 154 155 aper_low = read_pci_config(num, slot, func, 0x10); 156 aper_hi = read_pci_config(num, slot, func, 0x14); 157 aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32); 158 159 printk(KERN_INFO "Aperture from AGP @ %Lx size %u MB (APSIZE %x)\n", 160 aper, 32 << *order, apsizereg); 161 162 if (!aperture_valid(aper, (32*1024*1024) << *order)) 163 return 0; 164 return (u32)aper; 165 } 166 167 /* 168 * Look for an AGP bridge. Windows only expects the aperture in the 169 * AGP bridge and some BIOS forget to initialize the Northbridge too. 170 * Work around this here. 171 * 172 * Do an PCI bus scan by hand because we're running before the PCI 173 * subsystem. 174 * 175 * All K8 AGP bridges are AGPv3 compliant, so we can do this scan 176 * generically. It's probably overkill to always scan all slots because 177 * the AGP bridges should be always an own bus on the HT hierarchy, 178 * but do it here for future safety. 179 */ 180 static __u32 __init search_agp_bridge(u32 *order, int *valid_agp) 181 { 182 int num, slot, func; 183 184 /* Poor man's PCI discovery */ 185 for (num = 0; num < 256; num++) { 186 for (slot = 0; slot < 32; slot++) { 187 for (func = 0; func < 8; func++) { 188 u32 class, cap; 189 u8 type; 190 class = read_pci_config(num, slot, func, 191 PCI_CLASS_REVISION); 192 if (class == 0xffffffff) 193 break; 194 195 switch (class >> 16) { 196 case PCI_CLASS_BRIDGE_HOST: 197 case PCI_CLASS_BRIDGE_OTHER: /* needed? */ 198 /* AGP bridge? */ 199 cap = find_cap(num, slot, func, 200 PCI_CAP_ID_AGP); 201 if (!cap) 202 break; 203 *valid_agp = 1; 204 return read_agp(num, slot, func, cap, 205 order); 206 } 207 208 /* No multi-function device? */ 209 type = read_pci_config_byte(num, slot, func, 210 PCI_HEADER_TYPE); 211 if (!(type & 0x80)) 212 break; 213 } 214 } 215 } 216 printk(KERN_INFO "No AGP bridge found\n"); 217 218 return 0; 219 } 220 221 static int gart_fix_e820 __initdata = 1; 222 223 static int __init parse_gart_mem(char *p) 224 { 225 if (!p) 226 return -EINVAL; 227 228 if (!strncmp(p, "off", 3)) 229 gart_fix_e820 = 0; 230 else if (!strncmp(p, "on", 2)) 231 gart_fix_e820 = 1; 232 233 return 0; 234 } 235 early_param("gart_fix_e820", parse_gart_mem); 236 237 void __init early_gart_iommu_check(void) 238 { 239 /* 240 * in case it is enabled before, esp for kexec/kdump, 241 * previous kernel already enable that. memset called 242 * by allocate_aperture/__alloc_bootmem_nopanic cause restart. 243 * or second kernel have different position for GART hole. and new 244 * kernel could use hole as RAM that is still used by GART set by 245 * first kernel 246 * or BIOS forget to put that in reserved. 247 * try to update e820 to make that region as reserved. 248 */ 249 int fix, num; 250 u32 ctl; 251 u32 aper_size = 0, aper_order = 0, last_aper_order = 0; 252 u64 aper_base = 0, last_aper_base = 0; 253 int aper_enabled = 0, last_aper_enabled = 0; 254 255 if (!early_pci_allowed()) 256 return; 257 258 fix = 0; 259 for (num = 24; num < 32; num++) { 260 if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00))) 261 continue; 262 263 ctl = read_pci_config(0, num, 3, 0x90); 264 aper_enabled = ctl & 1; 265 aper_order = (ctl >> 1) & 7; 266 aper_size = (32 * 1024 * 1024) << aper_order; 267 aper_base = read_pci_config(0, num, 3, 0x94) & 0x7fff; 268 aper_base <<= 25; 269 270 if ((last_aper_order && aper_order != last_aper_order) || 271 (last_aper_base && aper_base != last_aper_base) || 272 (last_aper_enabled && aper_enabled != last_aper_enabled)) { 273 fix = 1; 274 break; 275 } 276 last_aper_order = aper_order; 277 last_aper_base = aper_base; 278 last_aper_enabled = aper_enabled; 279 } 280 281 if (!fix && !aper_enabled) 282 return; 283 284 if (!aper_base || !aper_size || aper_base + aper_size > 0x100000000UL) 285 fix = 1; 286 287 if (gart_fix_e820 && !fix && aper_enabled) { 288 if (e820_any_mapped(aper_base, aper_base + aper_size, 289 E820_RAM)) { 290 /* reserved it, so we can resuse it in second kernel */ 291 printk(KERN_INFO "update e820 for GART\n"); 292 add_memory_region(aper_base, aper_size, E820_RESERVED); 293 update_e820(); 294 } 295 return; 296 } 297 298 /* different nodes have different setting, disable them all at first*/ 299 for (num = 24; num < 32; num++) { 300 if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00))) 301 continue; 302 303 ctl = read_pci_config(0, num, 3, 0x90); 304 ctl &= ~1; 305 write_pci_config(0, num, 3, 0x90, ctl); 306 } 307 308 } 309 310 void __init gart_iommu_hole_init(void) 311 { 312 u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0; 313 u64 aper_base, last_aper_base = 0; 314 int fix, num, valid_agp = 0; 315 int node; 316 317 if (gart_iommu_aperture_disabled || !fix_aperture || 318 !early_pci_allowed()) 319 return; 320 321 printk(KERN_INFO "Checking aperture...\n"); 322 323 fix = 0; 324 node = 0; 325 for (num = 24; num < 32; num++) { 326 if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00))) 327 continue; 328 329 iommu_detected = 1; 330 gart_iommu_aperture = 1; 331 332 aper_order = (read_pci_config(0, num, 3, 0x90) >> 1) & 7; 333 aper_size = (32 * 1024 * 1024) << aper_order; 334 aper_base = read_pci_config(0, num, 3, 0x94) & 0x7fff; 335 aper_base <<= 25; 336 337 printk(KERN_INFO "Node %d: aperture @ %Lx size %u MB\n", 338 node, aper_base, aper_size >> 20); 339 node++; 340 341 if (!aperture_valid(aper_base, aper_size)) { 342 fix = 1; 343 break; 344 } 345 346 if ((last_aper_order && aper_order != last_aper_order) || 347 (last_aper_base && aper_base != last_aper_base)) { 348 fix = 1; 349 break; 350 } 351 last_aper_order = aper_order; 352 last_aper_base = aper_base; 353 } 354 355 if (!fix && !fallback_aper_force) { 356 if (last_aper_base) { 357 unsigned long n = (32 * 1024 * 1024) << last_aper_order; 358 359 insert_aperture_resource((u32)last_aper_base, n); 360 } 361 return; 362 } 363 364 if (!fallback_aper_force) 365 aper_alloc = search_agp_bridge(&aper_order, &valid_agp); 366 367 if (aper_alloc) { 368 /* Got the aperture from the AGP bridge */ 369 } else if (swiotlb && !valid_agp) { 370 /* Do nothing */ 371 } else if ((!no_iommu && end_pfn > MAX_DMA32_PFN) || 372 force_iommu || 373 valid_agp || 374 fallback_aper_force) { 375 printk(KERN_ERR 376 "Your BIOS doesn't leave a aperture memory hole\n"); 377 printk(KERN_ERR 378 "Please enable the IOMMU option in the BIOS setup\n"); 379 printk(KERN_ERR 380 "This costs you %d MB of RAM\n", 381 32 << fallback_aper_order); 382 383 aper_order = fallback_aper_order; 384 aper_alloc = allocate_aperture(); 385 if (!aper_alloc) { 386 /* 387 * Could disable AGP and IOMMU here, but it's 388 * probably not worth it. But the later users 389 * cannot deal with bad apertures and turning 390 * on the aperture over memory causes very 391 * strange problems, so it's better to panic 392 * early. 393 */ 394 panic("Not enough memory for aperture"); 395 } 396 } else { 397 return; 398 } 399 400 /* Fix up the north bridges */ 401 for (num = 24; num < 32; num++) { 402 if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00))) 403 continue; 404 405 /* 406 * Don't enable translation yet. That is done later. 407 * Assume this BIOS didn't initialise the GART so 408 * just overwrite all previous bits 409 */ 410 write_pci_config(0, num, 3, 0x90, aper_order<<1); 411 write_pci_config(0, num, 3, 0x94, aper_alloc>>25); 412 } 413 } 414