1 /* 2 * Firmware replacement code. 3 * 4 * Work around broken BIOSes that don't set an aperture, only set the 5 * aperture in the AGP bridge, or set too small aperture. 6 * 7 * If all fails map the aperture over some low memory. This is cheaper than 8 * doing bounce buffering. The memory is lost. This is done at early boot 9 * because only the bootmem allocator can allocate 32+MB. 10 * 11 * Copyright 2002 Andi Kleen, SuSE Labs. 12 */ 13 #define pr_fmt(fmt) "AGP: " fmt 14 15 #include <linux/kernel.h> 16 #include <linux/types.h> 17 #include <linux/init.h> 18 #include <linux/memblock.h> 19 #include <linux/mmzone.h> 20 #include <linux/pci_ids.h> 21 #include <linux/pci.h> 22 #include <linux/bitops.h> 23 #include <linux/suspend.h> 24 #include <asm/e820.h> 25 #include <asm/io.h> 26 #include <asm/iommu.h> 27 #include <asm/gart.h> 28 #include <asm/pci-direct.h> 29 #include <asm/dma.h> 30 #include <asm/amd_nb.h> 31 #include <asm/x86_init.h> 32 33 /* 34 * Using 512M as goal, in case kexec will load kernel_big 35 * that will do the on-position decompress, and could overlap with 36 * with the gart aperture that is used. 37 * Sequence: 38 * kernel_small 39 * ==> kexec (with kdump trigger path or gart still enabled) 40 * ==> kernel_small (gart area become e820_reserved) 41 * ==> kexec (with kdump trigger path or gart still enabled) 42 * ==> kerne_big (uncompressed size will be big than 64M or 128M) 43 * So don't use 512M below as gart iommu, leave the space for kernel 44 * code for safe. 45 */ 46 #define GART_MIN_ADDR (512ULL << 20) 47 #define GART_MAX_ADDR (1ULL << 32) 48 49 int gart_iommu_aperture; 50 int gart_iommu_aperture_disabled __initdata; 51 int gart_iommu_aperture_allowed __initdata; 52 53 int fallback_aper_order __initdata = 1; /* 64MB */ 54 int fallback_aper_force __initdata; 55 56 int fix_aperture __initdata = 1; 57 58 /* This code runs before the PCI subsystem is initialized, so just 59 access the northbridge directly. */ 60 61 static u32 __init allocate_aperture(void) 62 { 63 u32 aper_size; 64 unsigned long addr; 65 66 /* aper_size should <= 1G */ 67 if (fallback_aper_order > 5) 68 fallback_aper_order = 5; 69 aper_size = (32 * 1024 * 1024) << fallback_aper_order; 70 71 /* 72 * Aperture has to be naturally aligned. This means a 2GB aperture 73 * won't have much chance of finding a place in the lower 4GB of 74 * memory. Unfortunately we cannot move it up because that would 75 * make the IOMMU useless. 76 */ 77 addr = memblock_find_in_range(GART_MIN_ADDR, GART_MAX_ADDR, 78 aper_size, aper_size); 79 if (!addr) { 80 pr_err("Cannot allocate aperture memory hole [mem %#010lx-%#010lx] (%uKB)\n", 81 addr, addr + aper_size - 1, aper_size >> 10); 82 return 0; 83 } 84 memblock_reserve(addr, aper_size); 85 pr_info("Mapping aperture over RAM [mem %#010lx-%#010lx] (%uKB)\n", 86 addr, addr + aper_size - 1, aper_size >> 10); 87 register_nosave_region(addr >> PAGE_SHIFT, 88 (addr+aper_size) >> PAGE_SHIFT); 89 90 return (u32)addr; 91 } 92 93 94 /* Find a PCI capability */ 95 static u32 __init find_cap(int bus, int slot, int func, int cap) 96 { 97 int bytes; 98 u8 pos; 99 100 if (!(read_pci_config_16(bus, slot, func, PCI_STATUS) & 101 PCI_STATUS_CAP_LIST)) 102 return 0; 103 104 pos = read_pci_config_byte(bus, slot, func, PCI_CAPABILITY_LIST); 105 for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) { 106 u8 id; 107 108 pos &= ~3; 109 id = read_pci_config_byte(bus, slot, func, pos+PCI_CAP_LIST_ID); 110 if (id == 0xff) 111 break; 112 if (id == cap) 113 return pos; 114 pos = read_pci_config_byte(bus, slot, func, 115 pos+PCI_CAP_LIST_NEXT); 116 } 117 return 0; 118 } 119 120 /* Read a standard AGPv3 bridge header */ 121 static u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order) 122 { 123 u32 apsize; 124 u32 apsizereg; 125 int nbits; 126 u32 aper_low, aper_hi; 127 u64 aper; 128 u32 old_order; 129 130 pr_info("pci 0000:%02x:%02x:%02x: AGP bridge\n", bus, slot, func); 131 apsizereg = read_pci_config_16(bus, slot, func, cap + 0x14); 132 if (apsizereg == 0xffffffff) { 133 pr_err("pci 0000:%02x:%02x.%d: APSIZE unreadable\n", 134 bus, slot, func); 135 return 0; 136 } 137 138 /* old_order could be the value from NB gart setting */ 139 old_order = *order; 140 141 apsize = apsizereg & 0xfff; 142 /* Some BIOS use weird encodings not in the AGPv3 table. */ 143 if (apsize & 0xff) 144 apsize |= 0xf00; 145 nbits = hweight16(apsize); 146 *order = 7 - nbits; 147 if ((int)*order < 0) /* < 32MB */ 148 *order = 0; 149 150 aper_low = read_pci_config(bus, slot, func, 0x10); 151 aper_hi = read_pci_config(bus, slot, func, 0x14); 152 aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32); 153 154 /* 155 * On some sick chips, APSIZE is 0. It means it wants 4G 156 * so let double check that order, and lets trust AMD NB settings: 157 */ 158 pr_info("pci 0000:%02x:%02x.%d: AGP aperture [bus addr %#010Lx-%#010Lx] (old size %uMB)\n", 159 bus, slot, func, aper, aper + (32ULL << (old_order + 20)) - 1, 160 32 << old_order); 161 if (aper + (32ULL<<(20 + *order)) > 0x100000000ULL) { 162 pr_info("pci 0000:%02x:%02x.%d: AGP aperture size %uMB (APSIZE %#x) is not right, using settings from NB\n", 163 bus, slot, func, 32 << *order, apsizereg); 164 *order = old_order; 165 } 166 167 pr_info("pci 0000:%02x:%02x.%d: AGP aperture [bus addr %#010Lx-%#010Lx] (%uMB, APSIZE %#x)\n", 168 bus, slot, func, aper, aper + (32ULL << (*order + 20)) - 1, 169 32 << *order, apsizereg); 170 171 if (!aperture_valid(aper, (32*1024*1024) << *order, 32<<20)) 172 return 0; 173 return (u32)aper; 174 } 175 176 /* 177 * Look for an AGP bridge. Windows only expects the aperture in the 178 * AGP bridge and some BIOS forget to initialize the Northbridge too. 179 * Work around this here. 180 * 181 * Do an PCI bus scan by hand because we're running before the PCI 182 * subsystem. 183 * 184 * All AMD AGP bridges are AGPv3 compliant, so we can do this scan 185 * generically. It's probably overkill to always scan all slots because 186 * the AGP bridges should be always an own bus on the HT hierarchy, 187 * but do it here for future safety. 188 */ 189 static u32 __init search_agp_bridge(u32 *order, int *valid_agp) 190 { 191 int bus, slot, func; 192 193 /* Poor man's PCI discovery */ 194 for (bus = 0; bus < 256; bus++) { 195 for (slot = 0; slot < 32; slot++) { 196 for (func = 0; func < 8; func++) { 197 u32 class, cap; 198 u8 type; 199 class = read_pci_config(bus, slot, func, 200 PCI_CLASS_REVISION); 201 if (class == 0xffffffff) 202 break; 203 204 switch (class >> 16) { 205 case PCI_CLASS_BRIDGE_HOST: 206 case PCI_CLASS_BRIDGE_OTHER: /* needed? */ 207 /* AGP bridge? */ 208 cap = find_cap(bus, slot, func, 209 PCI_CAP_ID_AGP); 210 if (!cap) 211 break; 212 *valid_agp = 1; 213 return read_agp(bus, slot, func, cap, 214 order); 215 } 216 217 /* No multi-function device? */ 218 type = read_pci_config_byte(bus, slot, func, 219 PCI_HEADER_TYPE); 220 if (!(type & 0x80)) 221 break; 222 } 223 } 224 } 225 pr_info("No AGP bridge found\n"); 226 227 return 0; 228 } 229 230 static int gart_fix_e820 __initdata = 1; 231 232 static int __init parse_gart_mem(char *p) 233 { 234 if (!p) 235 return -EINVAL; 236 237 if (!strncmp(p, "off", 3)) 238 gart_fix_e820 = 0; 239 else if (!strncmp(p, "on", 2)) 240 gart_fix_e820 = 1; 241 242 return 0; 243 } 244 early_param("gart_fix_e820", parse_gart_mem); 245 246 void __init early_gart_iommu_check(void) 247 { 248 /* 249 * in case it is enabled before, esp for kexec/kdump, 250 * previous kernel already enable that. memset called 251 * by allocate_aperture/__alloc_bootmem_nopanic cause restart. 252 * or second kernel have different position for GART hole. and new 253 * kernel could use hole as RAM that is still used by GART set by 254 * first kernel 255 * or BIOS forget to put that in reserved. 256 * try to update e820 to make that region as reserved. 257 */ 258 u32 agp_aper_order = 0; 259 int i, fix, slot, valid_agp = 0; 260 u32 ctl; 261 u32 aper_size = 0, aper_order = 0, last_aper_order = 0; 262 u64 aper_base = 0, last_aper_base = 0; 263 int aper_enabled = 0, last_aper_enabled = 0, last_valid = 0; 264 265 if (!early_pci_allowed()) 266 return; 267 268 /* This is mostly duplicate of iommu_hole_init */ 269 search_agp_bridge(&agp_aper_order, &valid_agp); 270 271 fix = 0; 272 for (i = 0; amd_nb_bus_dev_ranges[i].dev_limit; i++) { 273 int bus; 274 int dev_base, dev_limit; 275 276 bus = amd_nb_bus_dev_ranges[i].bus; 277 dev_base = amd_nb_bus_dev_ranges[i].dev_base; 278 dev_limit = amd_nb_bus_dev_ranges[i].dev_limit; 279 280 for (slot = dev_base; slot < dev_limit; slot++) { 281 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00))) 282 continue; 283 284 ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL); 285 aper_enabled = ctl & GARTEN; 286 aper_order = (ctl >> 1) & 7; 287 aper_size = (32 * 1024 * 1024) << aper_order; 288 aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff; 289 aper_base <<= 25; 290 291 if (last_valid) { 292 if ((aper_order != last_aper_order) || 293 (aper_base != last_aper_base) || 294 (aper_enabled != last_aper_enabled)) { 295 fix = 1; 296 break; 297 } 298 } 299 300 last_aper_order = aper_order; 301 last_aper_base = aper_base; 302 last_aper_enabled = aper_enabled; 303 last_valid = 1; 304 } 305 } 306 307 if (!fix && !aper_enabled) 308 return; 309 310 if (!aper_base || !aper_size || aper_base + aper_size > 0x100000000UL) 311 fix = 1; 312 313 if (gart_fix_e820 && !fix && aper_enabled) { 314 if (e820_any_mapped(aper_base, aper_base + aper_size, 315 E820_RAM)) { 316 /* reserve it, so we can reuse it in second kernel */ 317 pr_info("e820: reserve [mem %#010Lx-%#010Lx] for GART\n", 318 aper_base, aper_base + aper_size - 1); 319 e820_add_region(aper_base, aper_size, E820_RESERVED); 320 update_e820(); 321 } 322 } 323 324 if (valid_agp) 325 return; 326 327 /* disable them all at first */ 328 for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) { 329 int bus; 330 int dev_base, dev_limit; 331 332 bus = amd_nb_bus_dev_ranges[i].bus; 333 dev_base = amd_nb_bus_dev_ranges[i].dev_base; 334 dev_limit = amd_nb_bus_dev_ranges[i].dev_limit; 335 336 for (slot = dev_base; slot < dev_limit; slot++) { 337 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00))) 338 continue; 339 340 ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL); 341 ctl &= ~GARTEN; 342 write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl); 343 } 344 } 345 346 } 347 348 static int __initdata printed_gart_size_msg; 349 350 int __init gart_iommu_hole_init(void) 351 { 352 u32 agp_aper_base = 0, agp_aper_order = 0; 353 u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0; 354 u64 aper_base, last_aper_base = 0; 355 int fix, slot, valid_agp = 0; 356 int i, node; 357 358 if (gart_iommu_aperture_disabled || !fix_aperture || 359 !early_pci_allowed()) 360 return -ENODEV; 361 362 pr_info("Checking aperture...\n"); 363 364 if (!fallback_aper_force) 365 agp_aper_base = search_agp_bridge(&agp_aper_order, &valid_agp); 366 367 fix = 0; 368 node = 0; 369 for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) { 370 int bus; 371 int dev_base, dev_limit; 372 u32 ctl; 373 374 bus = amd_nb_bus_dev_ranges[i].bus; 375 dev_base = amd_nb_bus_dev_ranges[i].dev_base; 376 dev_limit = amd_nb_bus_dev_ranges[i].dev_limit; 377 378 for (slot = dev_base; slot < dev_limit; slot++) { 379 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00))) 380 continue; 381 382 iommu_detected = 1; 383 gart_iommu_aperture = 1; 384 x86_init.iommu.iommu_init = gart_iommu_init; 385 386 ctl = read_pci_config(bus, slot, 3, 387 AMD64_GARTAPERTURECTL); 388 389 /* 390 * Before we do anything else disable the GART. It may 391 * still be enabled if we boot into a crash-kernel here. 392 * Reconfiguring the GART while it is enabled could have 393 * unknown side-effects. 394 */ 395 ctl &= ~GARTEN; 396 write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl); 397 398 aper_order = (ctl >> 1) & 7; 399 aper_size = (32 * 1024 * 1024) << aper_order; 400 aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff; 401 aper_base <<= 25; 402 403 pr_info("Node %d: aperture [bus addr %#010Lx-%#010Lx] (%uMB)\n", 404 node, aper_base, aper_base + aper_size - 1, 405 aper_size >> 20); 406 node++; 407 408 if (!aperture_valid(aper_base, aper_size, 64<<20)) { 409 if (valid_agp && agp_aper_base && 410 agp_aper_base == aper_base && 411 agp_aper_order == aper_order) { 412 /* the same between two setting from NB and agp */ 413 if (!no_iommu && 414 max_pfn > MAX_DMA32_PFN && 415 !printed_gart_size_msg) { 416 pr_err("you are using iommu with agp, but GART size is less than 64MB\n"); 417 pr_err("please increase GART size in your BIOS setup\n"); 418 pr_err("if BIOS doesn't have that option, contact your HW vendor!\n"); 419 printed_gart_size_msg = 1; 420 } 421 } else { 422 fix = 1; 423 goto out; 424 } 425 } 426 427 if ((last_aper_order && aper_order != last_aper_order) || 428 (last_aper_base && aper_base != last_aper_base)) { 429 fix = 1; 430 goto out; 431 } 432 last_aper_order = aper_order; 433 last_aper_base = aper_base; 434 } 435 } 436 437 out: 438 if (!fix && !fallback_aper_force) { 439 if (last_aper_base) 440 return 1; 441 return 0; 442 } 443 444 if (!fallback_aper_force) { 445 aper_alloc = agp_aper_base; 446 aper_order = agp_aper_order; 447 } 448 449 if (aper_alloc) { 450 /* Got the aperture from the AGP bridge */ 451 } else if ((!no_iommu && max_pfn > MAX_DMA32_PFN) || 452 force_iommu || 453 valid_agp || 454 fallback_aper_force) { 455 pr_info("Your BIOS doesn't leave a aperture memory hole\n"); 456 pr_info("Please enable the IOMMU option in the BIOS setup\n"); 457 pr_info("This costs you %dMB of RAM\n", 458 32 << fallback_aper_order); 459 460 aper_order = fallback_aper_order; 461 aper_alloc = allocate_aperture(); 462 if (!aper_alloc) { 463 /* 464 * Could disable AGP and IOMMU here, but it's 465 * probably not worth it. But the later users 466 * cannot deal with bad apertures and turning 467 * on the aperture over memory causes very 468 * strange problems, so it's better to panic 469 * early. 470 */ 471 panic("Not enough memory for aperture"); 472 } 473 } else { 474 return 0; 475 } 476 477 /* Fix up the north bridges */ 478 for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) { 479 int bus, dev_base, dev_limit; 480 481 /* 482 * Don't enable translation yet but enable GART IO and CPU 483 * accesses and set DISTLBWALKPRB since GART table memory is UC. 484 */ 485 u32 ctl = aper_order << 1; 486 487 bus = amd_nb_bus_dev_ranges[i].bus; 488 dev_base = amd_nb_bus_dev_ranges[i].dev_base; 489 dev_limit = amd_nb_bus_dev_ranges[i].dev_limit; 490 for (slot = dev_base; slot < dev_limit; slot++) { 491 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00))) 492 continue; 493 494 write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl); 495 write_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE, aper_alloc >> 25); 496 } 497 } 498 499 set_up_gart_resume(aper_order, aper_alloc); 500 501 return 1; 502 } 503