1 // SPDX-License-Identifier: GPL-2.0-only 2 #define pr_fmt(fmt) "SMP alternatives: " fmt 3 4 #include <linux/module.h> 5 #include <linux/sched.h> 6 #include <linux/perf_event.h> 7 #include <linux/mutex.h> 8 #include <linux/list.h> 9 #include <linux/stringify.h> 10 #include <linux/highmem.h> 11 #include <linux/mm.h> 12 #include <linux/vmalloc.h> 13 #include <linux/memory.h> 14 #include <linux/stop_machine.h> 15 #include <linux/slab.h> 16 #include <linux/kdebug.h> 17 #include <linux/kprobes.h> 18 #include <linux/mmu_context.h> 19 #include <linux/bsearch.h> 20 #include <linux/sync_core.h> 21 #include <asm/text-patching.h> 22 #include <asm/alternative.h> 23 #include <asm/sections.h> 24 #include <asm/mce.h> 25 #include <asm/nmi.h> 26 #include <asm/cacheflush.h> 27 #include <asm/tlbflush.h> 28 #include <asm/insn.h> 29 #include <asm/io.h> 30 #include <asm/fixmap.h> 31 #include <asm/paravirt.h> 32 #include <asm/asm-prototypes.h> 33 34 int __read_mostly alternatives_patched; 35 36 EXPORT_SYMBOL_GPL(alternatives_patched); 37 38 #define MAX_PATCH_LEN (255-1) 39 40 #define DA_ALL (~0) 41 #define DA_ALT 0x01 42 #define DA_RET 0x02 43 #define DA_RETPOLINE 0x04 44 #define DA_ENDBR 0x08 45 #define DA_SMP 0x10 46 47 static unsigned int __initdata_or_module debug_alternative; 48 49 static int __init debug_alt(char *str) 50 { 51 if (str && *str == '=') 52 str++; 53 54 if (!str || kstrtouint(str, 0, &debug_alternative)) 55 debug_alternative = DA_ALL; 56 57 return 1; 58 } 59 __setup("debug-alternative", debug_alt); 60 61 static int noreplace_smp; 62 63 static int __init setup_noreplace_smp(char *str) 64 { 65 noreplace_smp = 1; 66 return 1; 67 } 68 __setup("noreplace-smp", setup_noreplace_smp); 69 70 #define DPRINTK(type, fmt, args...) \ 71 do { \ 72 if (debug_alternative & DA_##type) \ 73 printk(KERN_DEBUG pr_fmt(fmt) "\n", ##args); \ 74 } while (0) 75 76 #define DUMP_BYTES(type, buf, len, fmt, args...) \ 77 do { \ 78 if (unlikely(debug_alternative & DA_##type)) { \ 79 int j; \ 80 \ 81 if (!(len)) \ 82 break; \ 83 \ 84 printk(KERN_DEBUG pr_fmt(fmt), ##args); \ 85 for (j = 0; j < (len) - 1; j++) \ 86 printk(KERN_CONT "%02hhx ", buf[j]); \ 87 printk(KERN_CONT "%02hhx\n", buf[j]); \ 88 } \ 89 } while (0) 90 91 static const unsigned char x86nops[] = 92 { 93 BYTES_NOP1, 94 BYTES_NOP2, 95 BYTES_NOP3, 96 BYTES_NOP4, 97 BYTES_NOP5, 98 BYTES_NOP6, 99 BYTES_NOP7, 100 BYTES_NOP8, 101 #ifdef CONFIG_64BIT 102 BYTES_NOP9, 103 BYTES_NOP10, 104 BYTES_NOP11, 105 #endif 106 }; 107 108 const unsigned char * const x86_nops[ASM_NOP_MAX+1] = 109 { 110 NULL, 111 x86nops, 112 x86nops + 1, 113 x86nops + 1 + 2, 114 x86nops + 1 + 2 + 3, 115 x86nops + 1 + 2 + 3 + 4, 116 x86nops + 1 + 2 + 3 + 4 + 5, 117 x86nops + 1 + 2 + 3 + 4 + 5 + 6, 118 x86nops + 1 + 2 + 3 + 4 + 5 + 6 + 7, 119 #ifdef CONFIG_64BIT 120 x86nops + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8, 121 x86nops + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9, 122 x86nops + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10, 123 #endif 124 }; 125 126 /* 127 * Fill the buffer with a single effective instruction of size @len. 128 * 129 * In order not to issue an ORC stack depth tracking CFI entry (Call Frame Info) 130 * for every single-byte NOP, try to generate the maximally available NOP of 131 * size <= ASM_NOP_MAX such that only a single CFI entry is generated (vs one for 132 * each single-byte NOPs). If @len to fill out is > ASM_NOP_MAX, pad with INT3 and 133 * *jump* over instead of executing long and daft NOPs. 134 */ 135 static void __init_or_module add_nop(u8 *instr, unsigned int len) 136 { 137 u8 *target = instr + len; 138 139 if (!len) 140 return; 141 142 if (len <= ASM_NOP_MAX) { 143 memcpy(instr, x86_nops[len], len); 144 return; 145 } 146 147 if (len < 128) { 148 __text_gen_insn(instr, JMP8_INSN_OPCODE, instr, target, JMP8_INSN_SIZE); 149 instr += JMP8_INSN_SIZE; 150 } else { 151 __text_gen_insn(instr, JMP32_INSN_OPCODE, instr, target, JMP32_INSN_SIZE); 152 instr += JMP32_INSN_SIZE; 153 } 154 155 for (;instr < target; instr++) 156 *instr = INT3_INSN_OPCODE; 157 } 158 159 extern s32 __retpoline_sites[], __retpoline_sites_end[]; 160 extern s32 __return_sites[], __return_sites_end[]; 161 extern s32 __cfi_sites[], __cfi_sites_end[]; 162 extern s32 __ibt_endbr_seal[], __ibt_endbr_seal_end[]; 163 extern struct alt_instr __alt_instructions[], __alt_instructions_end[]; 164 extern s32 __smp_locks[], __smp_locks_end[]; 165 void text_poke_early(void *addr, const void *opcode, size_t len); 166 167 /* 168 * Matches NOP and NOPL, not any of the other possible NOPs. 169 */ 170 static bool insn_is_nop(struct insn *insn) 171 { 172 /* Anything NOP, but no REP NOP */ 173 if (insn->opcode.bytes[0] == 0x90 && 174 (!insn->prefixes.nbytes || insn->prefixes.bytes[0] != 0xF3)) 175 return true; 176 177 /* NOPL */ 178 if (insn->opcode.bytes[0] == 0x0F && insn->opcode.bytes[1] == 0x1F) 179 return true; 180 181 /* TODO: more nops */ 182 183 return false; 184 } 185 186 /* 187 * Find the offset of the first non-NOP instruction starting at @offset 188 * but no further than @len. 189 */ 190 static int skip_nops(u8 *instr, int offset, int len) 191 { 192 struct insn insn; 193 194 for (; offset < len; offset += insn.length) { 195 if (insn_decode_kernel(&insn, &instr[offset])) 196 break; 197 198 if (!insn_is_nop(&insn)) 199 break; 200 } 201 202 return offset; 203 } 204 205 /* 206 * Optimize a sequence of NOPs, possibly preceded by an unconditional jump 207 * to the end of the NOP sequence into a single NOP. 208 */ 209 static bool __init_or_module 210 __optimize_nops(u8 *instr, size_t len, struct insn *insn, int *next, int *prev, int *target) 211 { 212 int i = *next - insn->length; 213 214 switch (insn->opcode.bytes[0]) { 215 case JMP8_INSN_OPCODE: 216 case JMP32_INSN_OPCODE: 217 *prev = i; 218 *target = *next + insn->immediate.value; 219 return false; 220 } 221 222 if (insn_is_nop(insn)) { 223 int nop = i; 224 225 *next = skip_nops(instr, *next, len); 226 if (*target && *next == *target) 227 nop = *prev; 228 229 add_nop(instr + nop, *next - nop); 230 DUMP_BYTES(ALT, instr, len, "%px: [%d:%d) optimized NOPs: ", instr, nop, *next); 231 return true; 232 } 233 234 *target = 0; 235 return false; 236 } 237 238 /* 239 * "noinline" to cause control flow change and thus invalidate I$ and 240 * cause refetch after modification. 241 */ 242 static void __init_or_module noinline optimize_nops(u8 *instr, size_t len) 243 { 244 int prev, target = 0; 245 246 for (int next, i = 0; i < len; i = next) { 247 struct insn insn; 248 249 if (insn_decode_kernel(&insn, &instr[i])) 250 return; 251 252 next = i + insn.length; 253 254 __optimize_nops(instr, len, &insn, &next, &prev, &target); 255 } 256 } 257 258 /* 259 * In this context, "source" is where the instructions are placed in the 260 * section .altinstr_replacement, for example during kernel build by the 261 * toolchain. 262 * "Destination" is where the instructions are being patched in by this 263 * machinery. 264 * 265 * The source offset is: 266 * 267 * src_imm = target - src_next_ip (1) 268 * 269 * and the target offset is: 270 * 271 * dst_imm = target - dst_next_ip (2) 272 * 273 * so rework (1) as an expression for target like: 274 * 275 * target = src_imm + src_next_ip (1a) 276 * 277 * and substitute in (2) to get: 278 * 279 * dst_imm = (src_imm + src_next_ip) - dst_next_ip (3) 280 * 281 * Now, since the instruction stream is 'identical' at src and dst (it 282 * is being copied after all) it can be stated that: 283 * 284 * src_next_ip = src + ip_offset 285 * dst_next_ip = dst + ip_offset (4) 286 * 287 * Substitute (4) in (3) and observe ip_offset being cancelled out to 288 * obtain: 289 * 290 * dst_imm = src_imm + (src + ip_offset) - (dst + ip_offset) 291 * = src_imm + src - dst + ip_offset - ip_offset 292 * = src_imm + src - dst (5) 293 * 294 * IOW, only the relative displacement of the code block matters. 295 */ 296 297 #define apply_reloc_n(n_, p_, d_) \ 298 do { \ 299 s32 v = *(s##n_ *)(p_); \ 300 v += (d_); \ 301 BUG_ON((v >> 31) != (v >> (n_-1))); \ 302 *(s##n_ *)(p_) = (s##n_)v; \ 303 } while (0) 304 305 306 static __always_inline 307 void apply_reloc(int n, void *ptr, uintptr_t diff) 308 { 309 switch (n) { 310 case 1: apply_reloc_n(8, ptr, diff); break; 311 case 2: apply_reloc_n(16, ptr, diff); break; 312 case 4: apply_reloc_n(32, ptr, diff); break; 313 default: BUG(); 314 } 315 } 316 317 static __always_inline 318 bool need_reloc(unsigned long offset, u8 *src, size_t src_len) 319 { 320 u8 *target = src + offset; 321 /* 322 * If the target is inside the patched block, it's relative to the 323 * block itself and does not need relocation. 324 */ 325 return (target < src || target > src + src_len); 326 } 327 328 static void __init_or_module noinline 329 apply_relocation(u8 *buf, size_t len, u8 *dest, u8 *src, size_t src_len) 330 { 331 int prev, target = 0; 332 333 for (int next, i = 0; i < len; i = next) { 334 struct insn insn; 335 336 if (WARN_ON_ONCE(insn_decode_kernel(&insn, &buf[i]))) 337 return; 338 339 next = i + insn.length; 340 341 if (__optimize_nops(buf, len, &insn, &next, &prev, &target)) 342 continue; 343 344 switch (insn.opcode.bytes[0]) { 345 case 0x0f: 346 if (insn.opcode.bytes[1] < 0x80 || 347 insn.opcode.bytes[1] > 0x8f) 348 break; 349 350 fallthrough; /* Jcc.d32 */ 351 case 0x70 ... 0x7f: /* Jcc.d8 */ 352 case JMP8_INSN_OPCODE: 353 case JMP32_INSN_OPCODE: 354 case CALL_INSN_OPCODE: 355 if (need_reloc(next + insn.immediate.value, src, src_len)) { 356 apply_reloc(insn.immediate.nbytes, 357 buf + i + insn_offset_immediate(&insn), 358 src - dest); 359 } 360 361 /* 362 * Where possible, convert JMP.d32 into JMP.d8. 363 */ 364 if (insn.opcode.bytes[0] == JMP32_INSN_OPCODE) { 365 s32 imm = insn.immediate.value; 366 imm += src - dest; 367 imm += JMP32_INSN_SIZE - JMP8_INSN_SIZE; 368 if ((imm >> 31) == (imm >> 7)) { 369 buf[i+0] = JMP8_INSN_OPCODE; 370 buf[i+1] = (s8)imm; 371 372 memset(&buf[i+2], INT3_INSN_OPCODE, insn.length - 2); 373 } 374 } 375 break; 376 } 377 378 if (insn_rip_relative(&insn)) { 379 if (need_reloc(next + insn.displacement.value, src, src_len)) { 380 apply_reloc(insn.displacement.nbytes, 381 buf + i + insn_offset_displacement(&insn), 382 src - dest); 383 } 384 } 385 } 386 } 387 388 /* 389 * Replace instructions with better alternatives for this CPU type. This runs 390 * before SMP is initialized to avoid SMP problems with self modifying code. 391 * This implies that asymmetric systems where APs have less capabilities than 392 * the boot processor are not handled. Tough. Make sure you disable such 393 * features by hand. 394 * 395 * Marked "noinline" to cause control flow change and thus insn cache 396 * to refetch changed I$ lines. 397 */ 398 void __init_or_module noinline apply_alternatives(struct alt_instr *start, 399 struct alt_instr *end) 400 { 401 struct alt_instr *a; 402 u8 *instr, *replacement; 403 u8 insn_buff[MAX_PATCH_LEN]; 404 405 DPRINTK(ALT, "alt table %px, -> %px", start, end); 406 /* 407 * The scan order should be from start to end. A later scanned 408 * alternative code can overwrite previously scanned alternative code. 409 * Some kernel functions (e.g. memcpy, memset, etc) use this order to 410 * patch code. 411 * 412 * So be careful if you want to change the scan order to any other 413 * order. 414 */ 415 for (a = start; a < end; a++) { 416 int insn_buff_sz = 0; 417 418 instr = (u8 *)&a->instr_offset + a->instr_offset; 419 replacement = (u8 *)&a->repl_offset + a->repl_offset; 420 BUG_ON(a->instrlen > sizeof(insn_buff)); 421 BUG_ON(a->cpuid >= (NCAPINTS + NBUGINTS) * 32); 422 423 /* 424 * Patch if either: 425 * - feature is present 426 * - feature not present but ALT_FLAG_NOT is set to mean, 427 * patch if feature is *NOT* present. 428 */ 429 if (!boot_cpu_has(a->cpuid) == !(a->flags & ALT_FLAG_NOT)) { 430 optimize_nops(instr, a->instrlen); 431 continue; 432 } 433 434 DPRINTK(ALT, "feat: %s%d*32+%d, old: (%pS (%px) len: %d), repl: (%px, len: %d)", 435 (a->flags & ALT_FLAG_NOT) ? "!" : "", 436 a->cpuid >> 5, 437 a->cpuid & 0x1f, 438 instr, instr, a->instrlen, 439 replacement, a->replacementlen); 440 441 memcpy(insn_buff, replacement, a->replacementlen); 442 insn_buff_sz = a->replacementlen; 443 444 for (; insn_buff_sz < a->instrlen; insn_buff_sz++) 445 insn_buff[insn_buff_sz] = 0x90; 446 447 apply_relocation(insn_buff, a->instrlen, instr, replacement, a->replacementlen); 448 449 DUMP_BYTES(ALT, instr, a->instrlen, "%px: old_insn: ", instr); 450 DUMP_BYTES(ALT, replacement, a->replacementlen, "%px: rpl_insn: ", replacement); 451 DUMP_BYTES(ALT, insn_buff, insn_buff_sz, "%px: final_insn: ", instr); 452 453 text_poke_early(instr, insn_buff, insn_buff_sz); 454 } 455 } 456 457 static inline bool is_jcc32(struct insn *insn) 458 { 459 /* Jcc.d32 second opcode byte is in the range: 0x80-0x8f */ 460 return insn->opcode.bytes[0] == 0x0f && (insn->opcode.bytes[1] & 0xf0) == 0x80; 461 } 462 463 #if defined(CONFIG_RETPOLINE) && defined(CONFIG_OBJTOOL) 464 465 /* 466 * CALL/JMP *%\reg 467 */ 468 static int emit_indirect(int op, int reg, u8 *bytes) 469 { 470 int i = 0; 471 u8 modrm; 472 473 switch (op) { 474 case CALL_INSN_OPCODE: 475 modrm = 0x10; /* Reg = 2; CALL r/m */ 476 break; 477 478 case JMP32_INSN_OPCODE: 479 modrm = 0x20; /* Reg = 4; JMP r/m */ 480 break; 481 482 default: 483 WARN_ON_ONCE(1); 484 return -1; 485 } 486 487 if (reg >= 8) { 488 bytes[i++] = 0x41; /* REX.B prefix */ 489 reg -= 8; 490 } 491 492 modrm |= 0xc0; /* Mod = 3 */ 493 modrm += reg; 494 495 bytes[i++] = 0xff; /* opcode */ 496 bytes[i++] = modrm; 497 498 return i; 499 } 500 501 static int emit_call_track_retpoline(void *addr, struct insn *insn, int reg, u8 *bytes) 502 { 503 u8 op = insn->opcode.bytes[0]; 504 int i = 0; 505 506 /* 507 * Clang does 'weird' Jcc __x86_indirect_thunk_r11 conditional 508 * tail-calls. Deal with them. 509 */ 510 if (is_jcc32(insn)) { 511 bytes[i++] = op; 512 op = insn->opcode.bytes[1]; 513 goto clang_jcc; 514 } 515 516 if (insn->length == 6) 517 bytes[i++] = 0x2e; /* CS-prefix */ 518 519 switch (op) { 520 case CALL_INSN_OPCODE: 521 __text_gen_insn(bytes+i, op, addr+i, 522 __x86_indirect_call_thunk_array[reg], 523 CALL_INSN_SIZE); 524 i += CALL_INSN_SIZE; 525 break; 526 527 case JMP32_INSN_OPCODE: 528 clang_jcc: 529 __text_gen_insn(bytes+i, op, addr+i, 530 __x86_indirect_jump_thunk_array[reg], 531 JMP32_INSN_SIZE); 532 i += JMP32_INSN_SIZE; 533 break; 534 535 default: 536 WARN(1, "%pS %px %*ph\n", addr, addr, 6, addr); 537 return -1; 538 } 539 540 WARN_ON_ONCE(i != insn->length); 541 542 return i; 543 } 544 545 /* 546 * Rewrite the compiler generated retpoline thunk calls. 547 * 548 * For spectre_v2=off (!X86_FEATURE_RETPOLINE), rewrite them into immediate 549 * indirect instructions, avoiding the extra indirection. 550 * 551 * For example, convert: 552 * 553 * CALL __x86_indirect_thunk_\reg 554 * 555 * into: 556 * 557 * CALL *%\reg 558 * 559 * It also tries to inline spectre_v2=retpoline,lfence when size permits. 560 */ 561 static int patch_retpoline(void *addr, struct insn *insn, u8 *bytes) 562 { 563 retpoline_thunk_t *target; 564 int reg, ret, i = 0; 565 u8 op, cc; 566 567 target = addr + insn->length + insn->immediate.value; 568 reg = target - __x86_indirect_thunk_array; 569 570 if (WARN_ON_ONCE(reg & ~0xf)) 571 return -1; 572 573 /* If anyone ever does: CALL/JMP *%rsp, we're in deep trouble. */ 574 BUG_ON(reg == 4); 575 576 if (cpu_feature_enabled(X86_FEATURE_RETPOLINE) && 577 !cpu_feature_enabled(X86_FEATURE_RETPOLINE_LFENCE)) { 578 if (cpu_feature_enabled(X86_FEATURE_CALL_DEPTH)) 579 return emit_call_track_retpoline(addr, insn, reg, bytes); 580 581 return -1; 582 } 583 584 op = insn->opcode.bytes[0]; 585 586 /* 587 * Convert: 588 * 589 * Jcc.d32 __x86_indirect_thunk_\reg 590 * 591 * into: 592 * 593 * Jncc.d8 1f 594 * [ LFENCE ] 595 * JMP *%\reg 596 * [ NOP ] 597 * 1: 598 */ 599 if (is_jcc32(insn)) { 600 cc = insn->opcode.bytes[1] & 0xf; 601 cc ^= 1; /* invert condition */ 602 603 bytes[i++] = 0x70 + cc; /* Jcc.d8 */ 604 bytes[i++] = insn->length - 2; /* sizeof(Jcc.d8) == 2 */ 605 606 /* Continue as if: JMP.d32 __x86_indirect_thunk_\reg */ 607 op = JMP32_INSN_OPCODE; 608 } 609 610 /* 611 * For RETPOLINE_LFENCE: prepend the indirect CALL/JMP with an LFENCE. 612 */ 613 if (cpu_feature_enabled(X86_FEATURE_RETPOLINE_LFENCE)) { 614 bytes[i++] = 0x0f; 615 bytes[i++] = 0xae; 616 bytes[i++] = 0xe8; /* LFENCE */ 617 } 618 619 ret = emit_indirect(op, reg, bytes + i); 620 if (ret < 0) 621 return ret; 622 i += ret; 623 624 /* 625 * The compiler is supposed to EMIT an INT3 after every unconditional 626 * JMP instruction due to AMD BTC. However, if the compiler is too old 627 * or SLS isn't enabled, we still need an INT3 after indirect JMPs 628 * even on Intel. 629 */ 630 if (op == JMP32_INSN_OPCODE && i < insn->length) 631 bytes[i++] = INT3_INSN_OPCODE; 632 633 for (; i < insn->length;) 634 bytes[i++] = BYTES_NOP1; 635 636 return i; 637 } 638 639 /* 640 * Generated by 'objtool --retpoline'. 641 */ 642 void __init_or_module noinline apply_retpolines(s32 *start, s32 *end) 643 { 644 s32 *s; 645 646 for (s = start; s < end; s++) { 647 void *addr = (void *)s + *s; 648 struct insn insn; 649 int len, ret; 650 u8 bytes[16]; 651 u8 op1, op2; 652 653 ret = insn_decode_kernel(&insn, addr); 654 if (WARN_ON_ONCE(ret < 0)) 655 continue; 656 657 op1 = insn.opcode.bytes[0]; 658 op2 = insn.opcode.bytes[1]; 659 660 switch (op1) { 661 case CALL_INSN_OPCODE: 662 case JMP32_INSN_OPCODE: 663 break; 664 665 case 0x0f: /* escape */ 666 if (op2 >= 0x80 && op2 <= 0x8f) 667 break; 668 fallthrough; 669 default: 670 WARN_ON_ONCE(1); 671 continue; 672 } 673 674 DPRINTK(RETPOLINE, "retpoline at: %pS (%px) len: %d to: %pS", 675 addr, addr, insn.length, 676 addr + insn.length + insn.immediate.value); 677 678 len = patch_retpoline(addr, &insn, bytes); 679 if (len == insn.length) { 680 optimize_nops(bytes, len); 681 DUMP_BYTES(RETPOLINE, ((u8*)addr), len, "%px: orig: ", addr); 682 DUMP_BYTES(RETPOLINE, ((u8*)bytes), len, "%px: repl: ", addr); 683 text_poke_early(addr, bytes, len); 684 } 685 } 686 } 687 688 #ifdef CONFIG_RETHUNK 689 690 /* 691 * Rewrite the compiler generated return thunk tail-calls. 692 * 693 * For example, convert: 694 * 695 * JMP __x86_return_thunk 696 * 697 * into: 698 * 699 * RET 700 */ 701 static int patch_return(void *addr, struct insn *insn, u8 *bytes) 702 { 703 int i = 0; 704 705 /* Patch the custom return thunks... */ 706 if (cpu_feature_enabled(X86_FEATURE_RETHUNK)) { 707 i = JMP32_INSN_SIZE; 708 __text_gen_insn(bytes, JMP32_INSN_OPCODE, addr, x86_return_thunk, i); 709 } else { 710 /* ... or patch them out if not needed. */ 711 bytes[i++] = RET_INSN_OPCODE; 712 } 713 714 for (; i < insn->length;) 715 bytes[i++] = INT3_INSN_OPCODE; 716 return i; 717 } 718 719 void __init_or_module noinline apply_returns(s32 *start, s32 *end) 720 { 721 s32 *s; 722 723 /* 724 * Do not patch out the default return thunks if those needed are the 725 * ones generated by the compiler. 726 */ 727 if (cpu_feature_enabled(X86_FEATURE_RETHUNK) && 728 (x86_return_thunk == __x86_return_thunk)) 729 return; 730 731 for (s = start; s < end; s++) { 732 void *dest = NULL, *addr = (void *)s + *s; 733 struct insn insn; 734 int len, ret; 735 u8 bytes[16]; 736 u8 op; 737 738 ret = insn_decode_kernel(&insn, addr); 739 if (WARN_ON_ONCE(ret < 0)) 740 continue; 741 742 op = insn.opcode.bytes[0]; 743 if (op == JMP32_INSN_OPCODE) 744 dest = addr + insn.length + insn.immediate.value; 745 746 if (__static_call_fixup(addr, op, dest) || 747 WARN_ONCE(dest != &__x86_return_thunk, 748 "missing return thunk: %pS-%pS: %*ph", 749 addr, dest, 5, addr)) 750 continue; 751 752 DPRINTK(RET, "return thunk at: %pS (%px) len: %d to: %pS", 753 addr, addr, insn.length, 754 addr + insn.length + insn.immediate.value); 755 756 len = patch_return(addr, &insn, bytes); 757 if (len == insn.length) { 758 DUMP_BYTES(RET, ((u8*)addr), len, "%px: orig: ", addr); 759 DUMP_BYTES(RET, ((u8*)bytes), len, "%px: repl: ", addr); 760 text_poke_early(addr, bytes, len); 761 } 762 } 763 } 764 #else 765 void __init_or_module noinline apply_returns(s32 *start, s32 *end) { } 766 #endif /* CONFIG_RETHUNK */ 767 768 #else /* !CONFIG_RETPOLINE || !CONFIG_OBJTOOL */ 769 770 void __init_or_module noinline apply_retpolines(s32 *start, s32 *end) { } 771 void __init_or_module noinline apply_returns(s32 *start, s32 *end) { } 772 773 #endif /* CONFIG_RETPOLINE && CONFIG_OBJTOOL */ 774 775 #ifdef CONFIG_X86_KERNEL_IBT 776 777 static void poison_cfi(void *addr); 778 779 static void __init_or_module poison_endbr(void *addr, bool warn) 780 { 781 u32 endbr, poison = gen_endbr_poison(); 782 783 if (WARN_ON_ONCE(get_kernel_nofault(endbr, addr))) 784 return; 785 786 if (!is_endbr(endbr)) { 787 WARN_ON_ONCE(warn); 788 return; 789 } 790 791 DPRINTK(ENDBR, "ENDBR at: %pS (%px)", addr, addr); 792 793 /* 794 * When we have IBT, the lack of ENDBR will trigger #CP 795 */ 796 DUMP_BYTES(ENDBR, ((u8*)addr), 4, "%px: orig: ", addr); 797 DUMP_BYTES(ENDBR, ((u8*)&poison), 4, "%px: repl: ", addr); 798 text_poke_early(addr, &poison, 4); 799 } 800 801 /* 802 * Generated by: objtool --ibt 803 * 804 * Seal the functions for indirect calls by clobbering the ENDBR instructions 805 * and the kCFI hash value. 806 */ 807 void __init_or_module noinline apply_seal_endbr(s32 *start, s32 *end) 808 { 809 s32 *s; 810 811 for (s = start; s < end; s++) { 812 void *addr = (void *)s + *s; 813 814 poison_endbr(addr, true); 815 if (IS_ENABLED(CONFIG_FINEIBT)) 816 poison_cfi(addr - 16); 817 } 818 } 819 820 #else 821 822 void __init_or_module apply_seal_endbr(s32 *start, s32 *end) { } 823 824 #endif /* CONFIG_X86_KERNEL_IBT */ 825 826 #ifdef CONFIG_FINEIBT 827 828 enum cfi_mode { 829 CFI_DEFAULT, 830 CFI_OFF, 831 CFI_KCFI, 832 CFI_FINEIBT, 833 }; 834 835 static enum cfi_mode cfi_mode __ro_after_init = CFI_DEFAULT; 836 static bool cfi_rand __ro_after_init = true; 837 static u32 cfi_seed __ro_after_init; 838 839 /* 840 * Re-hash the CFI hash with a boot-time seed while making sure the result is 841 * not a valid ENDBR instruction. 842 */ 843 static u32 cfi_rehash(u32 hash) 844 { 845 hash ^= cfi_seed; 846 while (unlikely(is_endbr(hash) || is_endbr(-hash))) { 847 bool lsb = hash & 1; 848 hash >>= 1; 849 if (lsb) 850 hash ^= 0x80200003; 851 } 852 return hash; 853 } 854 855 static __init int cfi_parse_cmdline(char *str) 856 { 857 if (!str) 858 return -EINVAL; 859 860 while (str) { 861 char *next = strchr(str, ','); 862 if (next) { 863 *next = 0; 864 next++; 865 } 866 867 if (!strcmp(str, "auto")) { 868 cfi_mode = CFI_DEFAULT; 869 } else if (!strcmp(str, "off")) { 870 cfi_mode = CFI_OFF; 871 cfi_rand = false; 872 } else if (!strcmp(str, "kcfi")) { 873 cfi_mode = CFI_KCFI; 874 } else if (!strcmp(str, "fineibt")) { 875 cfi_mode = CFI_FINEIBT; 876 } else if (!strcmp(str, "norand")) { 877 cfi_rand = false; 878 } else { 879 pr_err("Ignoring unknown cfi option (%s).", str); 880 } 881 882 str = next; 883 } 884 885 return 0; 886 } 887 early_param("cfi", cfi_parse_cmdline); 888 889 /* 890 * kCFI FineIBT 891 * 892 * __cfi_\func: __cfi_\func: 893 * movl $0x12345678,%eax // 5 endbr64 // 4 894 * nop subl $0x12345678,%r10d // 7 895 * nop jz 1f // 2 896 * nop ud2 // 2 897 * nop 1: nop // 1 898 * nop 899 * nop 900 * nop 901 * nop 902 * nop 903 * nop 904 * nop 905 * 906 * 907 * caller: caller: 908 * movl $(-0x12345678),%r10d // 6 movl $0x12345678,%r10d // 6 909 * addl $-15(%r11),%r10d // 4 sub $16,%r11 // 4 910 * je 1f // 2 nop4 // 4 911 * ud2 // 2 912 * 1: call __x86_indirect_thunk_r11 // 5 call *%r11; nop2; // 5 913 * 914 */ 915 916 asm( ".pushsection .rodata \n" 917 "fineibt_preamble_start: \n" 918 " endbr64 \n" 919 " subl $0x12345678, %r10d \n" 920 " je fineibt_preamble_end \n" 921 " ud2 \n" 922 " nop \n" 923 "fineibt_preamble_end: \n" 924 ".popsection\n" 925 ); 926 927 extern u8 fineibt_preamble_start[]; 928 extern u8 fineibt_preamble_end[]; 929 930 #define fineibt_preamble_size (fineibt_preamble_end - fineibt_preamble_start) 931 #define fineibt_preamble_hash 7 932 933 asm( ".pushsection .rodata \n" 934 "fineibt_caller_start: \n" 935 " movl $0x12345678, %r10d \n" 936 " sub $16, %r11 \n" 937 ASM_NOP4 938 "fineibt_caller_end: \n" 939 ".popsection \n" 940 ); 941 942 extern u8 fineibt_caller_start[]; 943 extern u8 fineibt_caller_end[]; 944 945 #define fineibt_caller_size (fineibt_caller_end - fineibt_caller_start) 946 #define fineibt_caller_hash 2 947 948 #define fineibt_caller_jmp (fineibt_caller_size - 2) 949 950 static u32 decode_preamble_hash(void *addr) 951 { 952 u8 *p = addr; 953 954 /* b8 78 56 34 12 mov $0x12345678,%eax */ 955 if (p[0] == 0xb8) 956 return *(u32 *)(addr + 1); 957 958 return 0; /* invalid hash value */ 959 } 960 961 static u32 decode_caller_hash(void *addr) 962 { 963 u8 *p = addr; 964 965 /* 41 ba 78 56 34 12 mov $0x12345678,%r10d */ 966 if (p[0] == 0x41 && p[1] == 0xba) 967 return -*(u32 *)(addr + 2); 968 969 /* e8 0c 78 56 34 12 jmp.d8 +12 */ 970 if (p[0] == JMP8_INSN_OPCODE && p[1] == fineibt_caller_jmp) 971 return -*(u32 *)(addr + 2); 972 973 return 0; /* invalid hash value */ 974 } 975 976 /* .retpoline_sites */ 977 static int cfi_disable_callers(s32 *start, s32 *end) 978 { 979 /* 980 * Disable kCFI by patching in a JMP.d8, this leaves the hash immediate 981 * in tact for later usage. Also see decode_caller_hash() and 982 * cfi_rewrite_callers(). 983 */ 984 const u8 jmp[] = { JMP8_INSN_OPCODE, fineibt_caller_jmp }; 985 s32 *s; 986 987 for (s = start; s < end; s++) { 988 void *addr = (void *)s + *s; 989 u32 hash; 990 991 addr -= fineibt_caller_size; 992 hash = decode_caller_hash(addr); 993 if (!hash) /* nocfi callers */ 994 continue; 995 996 text_poke_early(addr, jmp, 2); 997 } 998 999 return 0; 1000 } 1001 1002 static int cfi_enable_callers(s32 *start, s32 *end) 1003 { 1004 /* 1005 * Re-enable kCFI, undo what cfi_disable_callers() did. 1006 */ 1007 const u8 mov[] = { 0x41, 0xba }; 1008 s32 *s; 1009 1010 for (s = start; s < end; s++) { 1011 void *addr = (void *)s + *s; 1012 u32 hash; 1013 1014 addr -= fineibt_caller_size; 1015 hash = decode_caller_hash(addr); 1016 if (!hash) /* nocfi callers */ 1017 continue; 1018 1019 text_poke_early(addr, mov, 2); 1020 } 1021 1022 return 0; 1023 } 1024 1025 /* .cfi_sites */ 1026 static int cfi_rand_preamble(s32 *start, s32 *end) 1027 { 1028 s32 *s; 1029 1030 for (s = start; s < end; s++) { 1031 void *addr = (void *)s + *s; 1032 u32 hash; 1033 1034 hash = decode_preamble_hash(addr); 1035 if (WARN(!hash, "no CFI hash found at: %pS %px %*ph\n", 1036 addr, addr, 5, addr)) 1037 return -EINVAL; 1038 1039 hash = cfi_rehash(hash); 1040 text_poke_early(addr + 1, &hash, 4); 1041 } 1042 1043 return 0; 1044 } 1045 1046 static int cfi_rewrite_preamble(s32 *start, s32 *end) 1047 { 1048 s32 *s; 1049 1050 for (s = start; s < end; s++) { 1051 void *addr = (void *)s + *s; 1052 u32 hash; 1053 1054 hash = decode_preamble_hash(addr); 1055 if (WARN(!hash, "no CFI hash found at: %pS %px %*ph\n", 1056 addr, addr, 5, addr)) 1057 return -EINVAL; 1058 1059 text_poke_early(addr, fineibt_preamble_start, fineibt_preamble_size); 1060 WARN_ON(*(u32 *)(addr + fineibt_preamble_hash) != 0x12345678); 1061 text_poke_early(addr + fineibt_preamble_hash, &hash, 4); 1062 } 1063 1064 return 0; 1065 } 1066 1067 static void cfi_rewrite_endbr(s32 *start, s32 *end) 1068 { 1069 s32 *s; 1070 1071 for (s = start; s < end; s++) { 1072 void *addr = (void *)s + *s; 1073 1074 poison_endbr(addr+16, false); 1075 } 1076 } 1077 1078 /* .retpoline_sites */ 1079 static int cfi_rand_callers(s32 *start, s32 *end) 1080 { 1081 s32 *s; 1082 1083 for (s = start; s < end; s++) { 1084 void *addr = (void *)s + *s; 1085 u32 hash; 1086 1087 addr -= fineibt_caller_size; 1088 hash = decode_caller_hash(addr); 1089 if (hash) { 1090 hash = -cfi_rehash(hash); 1091 text_poke_early(addr + 2, &hash, 4); 1092 } 1093 } 1094 1095 return 0; 1096 } 1097 1098 static int cfi_rewrite_callers(s32 *start, s32 *end) 1099 { 1100 s32 *s; 1101 1102 for (s = start; s < end; s++) { 1103 void *addr = (void *)s + *s; 1104 u32 hash; 1105 1106 addr -= fineibt_caller_size; 1107 hash = decode_caller_hash(addr); 1108 if (hash) { 1109 text_poke_early(addr, fineibt_caller_start, fineibt_caller_size); 1110 WARN_ON(*(u32 *)(addr + fineibt_caller_hash) != 0x12345678); 1111 text_poke_early(addr + fineibt_caller_hash, &hash, 4); 1112 } 1113 /* rely on apply_retpolines() */ 1114 } 1115 1116 return 0; 1117 } 1118 1119 static void __apply_fineibt(s32 *start_retpoline, s32 *end_retpoline, 1120 s32 *start_cfi, s32 *end_cfi, bool builtin) 1121 { 1122 int ret; 1123 1124 if (WARN_ONCE(fineibt_preamble_size != 16, 1125 "FineIBT preamble wrong size: %ld", fineibt_preamble_size)) 1126 return; 1127 1128 if (cfi_mode == CFI_DEFAULT) { 1129 cfi_mode = CFI_KCFI; 1130 if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT)) 1131 cfi_mode = CFI_FINEIBT; 1132 } 1133 1134 /* 1135 * Rewrite the callers to not use the __cfi_ stubs, such that we might 1136 * rewrite them. This disables all CFI. If this succeeds but any of the 1137 * later stages fails, we're without CFI. 1138 */ 1139 ret = cfi_disable_callers(start_retpoline, end_retpoline); 1140 if (ret) 1141 goto err; 1142 1143 if (cfi_rand) { 1144 if (builtin) 1145 cfi_seed = get_random_u32(); 1146 1147 ret = cfi_rand_preamble(start_cfi, end_cfi); 1148 if (ret) 1149 goto err; 1150 1151 ret = cfi_rand_callers(start_retpoline, end_retpoline); 1152 if (ret) 1153 goto err; 1154 } 1155 1156 switch (cfi_mode) { 1157 case CFI_OFF: 1158 if (builtin) 1159 pr_info("Disabling CFI\n"); 1160 return; 1161 1162 case CFI_KCFI: 1163 ret = cfi_enable_callers(start_retpoline, end_retpoline); 1164 if (ret) 1165 goto err; 1166 1167 if (builtin) 1168 pr_info("Using kCFI\n"); 1169 return; 1170 1171 case CFI_FINEIBT: 1172 /* place the FineIBT preamble at func()-16 */ 1173 ret = cfi_rewrite_preamble(start_cfi, end_cfi); 1174 if (ret) 1175 goto err; 1176 1177 /* rewrite the callers to target func()-16 */ 1178 ret = cfi_rewrite_callers(start_retpoline, end_retpoline); 1179 if (ret) 1180 goto err; 1181 1182 /* now that nobody targets func()+0, remove ENDBR there */ 1183 cfi_rewrite_endbr(start_cfi, end_cfi); 1184 1185 if (builtin) 1186 pr_info("Using FineIBT CFI\n"); 1187 return; 1188 1189 default: 1190 break; 1191 } 1192 1193 err: 1194 pr_err("Something went horribly wrong trying to rewrite the CFI implementation.\n"); 1195 } 1196 1197 static inline void poison_hash(void *addr) 1198 { 1199 *(u32 *)addr = 0; 1200 } 1201 1202 static void poison_cfi(void *addr) 1203 { 1204 switch (cfi_mode) { 1205 case CFI_FINEIBT: 1206 /* 1207 * __cfi_\func: 1208 * osp nopl (%rax) 1209 * subl $0, %r10d 1210 * jz 1f 1211 * ud2 1212 * 1: nop 1213 */ 1214 poison_endbr(addr, false); 1215 poison_hash(addr + fineibt_preamble_hash); 1216 break; 1217 1218 case CFI_KCFI: 1219 /* 1220 * __cfi_\func: 1221 * movl $0, %eax 1222 * .skip 11, 0x90 1223 */ 1224 poison_hash(addr + 1); 1225 break; 1226 1227 default: 1228 break; 1229 } 1230 } 1231 1232 #else 1233 1234 static void __apply_fineibt(s32 *start_retpoline, s32 *end_retpoline, 1235 s32 *start_cfi, s32 *end_cfi, bool builtin) 1236 { 1237 } 1238 1239 #ifdef CONFIG_X86_KERNEL_IBT 1240 static void poison_cfi(void *addr) { } 1241 #endif 1242 1243 #endif 1244 1245 void apply_fineibt(s32 *start_retpoline, s32 *end_retpoline, 1246 s32 *start_cfi, s32 *end_cfi) 1247 { 1248 return __apply_fineibt(start_retpoline, end_retpoline, 1249 start_cfi, end_cfi, 1250 /* .builtin = */ false); 1251 } 1252 1253 #ifdef CONFIG_SMP 1254 static void alternatives_smp_lock(const s32 *start, const s32 *end, 1255 u8 *text, u8 *text_end) 1256 { 1257 const s32 *poff; 1258 1259 for (poff = start; poff < end; poff++) { 1260 u8 *ptr = (u8 *)poff + *poff; 1261 1262 if (!*poff || ptr < text || ptr >= text_end) 1263 continue; 1264 /* turn DS segment override prefix into lock prefix */ 1265 if (*ptr == 0x3e) 1266 text_poke(ptr, ((unsigned char []){0xf0}), 1); 1267 } 1268 } 1269 1270 static void alternatives_smp_unlock(const s32 *start, const s32 *end, 1271 u8 *text, u8 *text_end) 1272 { 1273 const s32 *poff; 1274 1275 for (poff = start; poff < end; poff++) { 1276 u8 *ptr = (u8 *)poff + *poff; 1277 1278 if (!*poff || ptr < text || ptr >= text_end) 1279 continue; 1280 /* turn lock prefix into DS segment override prefix */ 1281 if (*ptr == 0xf0) 1282 text_poke(ptr, ((unsigned char []){0x3E}), 1); 1283 } 1284 } 1285 1286 struct smp_alt_module { 1287 /* what is this ??? */ 1288 struct module *mod; 1289 char *name; 1290 1291 /* ptrs to lock prefixes */ 1292 const s32 *locks; 1293 const s32 *locks_end; 1294 1295 /* .text segment, needed to avoid patching init code ;) */ 1296 u8 *text; 1297 u8 *text_end; 1298 1299 struct list_head next; 1300 }; 1301 static LIST_HEAD(smp_alt_modules); 1302 static bool uniproc_patched = false; /* protected by text_mutex */ 1303 1304 void __init_or_module alternatives_smp_module_add(struct module *mod, 1305 char *name, 1306 void *locks, void *locks_end, 1307 void *text, void *text_end) 1308 { 1309 struct smp_alt_module *smp; 1310 1311 mutex_lock(&text_mutex); 1312 if (!uniproc_patched) 1313 goto unlock; 1314 1315 if (num_possible_cpus() == 1) 1316 /* Don't bother remembering, we'll never have to undo it. */ 1317 goto smp_unlock; 1318 1319 smp = kzalloc(sizeof(*smp), GFP_KERNEL); 1320 if (NULL == smp) 1321 /* we'll run the (safe but slow) SMP code then ... */ 1322 goto unlock; 1323 1324 smp->mod = mod; 1325 smp->name = name; 1326 smp->locks = locks; 1327 smp->locks_end = locks_end; 1328 smp->text = text; 1329 smp->text_end = text_end; 1330 DPRINTK(SMP, "locks %p -> %p, text %p -> %p, name %s\n", 1331 smp->locks, smp->locks_end, 1332 smp->text, smp->text_end, smp->name); 1333 1334 list_add_tail(&smp->next, &smp_alt_modules); 1335 smp_unlock: 1336 alternatives_smp_unlock(locks, locks_end, text, text_end); 1337 unlock: 1338 mutex_unlock(&text_mutex); 1339 } 1340 1341 void __init_or_module alternatives_smp_module_del(struct module *mod) 1342 { 1343 struct smp_alt_module *item; 1344 1345 mutex_lock(&text_mutex); 1346 list_for_each_entry(item, &smp_alt_modules, next) { 1347 if (mod != item->mod) 1348 continue; 1349 list_del(&item->next); 1350 kfree(item); 1351 break; 1352 } 1353 mutex_unlock(&text_mutex); 1354 } 1355 1356 void alternatives_enable_smp(void) 1357 { 1358 struct smp_alt_module *mod; 1359 1360 /* Why bother if there are no other CPUs? */ 1361 BUG_ON(num_possible_cpus() == 1); 1362 1363 mutex_lock(&text_mutex); 1364 1365 if (uniproc_patched) { 1366 pr_info("switching to SMP code\n"); 1367 BUG_ON(num_online_cpus() != 1); 1368 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_UP); 1369 clear_cpu_cap(&cpu_data(0), X86_FEATURE_UP); 1370 list_for_each_entry(mod, &smp_alt_modules, next) 1371 alternatives_smp_lock(mod->locks, mod->locks_end, 1372 mod->text, mod->text_end); 1373 uniproc_patched = false; 1374 } 1375 mutex_unlock(&text_mutex); 1376 } 1377 1378 /* 1379 * Return 1 if the address range is reserved for SMP-alternatives. 1380 * Must hold text_mutex. 1381 */ 1382 int alternatives_text_reserved(void *start, void *end) 1383 { 1384 struct smp_alt_module *mod; 1385 const s32 *poff; 1386 u8 *text_start = start; 1387 u8 *text_end = end; 1388 1389 lockdep_assert_held(&text_mutex); 1390 1391 list_for_each_entry(mod, &smp_alt_modules, next) { 1392 if (mod->text > text_end || mod->text_end < text_start) 1393 continue; 1394 for (poff = mod->locks; poff < mod->locks_end; poff++) { 1395 const u8 *ptr = (const u8 *)poff + *poff; 1396 1397 if (text_start <= ptr && text_end > ptr) 1398 return 1; 1399 } 1400 } 1401 1402 return 0; 1403 } 1404 #endif /* CONFIG_SMP */ 1405 1406 #ifdef CONFIG_PARAVIRT 1407 1408 /* Use this to add nops to a buffer, then text_poke the whole buffer. */ 1409 static void __init_or_module add_nops(void *insns, unsigned int len) 1410 { 1411 while (len > 0) { 1412 unsigned int noplen = len; 1413 if (noplen > ASM_NOP_MAX) 1414 noplen = ASM_NOP_MAX; 1415 memcpy(insns, x86_nops[noplen], noplen); 1416 insns += noplen; 1417 len -= noplen; 1418 } 1419 } 1420 1421 void __init_or_module apply_paravirt(struct paravirt_patch_site *start, 1422 struct paravirt_patch_site *end) 1423 { 1424 struct paravirt_patch_site *p; 1425 char insn_buff[MAX_PATCH_LEN]; 1426 1427 for (p = start; p < end; p++) { 1428 unsigned int used; 1429 1430 BUG_ON(p->len > MAX_PATCH_LEN); 1431 /* prep the buffer with the original instructions */ 1432 memcpy(insn_buff, p->instr, p->len); 1433 used = paravirt_patch(p->type, insn_buff, (unsigned long)p->instr, p->len); 1434 1435 BUG_ON(used > p->len); 1436 1437 /* Pad the rest with nops */ 1438 add_nops(insn_buff + used, p->len - used); 1439 text_poke_early(p->instr, insn_buff, p->len); 1440 } 1441 } 1442 extern struct paravirt_patch_site __start_parainstructions[], 1443 __stop_parainstructions[]; 1444 #endif /* CONFIG_PARAVIRT */ 1445 1446 /* 1447 * Self-test for the INT3 based CALL emulation code. 1448 * 1449 * This exercises int3_emulate_call() to make sure INT3 pt_regs are set up 1450 * properly and that there is a stack gap between the INT3 frame and the 1451 * previous context. Without this gap doing a virtual PUSH on the interrupted 1452 * stack would corrupt the INT3 IRET frame. 1453 * 1454 * See entry_{32,64}.S for more details. 1455 */ 1456 1457 /* 1458 * We define the int3_magic() function in assembly to control the calling 1459 * convention such that we can 'call' it from assembly. 1460 */ 1461 1462 extern void int3_magic(unsigned int *ptr); /* defined in asm */ 1463 1464 asm ( 1465 " .pushsection .init.text, \"ax\", @progbits\n" 1466 " .type int3_magic, @function\n" 1467 "int3_magic:\n" 1468 ANNOTATE_NOENDBR 1469 " movl $1, (%" _ASM_ARG1 ")\n" 1470 ASM_RET 1471 " .size int3_magic, .-int3_magic\n" 1472 " .popsection\n" 1473 ); 1474 1475 extern void int3_selftest_ip(void); /* defined in asm below */ 1476 1477 static int __init 1478 int3_exception_notify(struct notifier_block *self, unsigned long val, void *data) 1479 { 1480 unsigned long selftest = (unsigned long)&int3_selftest_ip; 1481 struct die_args *args = data; 1482 struct pt_regs *regs = args->regs; 1483 1484 OPTIMIZER_HIDE_VAR(selftest); 1485 1486 if (!regs || user_mode(regs)) 1487 return NOTIFY_DONE; 1488 1489 if (val != DIE_INT3) 1490 return NOTIFY_DONE; 1491 1492 if (regs->ip - INT3_INSN_SIZE != selftest) 1493 return NOTIFY_DONE; 1494 1495 int3_emulate_call(regs, (unsigned long)&int3_magic); 1496 return NOTIFY_STOP; 1497 } 1498 1499 /* Must be noinline to ensure uniqueness of int3_selftest_ip. */ 1500 static noinline void __init int3_selftest(void) 1501 { 1502 static __initdata struct notifier_block int3_exception_nb = { 1503 .notifier_call = int3_exception_notify, 1504 .priority = INT_MAX-1, /* last */ 1505 }; 1506 unsigned int val = 0; 1507 1508 BUG_ON(register_die_notifier(&int3_exception_nb)); 1509 1510 /* 1511 * Basically: int3_magic(&val); but really complicated :-) 1512 * 1513 * INT3 padded with NOP to CALL_INSN_SIZE. The int3_exception_nb 1514 * notifier above will emulate CALL for us. 1515 */ 1516 asm volatile ("int3_selftest_ip:\n\t" 1517 ANNOTATE_NOENDBR 1518 " int3; nop; nop; nop; nop\n\t" 1519 : ASM_CALL_CONSTRAINT 1520 : __ASM_SEL_RAW(a, D) (&val) 1521 : "memory"); 1522 1523 BUG_ON(val != 1); 1524 1525 unregister_die_notifier(&int3_exception_nb); 1526 } 1527 1528 static __initdata int __alt_reloc_selftest_addr; 1529 1530 extern void __init __alt_reloc_selftest(void *arg); 1531 __visible noinline void __init __alt_reloc_selftest(void *arg) 1532 { 1533 WARN_ON(arg != &__alt_reloc_selftest_addr); 1534 } 1535 1536 static noinline void __init alt_reloc_selftest(void) 1537 { 1538 /* 1539 * Tests apply_relocation(). 1540 * 1541 * This has a relative immediate (CALL) in a place other than the first 1542 * instruction and additionally on x86_64 we get a RIP-relative LEA: 1543 * 1544 * lea 0x0(%rip),%rdi # 5d0: R_X86_64_PC32 .init.data+0x5566c 1545 * call +0 # 5d5: R_X86_64_PLT32 __alt_reloc_selftest-0x4 1546 * 1547 * Getting this wrong will either crash and burn or tickle the WARN 1548 * above. 1549 */ 1550 asm_inline volatile ( 1551 ALTERNATIVE("", "lea %[mem], %%" _ASM_ARG1 "; call __alt_reloc_selftest;", X86_FEATURE_ALWAYS) 1552 : /* output */ 1553 : [mem] "m" (__alt_reloc_selftest_addr) 1554 : _ASM_ARG1 1555 ); 1556 } 1557 1558 void __init alternative_instructions(void) 1559 { 1560 int3_selftest(); 1561 1562 /* 1563 * The patching is not fully atomic, so try to avoid local 1564 * interruptions that might execute the to be patched code. 1565 * Other CPUs are not running. 1566 */ 1567 stop_nmi(); 1568 1569 /* 1570 * Don't stop machine check exceptions while patching. 1571 * MCEs only happen when something got corrupted and in this 1572 * case we must do something about the corruption. 1573 * Ignoring it is worse than an unlikely patching race. 1574 * Also machine checks tend to be broadcast and if one CPU 1575 * goes into machine check the others follow quickly, so we don't 1576 * expect a machine check to cause undue problems during to code 1577 * patching. 1578 */ 1579 1580 /* 1581 * Paravirt patching and alternative patching can be combined to 1582 * replace a function call with a short direct code sequence (e.g. 1583 * by setting a constant return value instead of doing that in an 1584 * external function). 1585 * In order to make this work the following sequence is required: 1586 * 1. set (artificial) features depending on used paravirt 1587 * functions which can later influence alternative patching 1588 * 2. apply paravirt patching (generally replacing an indirect 1589 * function call with a direct one) 1590 * 3. apply alternative patching (e.g. replacing a direct function 1591 * call with a custom code sequence) 1592 * Doing paravirt patching after alternative patching would clobber 1593 * the optimization of the custom code with a function call again. 1594 */ 1595 paravirt_set_cap(); 1596 1597 /* 1598 * First patch paravirt functions, such that we overwrite the indirect 1599 * call with the direct call. 1600 */ 1601 apply_paravirt(__parainstructions, __parainstructions_end); 1602 1603 __apply_fineibt(__retpoline_sites, __retpoline_sites_end, 1604 __cfi_sites, __cfi_sites_end, true); 1605 1606 /* 1607 * Rewrite the retpolines, must be done before alternatives since 1608 * those can rewrite the retpoline thunks. 1609 */ 1610 apply_retpolines(__retpoline_sites, __retpoline_sites_end); 1611 apply_returns(__return_sites, __return_sites_end); 1612 1613 /* 1614 * Then patch alternatives, such that those paravirt calls that are in 1615 * alternatives can be overwritten by their immediate fragments. 1616 */ 1617 apply_alternatives(__alt_instructions, __alt_instructions_end); 1618 1619 /* 1620 * Now all calls are established. Apply the call thunks if 1621 * required. 1622 */ 1623 callthunks_patch_builtin_calls(); 1624 1625 /* 1626 * Seal all functions that do not have their address taken. 1627 */ 1628 apply_seal_endbr(__ibt_endbr_seal, __ibt_endbr_seal_end); 1629 1630 #ifdef CONFIG_SMP 1631 /* Patch to UP if other cpus not imminent. */ 1632 if (!noreplace_smp && (num_present_cpus() == 1 || setup_max_cpus <= 1)) { 1633 uniproc_patched = true; 1634 alternatives_smp_module_add(NULL, "core kernel", 1635 __smp_locks, __smp_locks_end, 1636 _text, _etext); 1637 } 1638 1639 if (!uniproc_patched || num_possible_cpus() == 1) { 1640 free_init_pages("SMP alternatives", 1641 (unsigned long)__smp_locks, 1642 (unsigned long)__smp_locks_end); 1643 } 1644 #endif 1645 1646 restart_nmi(); 1647 alternatives_patched = 1; 1648 1649 alt_reloc_selftest(); 1650 } 1651 1652 /** 1653 * text_poke_early - Update instructions on a live kernel at boot time 1654 * @addr: address to modify 1655 * @opcode: source of the copy 1656 * @len: length to copy 1657 * 1658 * When you use this code to patch more than one byte of an instruction 1659 * you need to make sure that other CPUs cannot execute this code in parallel. 1660 * Also no thread must be currently preempted in the middle of these 1661 * instructions. And on the local CPU you need to be protected against NMI or 1662 * MCE handlers seeing an inconsistent instruction while you patch. 1663 */ 1664 void __init_or_module text_poke_early(void *addr, const void *opcode, 1665 size_t len) 1666 { 1667 unsigned long flags; 1668 1669 if (boot_cpu_has(X86_FEATURE_NX) && 1670 is_module_text_address((unsigned long)addr)) { 1671 /* 1672 * Modules text is marked initially as non-executable, so the 1673 * code cannot be running and speculative code-fetches are 1674 * prevented. Just change the code. 1675 */ 1676 memcpy(addr, opcode, len); 1677 } else { 1678 local_irq_save(flags); 1679 memcpy(addr, opcode, len); 1680 local_irq_restore(flags); 1681 sync_core(); 1682 1683 /* 1684 * Could also do a CLFLUSH here to speed up CPU recovery; but 1685 * that causes hangs on some VIA CPUs. 1686 */ 1687 } 1688 } 1689 1690 typedef struct { 1691 struct mm_struct *mm; 1692 } temp_mm_state_t; 1693 1694 /* 1695 * Using a temporary mm allows to set temporary mappings that are not accessible 1696 * by other CPUs. Such mappings are needed to perform sensitive memory writes 1697 * that override the kernel memory protections (e.g., W^X), without exposing the 1698 * temporary page-table mappings that are required for these write operations to 1699 * other CPUs. Using a temporary mm also allows to avoid TLB shootdowns when the 1700 * mapping is torn down. 1701 * 1702 * Context: The temporary mm needs to be used exclusively by a single core. To 1703 * harden security IRQs must be disabled while the temporary mm is 1704 * loaded, thereby preventing interrupt handler bugs from overriding 1705 * the kernel memory protection. 1706 */ 1707 static inline temp_mm_state_t use_temporary_mm(struct mm_struct *mm) 1708 { 1709 temp_mm_state_t temp_state; 1710 1711 lockdep_assert_irqs_disabled(); 1712 1713 /* 1714 * Make sure not to be in TLB lazy mode, as otherwise we'll end up 1715 * with a stale address space WITHOUT being in lazy mode after 1716 * restoring the previous mm. 1717 */ 1718 if (this_cpu_read(cpu_tlbstate_shared.is_lazy)) 1719 leave_mm(smp_processor_id()); 1720 1721 temp_state.mm = this_cpu_read(cpu_tlbstate.loaded_mm); 1722 switch_mm_irqs_off(NULL, mm, current); 1723 1724 /* 1725 * If breakpoints are enabled, disable them while the temporary mm is 1726 * used. Userspace might set up watchpoints on addresses that are used 1727 * in the temporary mm, which would lead to wrong signals being sent or 1728 * crashes. 1729 * 1730 * Note that breakpoints are not disabled selectively, which also causes 1731 * kernel breakpoints (e.g., perf's) to be disabled. This might be 1732 * undesirable, but still seems reasonable as the code that runs in the 1733 * temporary mm should be short. 1734 */ 1735 if (hw_breakpoint_active()) 1736 hw_breakpoint_disable(); 1737 1738 return temp_state; 1739 } 1740 1741 static inline void unuse_temporary_mm(temp_mm_state_t prev_state) 1742 { 1743 lockdep_assert_irqs_disabled(); 1744 switch_mm_irqs_off(NULL, prev_state.mm, current); 1745 1746 /* 1747 * Restore the breakpoints if they were disabled before the temporary mm 1748 * was loaded. 1749 */ 1750 if (hw_breakpoint_active()) 1751 hw_breakpoint_restore(); 1752 } 1753 1754 __ro_after_init struct mm_struct *poking_mm; 1755 __ro_after_init unsigned long poking_addr; 1756 1757 static void text_poke_memcpy(void *dst, const void *src, size_t len) 1758 { 1759 memcpy(dst, src, len); 1760 } 1761 1762 static void text_poke_memset(void *dst, const void *src, size_t len) 1763 { 1764 int c = *(const int *)src; 1765 1766 memset(dst, c, len); 1767 } 1768 1769 typedef void text_poke_f(void *dst, const void *src, size_t len); 1770 1771 static void *__text_poke(text_poke_f func, void *addr, const void *src, size_t len) 1772 { 1773 bool cross_page_boundary = offset_in_page(addr) + len > PAGE_SIZE; 1774 struct page *pages[2] = {NULL}; 1775 temp_mm_state_t prev; 1776 unsigned long flags; 1777 pte_t pte, *ptep; 1778 spinlock_t *ptl; 1779 pgprot_t pgprot; 1780 1781 /* 1782 * While boot memory allocator is running we cannot use struct pages as 1783 * they are not yet initialized. There is no way to recover. 1784 */ 1785 BUG_ON(!after_bootmem); 1786 1787 if (!core_kernel_text((unsigned long)addr)) { 1788 pages[0] = vmalloc_to_page(addr); 1789 if (cross_page_boundary) 1790 pages[1] = vmalloc_to_page(addr + PAGE_SIZE); 1791 } else { 1792 pages[0] = virt_to_page(addr); 1793 WARN_ON(!PageReserved(pages[0])); 1794 if (cross_page_boundary) 1795 pages[1] = virt_to_page(addr + PAGE_SIZE); 1796 } 1797 /* 1798 * If something went wrong, crash and burn since recovery paths are not 1799 * implemented. 1800 */ 1801 BUG_ON(!pages[0] || (cross_page_boundary && !pages[1])); 1802 1803 /* 1804 * Map the page without the global bit, as TLB flushing is done with 1805 * flush_tlb_mm_range(), which is intended for non-global PTEs. 1806 */ 1807 pgprot = __pgprot(pgprot_val(PAGE_KERNEL) & ~_PAGE_GLOBAL); 1808 1809 /* 1810 * The lock is not really needed, but this allows to avoid open-coding. 1811 */ 1812 ptep = get_locked_pte(poking_mm, poking_addr, &ptl); 1813 1814 /* 1815 * This must not fail; preallocated in poking_init(). 1816 */ 1817 VM_BUG_ON(!ptep); 1818 1819 local_irq_save(flags); 1820 1821 pte = mk_pte(pages[0], pgprot); 1822 set_pte_at(poking_mm, poking_addr, ptep, pte); 1823 1824 if (cross_page_boundary) { 1825 pte = mk_pte(pages[1], pgprot); 1826 set_pte_at(poking_mm, poking_addr + PAGE_SIZE, ptep + 1, pte); 1827 } 1828 1829 /* 1830 * Loading the temporary mm behaves as a compiler barrier, which 1831 * guarantees that the PTE will be set at the time memcpy() is done. 1832 */ 1833 prev = use_temporary_mm(poking_mm); 1834 1835 kasan_disable_current(); 1836 func((u8 *)poking_addr + offset_in_page(addr), src, len); 1837 kasan_enable_current(); 1838 1839 /* 1840 * Ensure that the PTE is only cleared after the instructions of memcpy 1841 * were issued by using a compiler barrier. 1842 */ 1843 barrier(); 1844 1845 pte_clear(poking_mm, poking_addr, ptep); 1846 if (cross_page_boundary) 1847 pte_clear(poking_mm, poking_addr + PAGE_SIZE, ptep + 1); 1848 1849 /* 1850 * Loading the previous page-table hierarchy requires a serializing 1851 * instruction that already allows the core to see the updated version. 1852 * Xen-PV is assumed to serialize execution in a similar manner. 1853 */ 1854 unuse_temporary_mm(prev); 1855 1856 /* 1857 * Flushing the TLB might involve IPIs, which would require enabled 1858 * IRQs, but not if the mm is not used, as it is in this point. 1859 */ 1860 flush_tlb_mm_range(poking_mm, poking_addr, poking_addr + 1861 (cross_page_boundary ? 2 : 1) * PAGE_SIZE, 1862 PAGE_SHIFT, false); 1863 1864 if (func == text_poke_memcpy) { 1865 /* 1866 * If the text does not match what we just wrote then something is 1867 * fundamentally screwy; there's nothing we can really do about that. 1868 */ 1869 BUG_ON(memcmp(addr, src, len)); 1870 } 1871 1872 local_irq_restore(flags); 1873 pte_unmap_unlock(ptep, ptl); 1874 return addr; 1875 } 1876 1877 /** 1878 * text_poke - Update instructions on a live kernel 1879 * @addr: address to modify 1880 * @opcode: source of the copy 1881 * @len: length to copy 1882 * 1883 * Only atomic text poke/set should be allowed when not doing early patching. 1884 * It means the size must be writable atomically and the address must be aligned 1885 * in a way that permits an atomic write. It also makes sure we fit on a single 1886 * page. 1887 * 1888 * Note that the caller must ensure that if the modified code is part of a 1889 * module, the module would not be removed during poking. This can be achieved 1890 * by registering a module notifier, and ordering module removal and patching 1891 * trough a mutex. 1892 */ 1893 void *text_poke(void *addr, const void *opcode, size_t len) 1894 { 1895 lockdep_assert_held(&text_mutex); 1896 1897 return __text_poke(text_poke_memcpy, addr, opcode, len); 1898 } 1899 1900 /** 1901 * text_poke_kgdb - Update instructions on a live kernel by kgdb 1902 * @addr: address to modify 1903 * @opcode: source of the copy 1904 * @len: length to copy 1905 * 1906 * Only atomic text poke/set should be allowed when not doing early patching. 1907 * It means the size must be writable atomically and the address must be aligned 1908 * in a way that permits an atomic write. It also makes sure we fit on a single 1909 * page. 1910 * 1911 * Context: should only be used by kgdb, which ensures no other core is running, 1912 * despite the fact it does not hold the text_mutex. 1913 */ 1914 void *text_poke_kgdb(void *addr, const void *opcode, size_t len) 1915 { 1916 return __text_poke(text_poke_memcpy, addr, opcode, len); 1917 } 1918 1919 void *text_poke_copy_locked(void *addr, const void *opcode, size_t len, 1920 bool core_ok) 1921 { 1922 unsigned long start = (unsigned long)addr; 1923 size_t patched = 0; 1924 1925 if (WARN_ON_ONCE(!core_ok && core_kernel_text(start))) 1926 return NULL; 1927 1928 while (patched < len) { 1929 unsigned long ptr = start + patched; 1930 size_t s; 1931 1932 s = min_t(size_t, PAGE_SIZE * 2 - offset_in_page(ptr), len - patched); 1933 1934 __text_poke(text_poke_memcpy, (void *)ptr, opcode + patched, s); 1935 patched += s; 1936 } 1937 return addr; 1938 } 1939 1940 /** 1941 * text_poke_copy - Copy instructions into (an unused part of) RX memory 1942 * @addr: address to modify 1943 * @opcode: source of the copy 1944 * @len: length to copy, could be more than 2x PAGE_SIZE 1945 * 1946 * Not safe against concurrent execution; useful for JITs to dump 1947 * new code blocks into unused regions of RX memory. Can be used in 1948 * conjunction with synchronize_rcu_tasks() to wait for existing 1949 * execution to quiesce after having made sure no existing functions 1950 * pointers are live. 1951 */ 1952 void *text_poke_copy(void *addr, const void *opcode, size_t len) 1953 { 1954 mutex_lock(&text_mutex); 1955 addr = text_poke_copy_locked(addr, opcode, len, false); 1956 mutex_unlock(&text_mutex); 1957 return addr; 1958 } 1959 1960 /** 1961 * text_poke_set - memset into (an unused part of) RX memory 1962 * @addr: address to modify 1963 * @c: the byte to fill the area with 1964 * @len: length to copy, could be more than 2x PAGE_SIZE 1965 * 1966 * This is useful to overwrite unused regions of RX memory with illegal 1967 * instructions. 1968 */ 1969 void *text_poke_set(void *addr, int c, size_t len) 1970 { 1971 unsigned long start = (unsigned long)addr; 1972 size_t patched = 0; 1973 1974 if (WARN_ON_ONCE(core_kernel_text(start))) 1975 return NULL; 1976 1977 mutex_lock(&text_mutex); 1978 while (patched < len) { 1979 unsigned long ptr = start + patched; 1980 size_t s; 1981 1982 s = min_t(size_t, PAGE_SIZE * 2 - offset_in_page(ptr), len - patched); 1983 1984 __text_poke(text_poke_memset, (void *)ptr, (void *)&c, s); 1985 patched += s; 1986 } 1987 mutex_unlock(&text_mutex); 1988 return addr; 1989 } 1990 1991 static void do_sync_core(void *info) 1992 { 1993 sync_core(); 1994 } 1995 1996 void text_poke_sync(void) 1997 { 1998 on_each_cpu(do_sync_core, NULL, 1); 1999 } 2000 2001 /* 2002 * NOTE: crazy scheme to allow patching Jcc.d32 but not increase the size of 2003 * this thing. When len == 6 everything is prefixed with 0x0f and we map 2004 * opcode to Jcc.d8, using len to distinguish. 2005 */ 2006 struct text_poke_loc { 2007 /* addr := _stext + rel_addr */ 2008 s32 rel_addr; 2009 s32 disp; 2010 u8 len; 2011 u8 opcode; 2012 const u8 text[POKE_MAX_OPCODE_SIZE]; 2013 /* see text_poke_bp_batch() */ 2014 u8 old; 2015 }; 2016 2017 struct bp_patching_desc { 2018 struct text_poke_loc *vec; 2019 int nr_entries; 2020 atomic_t refs; 2021 }; 2022 2023 static struct bp_patching_desc bp_desc; 2024 2025 static __always_inline 2026 struct bp_patching_desc *try_get_desc(void) 2027 { 2028 struct bp_patching_desc *desc = &bp_desc; 2029 2030 if (!raw_atomic_inc_not_zero(&desc->refs)) 2031 return NULL; 2032 2033 return desc; 2034 } 2035 2036 static __always_inline void put_desc(void) 2037 { 2038 struct bp_patching_desc *desc = &bp_desc; 2039 2040 smp_mb__before_atomic(); 2041 raw_atomic_dec(&desc->refs); 2042 } 2043 2044 static __always_inline void *text_poke_addr(struct text_poke_loc *tp) 2045 { 2046 return _stext + tp->rel_addr; 2047 } 2048 2049 static __always_inline int patch_cmp(const void *key, const void *elt) 2050 { 2051 struct text_poke_loc *tp = (struct text_poke_loc *) elt; 2052 2053 if (key < text_poke_addr(tp)) 2054 return -1; 2055 if (key > text_poke_addr(tp)) 2056 return 1; 2057 return 0; 2058 } 2059 2060 noinstr int poke_int3_handler(struct pt_regs *regs) 2061 { 2062 struct bp_patching_desc *desc; 2063 struct text_poke_loc *tp; 2064 int ret = 0; 2065 void *ip; 2066 2067 if (user_mode(regs)) 2068 return 0; 2069 2070 /* 2071 * Having observed our INT3 instruction, we now must observe 2072 * bp_desc with non-zero refcount: 2073 * 2074 * bp_desc.refs = 1 INT3 2075 * WMB RMB 2076 * write INT3 if (bp_desc.refs != 0) 2077 */ 2078 smp_rmb(); 2079 2080 desc = try_get_desc(); 2081 if (!desc) 2082 return 0; 2083 2084 /* 2085 * Discount the INT3. See text_poke_bp_batch(). 2086 */ 2087 ip = (void *) regs->ip - INT3_INSN_SIZE; 2088 2089 /* 2090 * Skip the binary search if there is a single member in the vector. 2091 */ 2092 if (unlikely(desc->nr_entries > 1)) { 2093 tp = __inline_bsearch(ip, desc->vec, desc->nr_entries, 2094 sizeof(struct text_poke_loc), 2095 patch_cmp); 2096 if (!tp) 2097 goto out_put; 2098 } else { 2099 tp = desc->vec; 2100 if (text_poke_addr(tp) != ip) 2101 goto out_put; 2102 } 2103 2104 ip += tp->len; 2105 2106 switch (tp->opcode) { 2107 case INT3_INSN_OPCODE: 2108 /* 2109 * Someone poked an explicit INT3, they'll want to handle it, 2110 * do not consume. 2111 */ 2112 goto out_put; 2113 2114 case RET_INSN_OPCODE: 2115 int3_emulate_ret(regs); 2116 break; 2117 2118 case CALL_INSN_OPCODE: 2119 int3_emulate_call(regs, (long)ip + tp->disp); 2120 break; 2121 2122 case JMP32_INSN_OPCODE: 2123 case JMP8_INSN_OPCODE: 2124 int3_emulate_jmp(regs, (long)ip + tp->disp); 2125 break; 2126 2127 case 0x70 ... 0x7f: /* Jcc */ 2128 int3_emulate_jcc(regs, tp->opcode & 0xf, (long)ip, tp->disp); 2129 break; 2130 2131 default: 2132 BUG(); 2133 } 2134 2135 ret = 1; 2136 2137 out_put: 2138 put_desc(); 2139 return ret; 2140 } 2141 2142 #define TP_VEC_MAX (PAGE_SIZE / sizeof(struct text_poke_loc)) 2143 static struct text_poke_loc tp_vec[TP_VEC_MAX]; 2144 static int tp_vec_nr; 2145 2146 /** 2147 * text_poke_bp_batch() -- update instructions on live kernel on SMP 2148 * @tp: vector of instructions to patch 2149 * @nr_entries: number of entries in the vector 2150 * 2151 * Modify multi-byte instruction by using int3 breakpoint on SMP. 2152 * We completely avoid stop_machine() here, and achieve the 2153 * synchronization using int3 breakpoint. 2154 * 2155 * The way it is done: 2156 * - For each entry in the vector: 2157 * - add a int3 trap to the address that will be patched 2158 * - sync cores 2159 * - For each entry in the vector: 2160 * - update all but the first byte of the patched range 2161 * - sync cores 2162 * - For each entry in the vector: 2163 * - replace the first byte (int3) by the first byte of 2164 * replacing opcode 2165 * - sync cores 2166 */ 2167 static void text_poke_bp_batch(struct text_poke_loc *tp, unsigned int nr_entries) 2168 { 2169 unsigned char int3 = INT3_INSN_OPCODE; 2170 unsigned int i; 2171 int do_sync; 2172 2173 lockdep_assert_held(&text_mutex); 2174 2175 bp_desc.vec = tp; 2176 bp_desc.nr_entries = nr_entries; 2177 2178 /* 2179 * Corresponds to the implicit memory barrier in try_get_desc() to 2180 * ensure reading a non-zero refcount provides up to date bp_desc data. 2181 */ 2182 atomic_set_release(&bp_desc.refs, 1); 2183 2184 /* 2185 * Function tracing can enable thousands of places that need to be 2186 * updated. This can take quite some time, and with full kernel debugging 2187 * enabled, this could cause the softlockup watchdog to trigger. 2188 * This function gets called every 256 entries added to be patched. 2189 * Call cond_resched() here to make sure that other tasks can get scheduled 2190 * while processing all the functions being patched. 2191 */ 2192 cond_resched(); 2193 2194 /* 2195 * Corresponding read barrier in int3 notifier for making sure the 2196 * nr_entries and handler are correctly ordered wrt. patching. 2197 */ 2198 smp_wmb(); 2199 2200 /* 2201 * First step: add a int3 trap to the address that will be patched. 2202 */ 2203 for (i = 0; i < nr_entries; i++) { 2204 tp[i].old = *(u8 *)text_poke_addr(&tp[i]); 2205 text_poke(text_poke_addr(&tp[i]), &int3, INT3_INSN_SIZE); 2206 } 2207 2208 text_poke_sync(); 2209 2210 /* 2211 * Second step: update all but the first byte of the patched range. 2212 */ 2213 for (do_sync = 0, i = 0; i < nr_entries; i++) { 2214 u8 old[POKE_MAX_OPCODE_SIZE+1] = { tp[i].old, }; 2215 u8 _new[POKE_MAX_OPCODE_SIZE+1]; 2216 const u8 *new = tp[i].text; 2217 int len = tp[i].len; 2218 2219 if (len - INT3_INSN_SIZE > 0) { 2220 memcpy(old + INT3_INSN_SIZE, 2221 text_poke_addr(&tp[i]) + INT3_INSN_SIZE, 2222 len - INT3_INSN_SIZE); 2223 2224 if (len == 6) { 2225 _new[0] = 0x0f; 2226 memcpy(_new + 1, new, 5); 2227 new = _new; 2228 } 2229 2230 text_poke(text_poke_addr(&tp[i]) + INT3_INSN_SIZE, 2231 new + INT3_INSN_SIZE, 2232 len - INT3_INSN_SIZE); 2233 2234 do_sync++; 2235 } 2236 2237 /* 2238 * Emit a perf event to record the text poke, primarily to 2239 * support Intel PT decoding which must walk the executable code 2240 * to reconstruct the trace. The flow up to here is: 2241 * - write INT3 byte 2242 * - IPI-SYNC 2243 * - write instruction tail 2244 * At this point the actual control flow will be through the 2245 * INT3 and handler and not hit the old or new instruction. 2246 * Intel PT outputs FUP/TIP packets for the INT3, so the flow 2247 * can still be decoded. Subsequently: 2248 * - emit RECORD_TEXT_POKE with the new instruction 2249 * - IPI-SYNC 2250 * - write first byte 2251 * - IPI-SYNC 2252 * So before the text poke event timestamp, the decoder will see 2253 * either the old instruction flow or FUP/TIP of INT3. After the 2254 * text poke event timestamp, the decoder will see either the 2255 * new instruction flow or FUP/TIP of INT3. Thus decoders can 2256 * use the timestamp as the point at which to modify the 2257 * executable code. 2258 * The old instruction is recorded so that the event can be 2259 * processed forwards or backwards. 2260 */ 2261 perf_event_text_poke(text_poke_addr(&tp[i]), old, len, new, len); 2262 } 2263 2264 if (do_sync) { 2265 /* 2266 * According to Intel, this core syncing is very likely 2267 * not necessary and we'd be safe even without it. But 2268 * better safe than sorry (plus there's not only Intel). 2269 */ 2270 text_poke_sync(); 2271 } 2272 2273 /* 2274 * Third step: replace the first byte (int3) by the first byte of 2275 * replacing opcode. 2276 */ 2277 for (do_sync = 0, i = 0; i < nr_entries; i++) { 2278 u8 byte = tp[i].text[0]; 2279 2280 if (tp[i].len == 6) 2281 byte = 0x0f; 2282 2283 if (byte == INT3_INSN_OPCODE) 2284 continue; 2285 2286 text_poke(text_poke_addr(&tp[i]), &byte, INT3_INSN_SIZE); 2287 do_sync++; 2288 } 2289 2290 if (do_sync) 2291 text_poke_sync(); 2292 2293 /* 2294 * Remove and wait for refs to be zero. 2295 */ 2296 if (!atomic_dec_and_test(&bp_desc.refs)) 2297 atomic_cond_read_acquire(&bp_desc.refs, !VAL); 2298 } 2299 2300 static void text_poke_loc_init(struct text_poke_loc *tp, void *addr, 2301 const void *opcode, size_t len, const void *emulate) 2302 { 2303 struct insn insn; 2304 int ret, i = 0; 2305 2306 if (len == 6) 2307 i = 1; 2308 memcpy((void *)tp->text, opcode+i, len-i); 2309 if (!emulate) 2310 emulate = opcode; 2311 2312 ret = insn_decode_kernel(&insn, emulate); 2313 BUG_ON(ret < 0); 2314 2315 tp->rel_addr = addr - (void *)_stext; 2316 tp->len = len; 2317 tp->opcode = insn.opcode.bytes[0]; 2318 2319 if (is_jcc32(&insn)) { 2320 /* 2321 * Map Jcc.d32 onto Jcc.d8 and use len to distinguish. 2322 */ 2323 tp->opcode = insn.opcode.bytes[1] - 0x10; 2324 } 2325 2326 switch (tp->opcode) { 2327 case RET_INSN_OPCODE: 2328 case JMP32_INSN_OPCODE: 2329 case JMP8_INSN_OPCODE: 2330 /* 2331 * Control flow instructions without implied execution of the 2332 * next instruction can be padded with INT3. 2333 */ 2334 for (i = insn.length; i < len; i++) 2335 BUG_ON(tp->text[i] != INT3_INSN_OPCODE); 2336 break; 2337 2338 default: 2339 BUG_ON(len != insn.length); 2340 } 2341 2342 switch (tp->opcode) { 2343 case INT3_INSN_OPCODE: 2344 case RET_INSN_OPCODE: 2345 break; 2346 2347 case CALL_INSN_OPCODE: 2348 case JMP32_INSN_OPCODE: 2349 case JMP8_INSN_OPCODE: 2350 case 0x70 ... 0x7f: /* Jcc */ 2351 tp->disp = insn.immediate.value; 2352 break; 2353 2354 default: /* assume NOP */ 2355 switch (len) { 2356 case 2: /* NOP2 -- emulate as JMP8+0 */ 2357 BUG_ON(memcmp(emulate, x86_nops[len], len)); 2358 tp->opcode = JMP8_INSN_OPCODE; 2359 tp->disp = 0; 2360 break; 2361 2362 case 5: /* NOP5 -- emulate as JMP32+0 */ 2363 BUG_ON(memcmp(emulate, x86_nops[len], len)); 2364 tp->opcode = JMP32_INSN_OPCODE; 2365 tp->disp = 0; 2366 break; 2367 2368 default: /* unknown instruction */ 2369 BUG(); 2370 } 2371 break; 2372 } 2373 } 2374 2375 /* 2376 * We hard rely on the tp_vec being ordered; ensure this is so by flushing 2377 * early if needed. 2378 */ 2379 static bool tp_order_fail(void *addr) 2380 { 2381 struct text_poke_loc *tp; 2382 2383 if (!tp_vec_nr) 2384 return false; 2385 2386 if (!addr) /* force */ 2387 return true; 2388 2389 tp = &tp_vec[tp_vec_nr - 1]; 2390 if ((unsigned long)text_poke_addr(tp) > (unsigned long)addr) 2391 return true; 2392 2393 return false; 2394 } 2395 2396 static void text_poke_flush(void *addr) 2397 { 2398 if (tp_vec_nr == TP_VEC_MAX || tp_order_fail(addr)) { 2399 text_poke_bp_batch(tp_vec, tp_vec_nr); 2400 tp_vec_nr = 0; 2401 } 2402 } 2403 2404 void text_poke_finish(void) 2405 { 2406 text_poke_flush(NULL); 2407 } 2408 2409 void __ref text_poke_queue(void *addr, const void *opcode, size_t len, const void *emulate) 2410 { 2411 struct text_poke_loc *tp; 2412 2413 text_poke_flush(addr); 2414 2415 tp = &tp_vec[tp_vec_nr++]; 2416 text_poke_loc_init(tp, addr, opcode, len, emulate); 2417 } 2418 2419 /** 2420 * text_poke_bp() -- update instructions on live kernel on SMP 2421 * @addr: address to patch 2422 * @opcode: opcode of new instruction 2423 * @len: length to copy 2424 * @emulate: instruction to be emulated 2425 * 2426 * Update a single instruction with the vector in the stack, avoiding 2427 * dynamically allocated memory. This function should be used when it is 2428 * not possible to allocate memory. 2429 */ 2430 void __ref text_poke_bp(void *addr, const void *opcode, size_t len, const void *emulate) 2431 { 2432 struct text_poke_loc tp; 2433 2434 text_poke_loc_init(&tp, addr, opcode, len, emulate); 2435 text_poke_bp_batch(&tp, 1); 2436 } 2437