1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2005 Intel Corporation 4 * Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> 5 * - Added _PDC for SMP C-states on Intel CPUs 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/export.h> 10 #include <linux/init.h> 11 #include <linux/acpi.h> 12 #include <linux/cpu.h> 13 #include <linux/sched.h> 14 15 #include <acpi/processor.h> 16 #include <asm/cpuid.h> 17 #include <asm/mwait.h> 18 #include <asm/special_insns.h> 19 20 /* 21 * Initialize bm_flags based on the CPU cache properties 22 * On SMP it depends on cache configuration 23 * - When cache is not shared among all CPUs, we flush cache 24 * before entering C3. 25 * - When cache is shared among all CPUs, we use bm_check 26 * mechanism as in UP case 27 * 28 * This routine is called only after all the CPUs are online 29 */ 30 void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags, 31 unsigned int cpu) 32 { 33 struct cpuinfo_x86 *c = &cpu_data(cpu); 34 35 flags->bm_check = 0; 36 if (num_online_cpus() == 1) 37 flags->bm_check = 1; 38 else if (c->x86_vendor == X86_VENDOR_INTEL) { 39 /* 40 * Today all MP CPUs that support C3 share cache. 41 * And caches should not be flushed by software while 42 * entering C3 type state. 43 */ 44 flags->bm_check = 1; 45 } 46 47 /* 48 * On all recent Intel platforms, ARB_DISABLE is a nop. 49 * So, set bm_control to zero to indicate that ARB_DISABLE 50 * is not required while entering C3 type state on 51 * P4, Core and beyond CPUs 52 */ 53 if (c->x86_vendor == X86_VENDOR_INTEL && 54 (c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 0x0f))) 55 flags->bm_control = 0; 56 57 if (c->x86_vendor == X86_VENDOR_CENTAUR) { 58 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model == 0x0f && 59 c->x86_stepping >= 0x0e)) { 60 /* 61 * For all recent Centaur CPUs, the ucode will make sure that each 62 * core can keep cache coherence with each other while entering C3 63 * type state. So, set bm_check to 1 to indicate that the kernel 64 * doesn't need to execute a cache flush operation (WBINVD) when 65 * entering C3 type state. 66 */ 67 flags->bm_check = 1; 68 /* 69 * For all recent Centaur platforms, ARB_DISABLE is a nop. 70 * Set bm_control to zero to indicate that ARB_DISABLE is 71 * not required while entering C3 type state. 72 */ 73 flags->bm_control = 0; 74 } 75 } 76 77 if (c->x86_vendor == X86_VENDOR_ZHAOXIN) { 78 /* 79 * All Zhaoxin CPUs that support C3 share cache. 80 * And caches should not be flushed by software while 81 * entering C3 type state. 82 */ 83 flags->bm_check = 1; 84 /* 85 * On all recent Zhaoxin platforms, ARB_DISABLE is a nop. 86 * So, set bm_control to zero to indicate that ARB_DISABLE 87 * is not required while entering C3 type state. 88 */ 89 flags->bm_control = 0; 90 } 91 if (c->x86_vendor == X86_VENDOR_AMD && c->x86 >= 0x17) { 92 /* 93 * For all AMD Zen or newer CPUs that support C3, caches 94 * should not be flushed by software while entering C3 95 * type state. Set bm->check to 1 so that kernel doesn't 96 * need to execute cache flush operation. 97 */ 98 flags->bm_check = 1; 99 /* 100 * In current AMD C state implementation ARB_DIS is no longer 101 * used. So set bm_control to zero to indicate ARB_DIS is not 102 * required while entering C3 type state. 103 */ 104 flags->bm_control = 0; 105 } 106 } 107 EXPORT_SYMBOL(acpi_processor_power_init_bm_check); 108 109 /* The code below handles cstate entry with monitor-mwait pair on Intel*/ 110 111 struct cstate_entry { 112 struct { 113 unsigned int eax; 114 unsigned int ecx; 115 } states[ACPI_PROCESSOR_MAX_POWER]; 116 }; 117 static struct cstate_entry __percpu *cpu_cstate_entry; /* per CPU ptr */ 118 119 static short mwait_supported[ACPI_PROCESSOR_MAX_POWER]; 120 121 #define NATIVE_CSTATE_BEYOND_HALT (2) 122 123 static long acpi_processor_ffh_cstate_probe_cpu(void *_cx) 124 { 125 struct acpi_processor_cx *cx = _cx; 126 long retval; 127 unsigned int eax, ebx, ecx, edx; 128 unsigned int edx_part; 129 unsigned int cstate_type; /* C-state type and not ACPI C-state type */ 130 unsigned int num_cstate_subtype; 131 132 cpuid(CPUID_LEAF_MWAIT, &eax, &ebx, &ecx, &edx); 133 134 /* Check whether this particular cx_type (in CST) is supported or not */ 135 cstate_type = (((cx->address >> MWAIT_SUBSTATE_SIZE) & 136 MWAIT_CSTATE_MASK) + 1) & MWAIT_CSTATE_MASK; 137 edx_part = edx >> (cstate_type * MWAIT_SUBSTATE_SIZE); 138 num_cstate_subtype = edx_part & MWAIT_SUBSTATE_MASK; 139 140 retval = 0; 141 /* If the HW does not support any sub-states in this C-state */ 142 if (num_cstate_subtype == 0) { 143 pr_warn(FW_BUG "ACPI MWAIT C-state 0x%x not supported by HW (0x%x)\n", 144 cx->address, edx_part); 145 retval = -1; 146 goto out; 147 } 148 149 /* mwait ecx extensions INTERRUPT_BREAK should be supported for C2/C3 */ 150 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) || 151 !(ecx & CPUID5_ECX_INTERRUPT_BREAK)) { 152 retval = -1; 153 goto out; 154 } 155 156 if (!mwait_supported[cstate_type]) { 157 mwait_supported[cstate_type] = 1; 158 printk(KERN_DEBUG 159 "Monitor-Mwait will be used to enter C-%d state\n", 160 cx->type); 161 } 162 snprintf(cx->desc, 163 ACPI_CX_DESC_LEN, "ACPI FFH MWAIT 0x%x", 164 cx->address); 165 out: 166 return retval; 167 } 168 169 int acpi_processor_ffh_cstate_probe(unsigned int cpu, 170 struct acpi_processor_cx *cx, struct acpi_power_register *reg) 171 { 172 struct cstate_entry *percpu_entry; 173 struct cpuinfo_x86 *c = &cpu_data(cpu); 174 long retval; 175 176 if (!cpu_cstate_entry || c->cpuid_level < CPUID_LEAF_MWAIT) 177 return -1; 178 179 if (reg->bit_offset != NATIVE_CSTATE_BEYOND_HALT) 180 return -1; 181 182 percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu); 183 percpu_entry->states[cx->index].eax = 0; 184 percpu_entry->states[cx->index].ecx = 0; 185 186 /* Make sure we are running on right CPU */ 187 188 retval = call_on_cpu(cpu, acpi_processor_ffh_cstate_probe_cpu, cx, 189 false); 190 if (retval == 0) { 191 /* Use the hint in CST */ 192 percpu_entry->states[cx->index].eax = cx->address; 193 percpu_entry->states[cx->index].ecx = MWAIT_ECX_INTERRUPT_BREAK; 194 } 195 196 /* 197 * For _CST FFH on Intel, if GAS.access_size bit 1 is cleared, 198 * then we should skip checking BM_STS for this C-state. 199 * ref: "Intel Processor Vendor-Specific ACPI Interface Specification" 200 */ 201 if ((c->x86_vendor == X86_VENDOR_INTEL) && !(reg->access_size & 0x2)) 202 cx->bm_sts_skip = 1; 203 204 return retval; 205 } 206 EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_probe); 207 208 void __cpuidle acpi_processor_ffh_cstate_enter(struct acpi_processor_cx *cx) 209 { 210 unsigned int cpu = smp_processor_id(); 211 struct cstate_entry *percpu_entry; 212 213 percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu); 214 mwait_idle_with_hints(percpu_entry->states[cx->index].eax, 215 percpu_entry->states[cx->index].ecx); 216 } 217 EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_enter); 218 219 static int __init ffh_cstate_init(void) 220 { 221 struct cpuinfo_x86 *c = &boot_cpu_data; 222 223 if (c->x86_vendor != X86_VENDOR_INTEL && 224 c->x86_vendor != X86_VENDOR_AMD && 225 c->x86_vendor != X86_VENDOR_HYGON) 226 return -1; 227 228 cpu_cstate_entry = alloc_percpu(struct cstate_entry); 229 return 0; 230 } 231 232 static void __exit ffh_cstate_exit(void) 233 { 234 free_percpu(cpu_cstate_entry); 235 cpu_cstate_entry = NULL; 236 } 237 238 arch_initcall(ffh_cstate_init); 239 __exitcall(ffh_cstate_exit); 240