123d6f82bSThomas Gleixner /* 223d6f82bSThomas Gleixner * Copyright (C) 2005 Intel Corporation 323d6f82bSThomas Gleixner * Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> 423d6f82bSThomas Gleixner * - Added _PDC for SMP C-states on Intel CPUs 523d6f82bSThomas Gleixner */ 623d6f82bSThomas Gleixner 723d6f82bSThomas Gleixner #include <linux/kernel.h> 823d6f82bSThomas Gleixner #include <linux/module.h> 923d6f82bSThomas Gleixner #include <linux/init.h> 1023d6f82bSThomas Gleixner #include <linux/acpi.h> 1123d6f82bSThomas Gleixner #include <linux/cpu.h> 1223d6f82bSThomas Gleixner #include <linux/sched.h> 1323d6f82bSThomas Gleixner 1423d6f82bSThomas Gleixner #include <acpi/processor.h> 1523d6f82bSThomas Gleixner #include <asm/acpi.h> 1623d6f82bSThomas Gleixner 1723d6f82bSThomas Gleixner /* 1823d6f82bSThomas Gleixner * Initialize bm_flags based on the CPU cache properties 1923d6f82bSThomas Gleixner * On SMP it depends on cache configuration 2023d6f82bSThomas Gleixner * - When cache is not shared among all CPUs, we flush cache 2123d6f82bSThomas Gleixner * before entering C3. 2223d6f82bSThomas Gleixner * - When cache is shared among all CPUs, we use bm_check 2323d6f82bSThomas Gleixner * mechanism as in UP case 2423d6f82bSThomas Gleixner * 2523d6f82bSThomas Gleixner * This routine is called only after all the CPUs are online 2623d6f82bSThomas Gleixner */ 2723d6f82bSThomas Gleixner void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags, 2823d6f82bSThomas Gleixner unsigned int cpu) 2923d6f82bSThomas Gleixner { 3092cb7612SMike Travis struct cpuinfo_x86 *c = &cpu_data(cpu); 3123d6f82bSThomas Gleixner 3223d6f82bSThomas Gleixner flags->bm_check = 0; 3323d6f82bSThomas Gleixner if (num_online_cpus() == 1) 3423d6f82bSThomas Gleixner flags->bm_check = 1; 3523d6f82bSThomas Gleixner else if (c->x86_vendor == X86_VENDOR_INTEL) { 3623d6f82bSThomas Gleixner /* 37ee1ca48fSPallipadi, Venkatesh * Today all MP CPUs that support C3 share cache. 38ee1ca48fSPallipadi, Venkatesh * And caches should not be flushed by software while 39ee1ca48fSPallipadi, Venkatesh * entering C3 type state. 4023d6f82bSThomas Gleixner */ 4123d6f82bSThomas Gleixner flags->bm_check = 1; 4223d6f82bSThomas Gleixner } 43ee1ca48fSPallipadi, Venkatesh 44ee1ca48fSPallipadi, Venkatesh /* 45ee1ca48fSPallipadi, Venkatesh * On all recent Intel platforms, ARB_DISABLE is a nop. 46ee1ca48fSPallipadi, Venkatesh * So, set bm_control to zero to indicate that ARB_DISABLE 47ee1ca48fSPallipadi, Venkatesh * is not required while entering C3 type state on 48ee1ca48fSPallipadi, Venkatesh * P4, Core and beyond CPUs 49ee1ca48fSPallipadi, Venkatesh */ 50ee1ca48fSPallipadi, Venkatesh if (c->x86_vendor == X86_VENDOR_INTEL && 5103a05ed1SZhao Yakui (c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 0x0f))) 52ee1ca48fSPallipadi, Venkatesh flags->bm_control = 0; 5323d6f82bSThomas Gleixner } 5423d6f82bSThomas Gleixner EXPORT_SYMBOL(acpi_processor_power_init_bm_check); 5523d6f82bSThomas Gleixner 5623d6f82bSThomas Gleixner /* The code below handles cstate entry with monitor-mwait pair on Intel*/ 5723d6f82bSThomas Gleixner 5823d6f82bSThomas Gleixner struct cstate_entry { 5923d6f82bSThomas Gleixner struct { 6023d6f82bSThomas Gleixner unsigned int eax; 6123d6f82bSThomas Gleixner unsigned int ecx; 6223d6f82bSThomas Gleixner } states[ACPI_PROCESSOR_MAX_POWER]; 6323d6f82bSThomas Gleixner }; 64*bd126b23SNamhyung Kim static struct cstate_entry __percpu *cpu_cstate_entry; /* per CPU ptr */ 6523d6f82bSThomas Gleixner 6623d6f82bSThomas Gleixner static short mwait_supported[ACPI_PROCESSOR_MAX_POWER]; 6723d6f82bSThomas Gleixner 6823d6f82bSThomas Gleixner #define MWAIT_SUBSTATE_MASK (0xf) 6913b40a1aSZhao Yakui #define MWAIT_CSTATE_MASK (0xf) 7023d6f82bSThomas Gleixner #define MWAIT_SUBSTATE_SIZE (4) 7123d6f82bSThomas Gleixner 7223d6f82bSThomas Gleixner #define CPUID_MWAIT_LEAF (5) 7323d6f82bSThomas Gleixner #define CPUID5_ECX_EXTENSIONS_SUPPORTED (0x1) 7423d6f82bSThomas Gleixner #define CPUID5_ECX_INTERRUPT_BREAK (0x2) 7523d6f82bSThomas Gleixner 7623d6f82bSThomas Gleixner #define MWAIT_ECX_INTERRUPT_BREAK (0x1) 7723d6f82bSThomas Gleixner 7823d6f82bSThomas Gleixner #define NATIVE_CSTATE_BEYOND_HALT (2) 7923d6f82bSThomas Gleixner 80c74f31c0SMike Travis static long acpi_processor_ffh_cstate_probe_cpu(void *_cx) 8123d6f82bSThomas Gleixner { 82c74f31c0SMike Travis struct acpi_processor_cx *cx = _cx; 83c74f31c0SMike Travis long retval; 8423d6f82bSThomas Gleixner unsigned int eax, ebx, ecx, edx; 8523d6f82bSThomas Gleixner unsigned int edx_part; 8623d6f82bSThomas Gleixner unsigned int cstate_type; /* C-state type and not ACPI C-state type */ 8723d6f82bSThomas Gleixner unsigned int num_cstate_subtype; 8823d6f82bSThomas Gleixner 8923d6f82bSThomas Gleixner cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx); 9023d6f82bSThomas Gleixner 9123d6f82bSThomas Gleixner /* Check whether this particular cx_type (in CST) is supported or not */ 9213b40a1aSZhao Yakui cstate_type = ((cx->address >> MWAIT_SUBSTATE_SIZE) & 9313b40a1aSZhao Yakui MWAIT_CSTATE_MASK) + 1; 9423d6f82bSThomas Gleixner edx_part = edx >> (cstate_type * MWAIT_SUBSTATE_SIZE); 9523d6f82bSThomas Gleixner num_cstate_subtype = edx_part & MWAIT_SUBSTATE_MASK; 9623d6f82bSThomas Gleixner 9723d6f82bSThomas Gleixner retval = 0; 9823d6f82bSThomas Gleixner if (num_cstate_subtype < (cx->address & MWAIT_SUBSTATE_MASK)) { 9923d6f82bSThomas Gleixner retval = -1; 10023d6f82bSThomas Gleixner goto out; 10123d6f82bSThomas Gleixner } 10223d6f82bSThomas Gleixner 10323d6f82bSThomas Gleixner /* mwait ecx extensions INTERRUPT_BREAK should be supported for C2/C3 */ 10423d6f82bSThomas Gleixner if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) || 10523d6f82bSThomas Gleixner !(ecx & CPUID5_ECX_INTERRUPT_BREAK)) { 10623d6f82bSThomas Gleixner retval = -1; 10723d6f82bSThomas Gleixner goto out; 10823d6f82bSThomas Gleixner } 10923d6f82bSThomas Gleixner 11023d6f82bSThomas Gleixner if (!mwait_supported[cstate_type]) { 11123d6f82bSThomas Gleixner mwait_supported[cstate_type] = 1; 112c74f31c0SMike Travis printk(KERN_DEBUG 113c74f31c0SMike Travis "Monitor-Mwait will be used to enter C-%d " 11423d6f82bSThomas Gleixner "state\n", cx->type); 11523d6f82bSThomas Gleixner } 116c74f31c0SMike Travis snprintf(cx->desc, 117c74f31c0SMike Travis ACPI_CX_DESC_LEN, "ACPI FFH INTEL MWAIT 0x%x", 1184fcb2fcdSVenkatesh Pallipadi cx->address); 11923d6f82bSThomas Gleixner out: 120c74f31c0SMike Travis return retval; 121c74f31c0SMike Travis } 122c74f31c0SMike Travis 123c74f31c0SMike Travis int acpi_processor_ffh_cstate_probe(unsigned int cpu, 124c74f31c0SMike Travis struct acpi_processor_cx *cx, struct acpi_power_register *reg) 125c74f31c0SMike Travis { 126c74f31c0SMike Travis struct cstate_entry *percpu_entry; 127c74f31c0SMike Travis struct cpuinfo_x86 *c = &cpu_data(cpu); 128c74f31c0SMike Travis long retval; 129c74f31c0SMike Travis 130c74f31c0SMike Travis if (!cpu_cstate_entry || c->cpuid_level < CPUID_MWAIT_LEAF) 131c74f31c0SMike Travis return -1; 132c74f31c0SMike Travis 133c74f31c0SMike Travis if (reg->bit_offset != NATIVE_CSTATE_BEYOND_HALT) 134c74f31c0SMike Travis return -1; 135c74f31c0SMike Travis 136c74f31c0SMike Travis percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu); 137c74f31c0SMike Travis percpu_entry->states[cx->index].eax = 0; 138c74f31c0SMike Travis percpu_entry->states[cx->index].ecx = 0; 139c74f31c0SMike Travis 140c74f31c0SMike Travis /* Make sure we are running on right CPU */ 141c74f31c0SMike Travis 142c74f31c0SMike Travis retval = work_on_cpu(cpu, acpi_processor_ffh_cstate_probe_cpu, cx); 143c74f31c0SMike Travis if (retval == 0) { 144c74f31c0SMike Travis /* Use the hint in CST */ 145c74f31c0SMike Travis percpu_entry->states[cx->index].eax = cx->address; 146c74f31c0SMike Travis percpu_entry->states[cx->index].ecx = MWAIT_ECX_INTERRUPT_BREAK; 147c74f31c0SMike Travis } 148718be4aaSLen Brown 149718be4aaSLen Brown /* 150718be4aaSLen Brown * For _CST FFH on Intel, if GAS.access_size bit 1 is cleared, 151718be4aaSLen Brown * then we should skip checking BM_STS for this C-state. 152718be4aaSLen Brown * ref: "Intel Processor Vendor-Specific ACPI Interface Specification" 153718be4aaSLen Brown */ 154718be4aaSLen Brown if ((c->x86_vendor == X86_VENDOR_INTEL) && !(reg->access_size & 0x2)) 155718be4aaSLen Brown cx->bm_sts_skip = 1; 156718be4aaSLen Brown 15723d6f82bSThomas Gleixner return retval; 15823d6f82bSThomas Gleixner } 15923d6f82bSThomas Gleixner EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_probe); 16023d6f82bSThomas Gleixner 16123d6f82bSThomas Gleixner void acpi_processor_ffh_cstate_enter(struct acpi_processor_cx *cx) 16223d6f82bSThomas Gleixner { 16323d6f82bSThomas Gleixner unsigned int cpu = smp_processor_id(); 16423d6f82bSThomas Gleixner struct cstate_entry *percpu_entry; 16523d6f82bSThomas Gleixner 16623d6f82bSThomas Gleixner percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu); 16723d6f82bSThomas Gleixner mwait_idle_with_hints(percpu_entry->states[cx->index].eax, 16823d6f82bSThomas Gleixner percpu_entry->states[cx->index].ecx); 16923d6f82bSThomas Gleixner } 17023d6f82bSThomas Gleixner EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_enter); 17123d6f82bSThomas Gleixner 17223d6f82bSThomas Gleixner static int __init ffh_cstate_init(void) 17323d6f82bSThomas Gleixner { 17423d6f82bSThomas Gleixner struct cpuinfo_x86 *c = &boot_cpu_data; 17523d6f82bSThomas Gleixner if (c->x86_vendor != X86_VENDOR_INTEL) 17623d6f82bSThomas Gleixner return -1; 17723d6f82bSThomas Gleixner 17823d6f82bSThomas Gleixner cpu_cstate_entry = alloc_percpu(struct cstate_entry); 17923d6f82bSThomas Gleixner return 0; 18023d6f82bSThomas Gleixner } 18123d6f82bSThomas Gleixner 18223d6f82bSThomas Gleixner static void __exit ffh_cstate_exit(void) 18323d6f82bSThomas Gleixner { 18423d6f82bSThomas Gleixner free_percpu(cpu_cstate_entry); 18523d6f82bSThomas Gleixner cpu_cstate_entry = NULL; 18623d6f82bSThomas Gleixner } 18723d6f82bSThomas Gleixner 18823d6f82bSThomas Gleixner arch_initcall(ffh_cstate_init); 18923d6f82bSThomas Gleixner __exitcall(ffh_cstate_exit); 190