1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 3 #ifndef _UAPI_ASM_X86_AMD_HSMP_H_ 4 #define _UAPI_ASM_X86_AMD_HSMP_H_ 5 6 #include <linux/types.h> 7 8 #pragma pack(4) 9 10 #define HSMP_MAX_MSG_LEN 8 11 12 /* 13 * HSMP Messages supported 14 */ 15 enum hsmp_message_ids { 16 HSMP_TEST = 1, /* 01h Increments input value by 1 */ 17 HSMP_GET_SMU_VER, /* 02h SMU FW version */ 18 HSMP_GET_PROTO_VER, /* 03h HSMP interface version */ 19 HSMP_GET_SOCKET_POWER, /* 04h average package power consumption */ 20 HSMP_SET_SOCKET_POWER_LIMIT, /* 05h Set the socket power limit */ 21 HSMP_GET_SOCKET_POWER_LIMIT, /* 06h Get current socket power limit */ 22 HSMP_GET_SOCKET_POWER_LIMIT_MAX,/* 07h Get maximum socket power value */ 23 HSMP_SET_BOOST_LIMIT, /* 08h Set a core maximum frequency limit */ 24 HSMP_SET_BOOST_LIMIT_SOCKET, /* 09h Set socket maximum frequency level */ 25 HSMP_GET_BOOST_LIMIT, /* 0Ah Get current frequency limit */ 26 HSMP_GET_PROC_HOT, /* 0Bh Get PROCHOT status */ 27 HSMP_SET_XGMI_LINK_WIDTH, /* 0Ch Set max and min width of xGMI Link */ 28 HSMP_SET_DF_PSTATE, /* 0Dh Alter APEnable/Disable messages behavior */ 29 HSMP_SET_AUTO_DF_PSTATE, /* 0Eh Enable DF P-State Performance Boost algorithm */ 30 HSMP_GET_FCLK_MCLK, /* 0Fh Get FCLK and MEMCLK for current socket */ 31 HSMP_GET_CCLK_THROTTLE_LIMIT, /* 10h Get CCLK frequency limit in socket */ 32 HSMP_GET_C0_PERCENT, /* 11h Get average C0 residency in socket */ 33 HSMP_SET_NBIO_DPM_LEVEL, /* 12h Set max/min LCLK DPM Level for a given NBIO */ 34 HSMP_GET_NBIO_DPM_LEVEL, /* 13h Get LCLK DPM level min and max for a given NBIO */ 35 HSMP_GET_DDR_BANDWIDTH, /* 14h Get theoretical maximum and current DDR Bandwidth */ 36 HSMP_GET_TEMP_MONITOR, /* 15h Get socket temperature */ 37 HSMP_GET_DIMM_TEMP_RANGE, /* 16h Get per-DIMM temperature range and refresh rate */ 38 HSMP_GET_DIMM_POWER, /* 17h Get per-DIMM power consumption */ 39 HSMP_GET_DIMM_THERMAL, /* 18h Get per-DIMM thermal sensors */ 40 HSMP_GET_SOCKET_FREQ_LIMIT, /* 19h Get current active frequency per socket */ 41 HSMP_GET_CCLK_CORE_LIMIT, /* 1Ah Get CCLK frequency limit per core */ 42 HSMP_GET_RAILS_SVI, /* 1Bh Get SVI-based Telemetry for all rails */ 43 HSMP_GET_SOCKET_FMAX_FMIN, /* 1Ch Get Fmax and Fmin per socket */ 44 HSMP_GET_IOLINK_BANDWITH, /* 1Dh Get current bandwidth on IO Link */ 45 HSMP_GET_XGMI_BANDWITH, /* 1Eh Get current bandwidth on xGMI Link */ 46 HSMP_SET_GMI3_WIDTH, /* 1Fh Set max and min GMI3 Link width */ 47 HSMP_SET_PCI_RATE, /* 20h Control link rate on PCIe devices */ 48 HSMP_SET_POWER_MODE, /* 21h Select power efficiency profile policy */ 49 HSMP_SET_PSTATE_MAX_MIN, /* 22h Set the max and min DF P-State */ 50 HSMP_GET_METRIC_TABLE_VER, /* 23h Get metrics table version */ 51 HSMP_GET_METRIC_TABLE, /* 24h Get metrics table */ 52 HSMP_GET_METRIC_TABLE_DRAM_ADDR,/* 25h Get metrics table dram address */ 53 HSMP_MSG_ID_MAX, 54 }; 55 56 struct hsmp_message { 57 __u32 msg_id; /* Message ID */ 58 __u16 num_args; /* Number of input argument words in message */ 59 __u16 response_sz; /* Number of expected output/response words */ 60 __u32 args[HSMP_MAX_MSG_LEN]; /* argument/response buffer */ 61 __u16 sock_ind; /* socket number */ 62 }; 63 64 enum hsmp_msg_type { 65 HSMP_RSVD = -1, 66 HSMP_SET = 0, 67 HSMP_GET = 1, 68 }; 69 70 enum hsmp_proto_versions { 71 HSMP_PROTO_VER2 = 2, 72 HSMP_PROTO_VER3, 73 HSMP_PROTO_VER4, 74 HSMP_PROTO_VER5, 75 HSMP_PROTO_VER6 76 }; 77 78 struct hsmp_msg_desc { 79 int num_args; 80 int response_sz; 81 enum hsmp_msg_type type; 82 }; 83 84 /* 85 * User may use these comments as reference, please find the 86 * supported list of messages and message definition in the 87 * HSMP chapter of respective family/model PPR. 88 * 89 * Not supported messages would return -ENOMSG. 90 */ 91 static const struct hsmp_msg_desc hsmp_msg_desc_table[] 92 __attribute__((unused)) = { 93 /* RESERVED */ 94 {0, 0, HSMP_RSVD}, 95 96 /* 97 * HSMP_TEST, num_args = 1, response_sz = 1 98 * input: args[0] = xx 99 * output: args[0] = xx + 1 100 */ 101 {1, 1, HSMP_GET}, 102 103 /* 104 * HSMP_GET_SMU_VER, num_args = 0, response_sz = 1 105 * output: args[0] = smu fw ver 106 */ 107 {0, 1, HSMP_GET}, 108 109 /* 110 * HSMP_GET_PROTO_VER, num_args = 0, response_sz = 1 111 * output: args[0] = proto version 112 */ 113 {0, 1, HSMP_GET}, 114 115 /* 116 * HSMP_GET_SOCKET_POWER, num_args = 0, response_sz = 1 117 * output: args[0] = socket power in mWatts 118 */ 119 {0, 1, HSMP_GET}, 120 121 /* 122 * HSMP_SET_SOCKET_POWER_LIMIT, num_args = 1, response_sz = 0 123 * input: args[0] = power limit value in mWatts 124 */ 125 {1, 0, HSMP_SET}, 126 127 /* 128 * HSMP_GET_SOCKET_POWER_LIMIT, num_args = 0, response_sz = 1 129 * output: args[0] = socket power limit value in mWatts 130 */ 131 {0, 1, HSMP_GET}, 132 133 /* 134 * HSMP_GET_SOCKET_POWER_LIMIT_MAX, num_args = 0, response_sz = 1 135 * output: args[0] = maximuam socket power limit in mWatts 136 */ 137 {0, 1, HSMP_GET}, 138 139 /* 140 * HSMP_SET_BOOST_LIMIT, num_args = 1, response_sz = 0 141 * input: args[0] = apic id[31:16] + boost limit value in MHz[15:0] 142 */ 143 {1, 0, HSMP_SET}, 144 145 /* 146 * HSMP_SET_BOOST_LIMIT_SOCKET, num_args = 1, response_sz = 0 147 * input: args[0] = boost limit value in MHz 148 */ 149 {1, 0, HSMP_SET}, 150 151 /* 152 * HSMP_GET_BOOST_LIMIT, num_args = 1, response_sz = 1 153 * input: args[0] = apic id 154 * output: args[0] = boost limit value in MHz 155 */ 156 {1, 1, HSMP_GET}, 157 158 /* 159 * HSMP_GET_PROC_HOT, num_args = 0, response_sz = 1 160 * output: args[0] = proc hot status 161 */ 162 {0, 1, HSMP_GET}, 163 164 /* 165 * HSMP_SET_XGMI_LINK_WIDTH, num_args = 1, response_sz = 0 166 * input: args[0] = min link width[15:8] + max link width[7:0] 167 */ 168 {1, 0, HSMP_SET}, 169 170 /* 171 * HSMP_SET_DF_PSTATE, num_args = 1, response_sz = 0 172 * input: args[0] = df pstate[7:0] 173 */ 174 {1, 0, HSMP_SET}, 175 176 /* HSMP_SET_AUTO_DF_PSTATE, num_args = 0, response_sz = 0 */ 177 {0, 0, HSMP_SET}, 178 179 /* 180 * HSMP_GET_FCLK_MCLK, num_args = 0, response_sz = 2 181 * output: args[0] = fclk in MHz, args[1] = mclk in MHz 182 */ 183 {0, 2, HSMP_GET}, 184 185 /* 186 * HSMP_GET_CCLK_THROTTLE_LIMIT, num_args = 0, response_sz = 1 187 * output: args[0] = core clock in MHz 188 */ 189 {0, 1, HSMP_GET}, 190 191 /* 192 * HSMP_GET_C0_PERCENT, num_args = 0, response_sz = 1 193 * output: args[0] = average c0 residency 194 */ 195 {0, 1, HSMP_GET}, 196 197 /* 198 * HSMP_SET_NBIO_DPM_LEVEL, num_args = 1, response_sz = 0 199 * input: args[0] = nbioid[23:16] + max dpm level[15:8] + min dpm level[7:0] 200 */ 201 {1, 0, HSMP_SET}, 202 203 /* 204 * HSMP_GET_NBIO_DPM_LEVEL, num_args = 1, response_sz = 1 205 * input: args[0] = nbioid[23:16] 206 * output: args[0] = max dpm level[15:8] + min dpm level[7:0] 207 */ 208 {1, 1, HSMP_GET}, 209 210 /* 211 * HSMP_GET_DDR_BANDWIDTH, num_args = 0, response_sz = 1 212 * output: args[0] = max bw in Gbps[31:20] + utilised bw in Gbps[19:8] + 213 * bw in percentage[7:0] 214 */ 215 {0, 1, HSMP_GET}, 216 217 /* 218 * HSMP_GET_TEMP_MONITOR, num_args = 0, response_sz = 1 219 * output: args[0] = temperature in degree celsius. [15:8] integer part + 220 * [7:5] fractional part 221 */ 222 {0, 1, HSMP_GET}, 223 224 /* 225 * HSMP_GET_DIMM_TEMP_RANGE, num_args = 1, response_sz = 1 226 * input: args[0] = DIMM address[7:0] 227 * output: args[0] = refresh rate[3] + temperature range[2:0] 228 */ 229 {1, 1, HSMP_GET}, 230 231 /* 232 * HSMP_GET_DIMM_POWER, num_args = 1, response_sz = 1 233 * input: args[0] = DIMM address[7:0] 234 * output: args[0] = DIMM power in mW[31:17] + update rate in ms[16:8] + 235 * DIMM address[7:0] 236 */ 237 {1, 1, HSMP_GET}, 238 239 /* 240 * HSMP_GET_DIMM_THERMAL, num_args = 1, response_sz = 1 241 * input: args[0] = DIMM address[7:0] 242 * output: args[0] = temperature in degree celsius[31:21] + update rate in ms[16:8] + 243 * DIMM address[7:0] 244 */ 245 {1, 1, HSMP_GET}, 246 247 /* 248 * HSMP_GET_SOCKET_FREQ_LIMIT, num_args = 0, response_sz = 1 249 * output: args[0] = frequency in MHz[31:16] + frequency source[15:0] 250 */ 251 {0, 1, HSMP_GET}, 252 253 /* 254 * HSMP_GET_CCLK_CORE_LIMIT, num_args = 1, response_sz = 1 255 * input: args[0] = apic id [31:0] 256 * output: args[0] = frequency in MHz[31:0] 257 */ 258 {1, 1, HSMP_GET}, 259 260 /* 261 * HSMP_GET_RAILS_SVI, num_args = 0, response_sz = 1 262 * output: args[0] = power in mW[31:0] 263 */ 264 {0, 1, HSMP_GET}, 265 266 /* 267 * HSMP_GET_SOCKET_FMAX_FMIN, num_args = 0, response_sz = 1 268 * output: args[0] = fmax in MHz[31:16] + fmin in MHz[15:0] 269 */ 270 {0, 1, HSMP_GET}, 271 272 /* 273 * HSMP_GET_IOLINK_BANDWITH, num_args = 1, response_sz = 1 274 * input: args[0] = link id[15:8] + bw type[2:0] 275 * output: args[0] = io bandwidth in Mbps[31:0] 276 */ 277 {1, 1, HSMP_GET}, 278 279 /* 280 * HSMP_GET_XGMI_BANDWITH, num_args = 1, response_sz = 1 281 * input: args[0] = link id[15:8] + bw type[2:0] 282 * output: args[0] = xgmi bandwidth in Mbps[31:0] 283 */ 284 {1, 1, HSMP_GET}, 285 286 /* 287 * HSMP_SET_GMI3_WIDTH, num_args = 1, response_sz = 0 288 * input: args[0] = min link width[15:8] + max link width[7:0] 289 */ 290 {1, 0, HSMP_SET}, 291 292 /* 293 * HSMP_SET_PCI_RATE, num_args = 1, response_sz = 1 294 * input: args[0] = link rate control value 295 * output: args[0] = previous link rate control value 296 */ 297 {1, 1, HSMP_SET}, 298 299 /* 300 * HSMP_SET_POWER_MODE, num_args = 1, response_sz = 0 301 * input: args[0] = power efficiency mode[2:0] 302 */ 303 {1, 0, HSMP_SET}, 304 305 /* 306 * HSMP_SET_PSTATE_MAX_MIN, num_args = 1, response_sz = 0 307 * input: args[0] = min df pstate[15:8] + max df pstate[7:0] 308 */ 309 {1, 0, HSMP_SET}, 310 311 /* 312 * HSMP_GET_METRIC_TABLE_VER, num_args = 0, response_sz = 1 313 * output: args[0] = metrics table version 314 */ 315 {0, 1, HSMP_GET}, 316 317 /* 318 * HSMP_GET_METRIC_TABLE, num_args = 0, response_sz = 0 319 */ 320 {0, 0, HSMP_GET}, 321 322 /* 323 * HSMP_GET_METRIC_TABLE_DRAM_ADDR, num_args = 0, response_sz = 2 324 * output: args[0] = lower 32 bits of the address 325 * output: args[1] = upper 32 bits of the address 326 */ 327 {0, 2, HSMP_GET}, 328 }; 329 330 /* Metrics table (supported only with proto version 6) */ 331 struct hsmp_metric_table { 332 __u32 accumulation_counter; 333 334 /* TEMPERATURE */ 335 __u32 max_socket_temperature; 336 __u32 max_vr_temperature; 337 __u32 max_hbm_temperature; 338 __u64 max_socket_temperature_acc; 339 __u64 max_vr_temperature_acc; 340 __u64 max_hbm_temperature_acc; 341 342 /* POWER */ 343 __u32 socket_power_limit; 344 __u32 max_socket_power_limit; 345 __u32 socket_power; 346 347 /* ENERGY */ 348 __u64 timestamp; 349 __u64 socket_energy_acc; 350 __u64 ccd_energy_acc; 351 __u64 xcd_energy_acc; 352 __u64 aid_energy_acc; 353 __u64 hbm_energy_acc; 354 355 /* FREQUENCY */ 356 __u32 cclk_frequency_limit; 357 __u32 gfxclk_frequency_limit; 358 __u32 fclk_frequency; 359 __u32 uclk_frequency; 360 __u32 socclk_frequency[4]; 361 __u32 vclk_frequency[4]; 362 __u32 dclk_frequency[4]; 363 __u32 lclk_frequency[4]; 364 __u64 gfxclk_frequency_acc[8]; 365 __u64 cclk_frequency_acc[96]; 366 367 /* FREQUENCY RANGE */ 368 __u32 max_cclk_frequency; 369 __u32 min_cclk_frequency; 370 __u32 max_gfxclk_frequency; 371 __u32 min_gfxclk_frequency; 372 __u32 fclk_frequency_table[4]; 373 __u32 uclk_frequency_table[4]; 374 __u32 socclk_frequency_table[4]; 375 __u32 vclk_frequency_table[4]; 376 __u32 dclk_frequency_table[4]; 377 __u32 lclk_frequency_table[4]; 378 __u32 max_lclk_dpm_range; 379 __u32 min_lclk_dpm_range; 380 381 /* XGMI */ 382 __u32 xgmi_width; 383 __u32 xgmi_bitrate; 384 __u64 xgmi_read_bandwidth_acc[8]; 385 __u64 xgmi_write_bandwidth_acc[8]; 386 387 /* ACTIVITY */ 388 __u32 socket_c0_residency; 389 __u32 socket_gfx_busy; 390 __u32 dram_bandwidth_utilization; 391 __u64 socket_c0_residency_acc; 392 __u64 socket_gfx_busy_acc; 393 __u64 dram_bandwidth_acc; 394 __u32 max_dram_bandwidth; 395 __u64 dram_bandwidth_utilization_acc; 396 __u64 pcie_bandwidth_acc[4]; 397 398 /* THROTTLERS */ 399 __u32 prochot_residency_acc; 400 __u32 ppt_residency_acc; 401 __u32 socket_thm_residency_acc; 402 __u32 vr_thm_residency_acc; 403 __u32 hbm_thm_residency_acc; 404 __u32 spare; 405 406 /* New items at the end to maintain driver compatibility */ 407 __u32 gfxclk_frequency[8]; 408 }; 409 410 /* Reset to default packing */ 411 #pragma pack() 412 413 /* Define unique ioctl command for hsmp msgs using generic _IOWR */ 414 #define HSMP_BASE_IOCTL_NR 0xF8 415 #define HSMP_IOCTL_CMD _IOWR(HSMP_BASE_IOCTL_NR, 0, struct hsmp_message) 416 417 #endif /*_ASM_X86_AMD_HSMP_H_*/ 418