1bb898558SAl Viro /****************************************************************************** 2bb898558SAl Viro * arch-x86_32.h 3bb898558SAl Viro * 4bb898558SAl Viro * Guest OS interface to x86 Xen. 5bb898558SAl Viro * 617fb46b1SJuergen Gross * Permission is hereby granted, free of charge, to any person obtaining a copy 717fb46b1SJuergen Gross * of this software and associated documentation files (the "Software"), to 817fb46b1SJuergen Gross * deal in the Software without restriction, including without limitation the 917fb46b1SJuergen Gross * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 1017fb46b1SJuergen Gross * sell copies of the Software, and to permit persons to whom the Software is 1117fb46b1SJuergen Gross * furnished to do so, subject to the following conditions: 1217fb46b1SJuergen Gross * 1317fb46b1SJuergen Gross * The above copyright notice and this permission notice shall be included in 1417fb46b1SJuergen Gross * all copies or substantial portions of the Software. 1517fb46b1SJuergen Gross * 1617fb46b1SJuergen Gross * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1717fb46b1SJuergen Gross * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1817fb46b1SJuergen Gross * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 1917fb46b1SJuergen Gross * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2017fb46b1SJuergen Gross * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 2117fb46b1SJuergen Gross * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 2217fb46b1SJuergen Gross * DEALINGS IN THE SOFTWARE. 2317fb46b1SJuergen Gross * 2417fb46b1SJuergen Gross * Copyright (c) 2004-2006, K A Fraser 25bb898558SAl Viro */ 26bb898558SAl Viro 2705e4d316SH. Peter Anvin #ifndef _ASM_X86_XEN_INTERFACE_H 2805e4d316SH. Peter Anvin #define _ASM_X86_XEN_INTERFACE_H 29bb898558SAl Viro 3017fb46b1SJuergen Gross /* 3117fb46b1SJuergen Gross * XEN_GUEST_HANDLE represents a guest pointer, when passed as a field 3217fb46b1SJuergen Gross * in a struct in memory. 3317fb46b1SJuergen Gross * XEN_GUEST_HANDLE_PARAM represent a guest pointer, when passed as an 3417fb46b1SJuergen Gross * hypercall argument. 3517fb46b1SJuergen Gross * XEN_GUEST_HANDLE_PARAM and XEN_GUEST_HANDLE are the same on X86 but 3617fb46b1SJuergen Gross * they might not be on other architectures. 3717fb46b1SJuergen Gross */ 38bb898558SAl Viro #ifdef __XEN__ 39bb898558SAl Viro #define __DEFINE_GUEST_HANDLE(name, type) \ 40bb898558SAl Viro typedef struct { type *p; } __guest_handle_ ## name 41bb898558SAl Viro #else 42bb898558SAl Viro #define __DEFINE_GUEST_HANDLE(name, type) \ 43bb898558SAl Viro typedef type * __guest_handle_ ## name 44bb898558SAl Viro #endif 45bb898558SAl Viro 46bb898558SAl Viro #define DEFINE_GUEST_HANDLE_STRUCT(name) \ 47bb898558SAl Viro __DEFINE_GUEST_HANDLE(name, struct name) 48bb898558SAl Viro #define DEFINE_GUEST_HANDLE(name) __DEFINE_GUEST_HANDLE(name, name) 49bb898558SAl Viro #define GUEST_HANDLE(name) __guest_handle_ ## name 50bb898558SAl Viro 51bb898558SAl Viro #ifdef __XEN__ 52bb898558SAl Viro #if defined(__i386__) 53bb898558SAl Viro #define set_xen_guest_handle(hnd, val) \ 54bb898558SAl Viro do { \ 55bb898558SAl Viro if (sizeof(hnd) == 8) \ 56bb898558SAl Viro *(uint64_t *)&(hnd) = 0; \ 57bb898558SAl Viro (hnd).p = val; \ 58bb898558SAl Viro } while (0) 59bb898558SAl Viro #elif defined(__x86_64__) 60bb898558SAl Viro #define set_xen_guest_handle(hnd, val) do { (hnd).p = val; } while (0) 61bb898558SAl Viro #endif 62bb898558SAl Viro #else 63bb898558SAl Viro #if defined(__i386__) 64bb898558SAl Viro #define set_xen_guest_handle(hnd, val) \ 65bb898558SAl Viro do { \ 66bb898558SAl Viro if (sizeof(hnd) == 8) \ 67bb898558SAl Viro *(uint64_t *)&(hnd) = 0; \ 68bb898558SAl Viro (hnd) = val; \ 69bb898558SAl Viro } while (0) 70bb898558SAl Viro #elif defined(__x86_64__) 71bb898558SAl Viro #define set_xen_guest_handle(hnd, val) do { (hnd) = val; } while (0) 72bb898558SAl Viro #endif 73bb898558SAl Viro #endif 74bb898558SAl Viro 75bb898558SAl Viro #ifndef __ASSEMBLY__ 76bd3f79b7SStefano Stabellini /* Explicitly size integers that represent pfns in the public interface 77bd3f79b7SStefano Stabellini * with Xen so that on ARM we can have one ABI that works for 32 and 64 78bd3f79b7SStefano Stabellini * bit guests. */ 79bd3f79b7SStefano Stabellini typedef unsigned long xen_pfn_t; 8037ea0fcbSIan Campbell #define PRI_xen_pfn "lx" 81256f631fSStefano Stabellini typedef unsigned long xen_ulong_t; 8237ea0fcbSIan Campbell #define PRI_xen_ulong "lx" 835e40704eSIan Campbell typedef long xen_long_t; 845e40704eSIan Campbell #define PRI_xen_long "lx" 855e40704eSIan Campbell 86bb898558SAl Viro /* Guest handles for primitive C types. */ 87bb898558SAl Viro __DEFINE_GUEST_HANDLE(uchar, unsigned char); 88bb898558SAl Viro __DEFINE_GUEST_HANDLE(uint, unsigned int); 89bb898558SAl Viro DEFINE_GUEST_HANDLE(char); 90bb898558SAl Viro DEFINE_GUEST_HANDLE(int); 91bb898558SAl Viro DEFINE_GUEST_HANDLE(void); 923e099679SYu Ke DEFINE_GUEST_HANDLE(uint64_t); 9373c154c6SKonrad Rzeszutek Wilk DEFINE_GUEST_HANDLE(uint32_t); 94bd3f79b7SStefano Stabellini DEFINE_GUEST_HANDLE(xen_pfn_t); 95f832da06SIan Campbell DEFINE_GUEST_HANDLE(xen_ulong_t); 96bb898558SAl Viro #endif 97bb898558SAl Viro 98bb898558SAl Viro #ifndef HYPERVISOR_VIRT_START 99bb898558SAl Viro #define HYPERVISOR_VIRT_START mk_unsigned_long(__HYPERVISOR_VIRT_START) 100bb898558SAl Viro #endif 101bb898558SAl Viro 1027e77506aSIan Campbell #define MACH2PHYS_VIRT_START mk_unsigned_long(__MACH2PHYS_VIRT_START) 1037e77506aSIan Campbell #define MACH2PHYS_VIRT_END mk_unsigned_long(__MACH2PHYS_VIRT_END) 1047e77506aSIan Campbell #define MACH2PHYS_NR_ENTRIES ((MACH2PHYS_VIRT_END-MACH2PHYS_VIRT_START)>>__MACH2PHYS_SHIFT) 105bb898558SAl Viro 106bb898558SAl Viro /* Maximum number of virtual CPUs in multi-processor guests. */ 107bb898558SAl Viro #define MAX_VIRT_CPUS 32 108bb898558SAl Viro 109bb898558SAl Viro /* 110bb898558SAl Viro * SEGMENT DESCRIPTOR TABLES 111bb898558SAl Viro */ 112bb898558SAl Viro /* 113bb898558SAl Viro * A number of GDT entries are reserved by Xen. These are not situated at the 114bb898558SAl Viro * start of the GDT because some stupid OSes export hard-coded selector values 115bb898558SAl Viro * in their ABI. These hard-coded values are always near the start of the GDT, 116bb898558SAl Viro * so Xen places itself out of the way, at the far end of the GDT. 11717fb46b1SJuergen Gross * 11817fb46b1SJuergen Gross * NB The LDT is set using the MMUEXT_SET_LDT op of HYPERVISOR_mmuext_op 119bb898558SAl Viro */ 120bb898558SAl Viro #define FIRST_RESERVED_GDT_PAGE 14 121bb898558SAl Viro #define FIRST_RESERVED_GDT_BYTE (FIRST_RESERVED_GDT_PAGE * 4096) 122bb898558SAl Viro #define FIRST_RESERVED_GDT_ENTRY (FIRST_RESERVED_GDT_BYTE / 8) 123bb898558SAl Viro 124bb898558SAl Viro /* 12517fb46b1SJuergen Gross * Send an array of these to HYPERVISOR_set_trap_table(). 12617fb46b1SJuergen Gross * Terminate the array with a sentinel entry, with traps[].address==0. 127bb898558SAl Viro * The privilege level specifies which modes may enter a trap via a software 128bb898558SAl Viro * interrupt. On x86/64, since rings 1 and 2 are unavailable, we allocate 129bb898558SAl Viro * privilege levels as follows: 130bb898558SAl Viro * Level == 0: No one may enter 131bb898558SAl Viro * Level == 1: Kernel may enter 132bb898558SAl Viro * Level == 2: Kernel may enter 133bb898558SAl Viro * Level == 3: Everyone may enter 134bb898558SAl Viro */ 135bb898558SAl Viro #define TI_GET_DPL(_ti) ((_ti)->flags & 3) 136bb898558SAl Viro #define TI_GET_IF(_ti) ((_ti)->flags & 4) 137bb898558SAl Viro #define TI_SET_DPL(_ti, _dpl) ((_ti)->flags |= (_dpl)) 138bb898558SAl Viro #define TI_SET_IF(_ti, _if) ((_ti)->flags |= ((!!(_if))<<2)) 139bb898558SAl Viro 140bb898558SAl Viro #ifndef __ASSEMBLY__ 141bb898558SAl Viro struct trap_info { 142bb898558SAl Viro uint8_t vector; /* exception vector */ 143bb898558SAl Viro uint8_t flags; /* 0-3: privilege level; 4: clear event enable? */ 144bb898558SAl Viro uint16_t cs; /* code selector */ 145bb898558SAl Viro unsigned long address; /* code offset */ 146bb898558SAl Viro }; 147bb898558SAl Viro DEFINE_GUEST_HANDLE_STRUCT(trap_info); 148bb898558SAl Viro 149bb898558SAl Viro struct arch_shared_info { 15017fb46b1SJuergen Gross /* 15117fb46b1SJuergen Gross * Number of valid entries in the p2m table(s) anchored at 15217fb46b1SJuergen Gross * pfn_to_mfn_frame_list_list and/or p2m_vaddr. 15317fb46b1SJuergen Gross */ 15417fb46b1SJuergen Gross unsigned long max_pfn; 15517fb46b1SJuergen Gross /* 15617fb46b1SJuergen Gross * Frame containing list of mfns containing list of mfns containing p2m. 15717fb46b1SJuergen Gross * A value of 0 indicates it has not yet been set up, ~0 indicates it 15817fb46b1SJuergen Gross * has been set to invalid e.g. due to the p2m being too large for the 15917fb46b1SJuergen Gross * 3-level p2m tree. In this case the linear mapper p2m list anchored 16017fb46b1SJuergen Gross * at p2m_vaddr is to be used. 16117fb46b1SJuergen Gross */ 16217fb46b1SJuergen Gross xen_pfn_t pfn_to_mfn_frame_list_list; 163bb898558SAl Viro unsigned long nmi_reason; 16417fb46b1SJuergen Gross /* 16517fb46b1SJuergen Gross * Following three fields are valid if p2m_cr3 contains a value 16617fb46b1SJuergen Gross * different from 0. 16717fb46b1SJuergen Gross * p2m_cr3 is the root of the address space where p2m_vaddr is valid. 16817fb46b1SJuergen Gross * p2m_cr3 is in the same format as a cr3 value in the vcpu register 16917fb46b1SJuergen Gross * state and holds the folded machine frame number (via xen_pfn_to_cr3) 17017fb46b1SJuergen Gross * of a L3 or L4 page table. 17117fb46b1SJuergen Gross * p2m_vaddr holds the virtual address of the linear p2m list. All 17217fb46b1SJuergen Gross * entries in the range [0...max_pfn[ are accessible via this pointer. 17317fb46b1SJuergen Gross * p2m_generation will be incremented by the guest before and after each 17417fb46b1SJuergen Gross * change of the mappings of the p2m list. p2m_generation starts at 0 17517fb46b1SJuergen Gross * and a value with the least significant bit set indicates that a 17617fb46b1SJuergen Gross * mapping update is in progress. This allows guest external software 17717fb46b1SJuergen Gross * (e.g. in Dom0) to verify that read mappings are consistent and 17817fb46b1SJuergen Gross * whether they have changed since the last check. 17917fb46b1SJuergen Gross * Modifying a p2m element in the linear p2m list is allowed via an 18017fb46b1SJuergen Gross * atomic write only. 18117fb46b1SJuergen Gross */ 18217fb46b1SJuergen Gross unsigned long p2m_cr3; /* cr3 value of the p2m address space */ 18317fb46b1SJuergen Gross unsigned long p2m_vaddr; /* virtual address of the p2m list */ 18417fb46b1SJuergen Gross unsigned long p2m_generation; /* generation count of p2m mapping */ 185*42387042SDavid Woodhouse #ifdef CONFIG_X86_32 186*42387042SDavid Woodhouse uint32_t wc_sec_hi; 187*42387042SDavid Woodhouse #endif 188bb898558SAl Viro }; 189bb898558SAl Viro #endif /* !__ASSEMBLY__ */ 190bb898558SAl Viro 191bb898558SAl Viro #ifdef CONFIG_X86_32 192a1ce3928SDavid Howells #include <asm/xen/interface_32.h> 193bb898558SAl Viro #else 194a1ce3928SDavid Howells #include <asm/xen/interface_64.h> 195bb898558SAl Viro #endif 196bb898558SAl Viro 1974d9310e3SStefano Stabellini #include <asm/pvclock-abi.h> 1984d9310e3SStefano Stabellini 199bb898558SAl Viro #ifndef __ASSEMBLY__ 200bb898558SAl Viro /* 201bb898558SAl Viro * The following is all CPU context. Note that the fpu_ctxt block is filled 202bb898558SAl Viro * in by FXSAVE if the CPU has feature FXSR; otherwise FSAVE is used. 20317fb46b1SJuergen Gross * 20417fb46b1SJuergen Gross * Also note that when calling DOMCTL_setvcpucontext and VCPU_initialise 20517fb46b1SJuergen Gross * for HVM and PVH guests, not all information in this structure is updated: 20617fb46b1SJuergen Gross * 20717fb46b1SJuergen Gross * - For HVM guests, the structures read include: fpu_ctxt (if 20817fb46b1SJuergen Gross * VGCT_I387_VALID is set), flags, user_regs, debugreg[*] 20917fb46b1SJuergen Gross * 21017fb46b1SJuergen Gross * - PVH guests are the same as HVM guests, but additionally use ctrlreg[3] to 21117fb46b1SJuergen Gross * set cr3. All other fields not used should be set to 0. 212bb898558SAl Viro */ 213bb898558SAl Viro struct vcpu_guest_context { 214bb898558SAl Viro /* FPU registers come first so they can be aligned for FXSAVE/FXRSTOR. */ 215bb898558SAl Viro struct { char x[512]; } fpu_ctxt; /* User-level FPU registers */ 216bb898558SAl Viro #define VGCF_I387_VALID (1<<0) 217bb898558SAl Viro #define VGCF_IN_KERNEL (1<<2) 21817fb46b1SJuergen Gross #define _VGCF_i387_valid 0 21917fb46b1SJuergen Gross #define VGCF_i387_valid (1<<_VGCF_i387_valid) 22017fb46b1SJuergen Gross #define _VGCF_in_kernel 2 22117fb46b1SJuergen Gross #define VGCF_in_kernel (1<<_VGCF_in_kernel) 22217fb46b1SJuergen Gross #define _VGCF_failsafe_disables_events 3 22317fb46b1SJuergen Gross #define VGCF_failsafe_disables_events (1<<_VGCF_failsafe_disables_events) 22417fb46b1SJuergen Gross #define _VGCF_syscall_disables_events 4 22517fb46b1SJuergen Gross #define VGCF_syscall_disables_events (1<<_VGCF_syscall_disables_events) 22617fb46b1SJuergen Gross #define _VGCF_online 5 22717fb46b1SJuergen Gross #define VGCF_online (1<<_VGCF_online) 228bb898558SAl Viro unsigned long flags; /* VGCF_* flags */ 229bb898558SAl Viro struct cpu_user_regs user_regs; /* User-level CPU registers */ 230bb898558SAl Viro struct trap_info trap_ctxt[256]; /* Virtual IDT */ 231bb898558SAl Viro unsigned long ldt_base, ldt_ents; /* LDT (linear address, # ents) */ 232bb898558SAl Viro unsigned long gdt_frames[16], gdt_ents; /* GDT (machine frames, # ents) */ 233bb898558SAl Viro unsigned long kernel_ss, kernel_sp; /* Virtual TSS (only SS1/SP1) */ 234bb898558SAl Viro /* NB. User pagetable on x86/64 is placed in ctrlreg[1]. */ 235bb898558SAl Viro unsigned long ctrlreg[8]; /* CR0-CR7 (control registers) */ 236bb898558SAl Viro unsigned long debugreg[8]; /* DB0-DB7 (debug registers) */ 237bb898558SAl Viro #ifdef __i386__ 238bb898558SAl Viro unsigned long event_callback_cs; /* CS:EIP of event callback */ 239bb898558SAl Viro unsigned long event_callback_eip; 240bb898558SAl Viro unsigned long failsafe_callback_cs; /* CS:EIP of failsafe callback */ 241bb898558SAl Viro unsigned long failsafe_callback_eip; 242bb898558SAl Viro #else 243bb898558SAl Viro unsigned long event_callback_eip; 244bb898558SAl Viro unsigned long failsafe_callback_eip; 245bb898558SAl Viro unsigned long syscall_callback_eip; 246bb898558SAl Viro #endif 247bb898558SAl Viro unsigned long vm_assist; /* VMASST_TYPE_* bitmap */ 248bb898558SAl Viro #ifdef __x86_64__ 249bb898558SAl Viro /* Segment base addresses. */ 250bb898558SAl Viro uint64_t fs_base; 251bb898558SAl Viro uint64_t gs_base_kernel; 252bb898558SAl Viro uint64_t gs_base_user; 253bb898558SAl Viro #endif 254bb898558SAl Viro }; 255bb898558SAl Viro DEFINE_GUEST_HANDLE_STRUCT(vcpu_guest_context); 25665d0cf0bSBoris Ostrovsky 25765d0cf0bSBoris Ostrovsky /* AMD PMU registers and structures */ 25865d0cf0bSBoris Ostrovsky struct xen_pmu_amd_ctxt { 25965d0cf0bSBoris Ostrovsky /* 26065d0cf0bSBoris Ostrovsky * Offsets to counter and control MSRs (relative to xen_pmu_arch.c.amd). 26165d0cf0bSBoris Ostrovsky * For PV(H) guests these fields are RO. 26265d0cf0bSBoris Ostrovsky */ 26365d0cf0bSBoris Ostrovsky uint32_t counters; 26465d0cf0bSBoris Ostrovsky uint32_t ctrls; 26565d0cf0bSBoris Ostrovsky 26665d0cf0bSBoris Ostrovsky /* Counter MSRs */ 26765d0cf0bSBoris Ostrovsky #if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L 26865d0cf0bSBoris Ostrovsky uint64_t regs[]; 26965d0cf0bSBoris Ostrovsky #elif defined(__GNUC__) 27065d0cf0bSBoris Ostrovsky uint64_t regs[0]; 27165d0cf0bSBoris Ostrovsky #endif 27265d0cf0bSBoris Ostrovsky }; 27365d0cf0bSBoris Ostrovsky 27465d0cf0bSBoris Ostrovsky /* Intel PMU registers and structures */ 27565d0cf0bSBoris Ostrovsky struct xen_pmu_cntr_pair { 27665d0cf0bSBoris Ostrovsky uint64_t counter; 27765d0cf0bSBoris Ostrovsky uint64_t control; 27865d0cf0bSBoris Ostrovsky }; 27965d0cf0bSBoris Ostrovsky 28065d0cf0bSBoris Ostrovsky struct xen_pmu_intel_ctxt { 28165d0cf0bSBoris Ostrovsky /* 28265d0cf0bSBoris Ostrovsky * Offsets to fixed and architectural counter MSRs (relative to 28365d0cf0bSBoris Ostrovsky * xen_pmu_arch.c.intel). 28465d0cf0bSBoris Ostrovsky * For PV(H) guests these fields are RO. 28565d0cf0bSBoris Ostrovsky */ 28665d0cf0bSBoris Ostrovsky uint32_t fixed_counters; 28765d0cf0bSBoris Ostrovsky uint32_t arch_counters; 28865d0cf0bSBoris Ostrovsky 28965d0cf0bSBoris Ostrovsky /* PMU registers */ 29065d0cf0bSBoris Ostrovsky uint64_t global_ctrl; 29165d0cf0bSBoris Ostrovsky uint64_t global_ovf_ctrl; 29265d0cf0bSBoris Ostrovsky uint64_t global_status; 29365d0cf0bSBoris Ostrovsky uint64_t fixed_ctrl; 29465d0cf0bSBoris Ostrovsky uint64_t ds_area; 29565d0cf0bSBoris Ostrovsky uint64_t pebs_enable; 29665d0cf0bSBoris Ostrovsky uint64_t debugctl; 29765d0cf0bSBoris Ostrovsky 29865d0cf0bSBoris Ostrovsky /* Fixed and architectural counter MSRs */ 29965d0cf0bSBoris Ostrovsky #if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L 30065d0cf0bSBoris Ostrovsky uint64_t regs[]; 30165d0cf0bSBoris Ostrovsky #elif defined(__GNUC__) 30265d0cf0bSBoris Ostrovsky uint64_t regs[0]; 30365d0cf0bSBoris Ostrovsky #endif 30465d0cf0bSBoris Ostrovsky }; 30565d0cf0bSBoris Ostrovsky 30665d0cf0bSBoris Ostrovsky /* Sampled domain's registers */ 30765d0cf0bSBoris Ostrovsky struct xen_pmu_regs { 30865d0cf0bSBoris Ostrovsky uint64_t ip; 30965d0cf0bSBoris Ostrovsky uint64_t sp; 31065d0cf0bSBoris Ostrovsky uint64_t flags; 31165d0cf0bSBoris Ostrovsky uint16_t cs; 31265d0cf0bSBoris Ostrovsky uint16_t ss; 31365d0cf0bSBoris Ostrovsky uint8_t cpl; 31465d0cf0bSBoris Ostrovsky uint8_t pad[3]; 31565d0cf0bSBoris Ostrovsky }; 31665d0cf0bSBoris Ostrovsky 31765d0cf0bSBoris Ostrovsky /* PMU flags */ 31865d0cf0bSBoris Ostrovsky #define PMU_CACHED (1<<0) /* PMU MSRs are cached in the context */ 31965d0cf0bSBoris Ostrovsky #define PMU_SAMPLE_USER (1<<1) /* Sample is from user or kernel mode */ 32065d0cf0bSBoris Ostrovsky #define PMU_SAMPLE_REAL (1<<2) /* Sample is from realmode */ 32165d0cf0bSBoris Ostrovsky #define PMU_SAMPLE_PV (1<<3) /* Sample from a PV guest */ 32265d0cf0bSBoris Ostrovsky 32365d0cf0bSBoris Ostrovsky /* 32465d0cf0bSBoris Ostrovsky * Architecture-specific information describing state of the processor at 32565d0cf0bSBoris Ostrovsky * the time of PMU interrupt. 32665d0cf0bSBoris Ostrovsky * Fields of this structure marked as RW for guest should only be written by 32765d0cf0bSBoris Ostrovsky * the guest when PMU_CACHED bit in pmu_flags is set (which is done by the 32865d0cf0bSBoris Ostrovsky * hypervisor during PMU interrupt). Hypervisor will read updated data in 32965d0cf0bSBoris Ostrovsky * XENPMU_flush hypercall and clear PMU_CACHED bit. 33065d0cf0bSBoris Ostrovsky */ 33165d0cf0bSBoris Ostrovsky struct xen_pmu_arch { 33265d0cf0bSBoris Ostrovsky union { 33365d0cf0bSBoris Ostrovsky /* 33465d0cf0bSBoris Ostrovsky * Processor's registers at the time of interrupt. 33565d0cf0bSBoris Ostrovsky * WO for hypervisor, RO for guests. 33665d0cf0bSBoris Ostrovsky */ 33765d0cf0bSBoris Ostrovsky struct xen_pmu_regs regs; 33865d0cf0bSBoris Ostrovsky /* 33965d0cf0bSBoris Ostrovsky * Padding for adding new registers to xen_pmu_regs in 34065d0cf0bSBoris Ostrovsky * the future 34165d0cf0bSBoris Ostrovsky */ 34265d0cf0bSBoris Ostrovsky #define XENPMU_REGS_PAD_SZ 64 34365d0cf0bSBoris Ostrovsky uint8_t pad[XENPMU_REGS_PAD_SZ]; 34465d0cf0bSBoris Ostrovsky } r; 34565d0cf0bSBoris Ostrovsky 34665d0cf0bSBoris Ostrovsky /* WO for hypervisor, RO for guest */ 34765d0cf0bSBoris Ostrovsky uint64_t pmu_flags; 34865d0cf0bSBoris Ostrovsky 34965d0cf0bSBoris Ostrovsky /* 35065d0cf0bSBoris Ostrovsky * APIC LVTPC register. 35165d0cf0bSBoris Ostrovsky * RW for both hypervisor and guest. 35265d0cf0bSBoris Ostrovsky * Only APIC_LVT_MASKED bit is loaded by the hypervisor into hardware 35365d0cf0bSBoris Ostrovsky * during XENPMU_flush or XENPMU_lvtpc_set. 35465d0cf0bSBoris Ostrovsky */ 35565d0cf0bSBoris Ostrovsky union { 35665d0cf0bSBoris Ostrovsky uint32_t lapic_lvtpc; 35765d0cf0bSBoris Ostrovsky uint64_t pad; 35865d0cf0bSBoris Ostrovsky } l; 35965d0cf0bSBoris Ostrovsky 36065d0cf0bSBoris Ostrovsky /* 36165d0cf0bSBoris Ostrovsky * Vendor-specific PMU registers. 36265d0cf0bSBoris Ostrovsky * RW for both hypervisor and guest (see exceptions above). 36365d0cf0bSBoris Ostrovsky * Guest's updates to this field are verified and then loaded by the 36465d0cf0bSBoris Ostrovsky * hypervisor into hardware during XENPMU_flush 36565d0cf0bSBoris Ostrovsky */ 36665d0cf0bSBoris Ostrovsky union { 36765d0cf0bSBoris Ostrovsky struct xen_pmu_amd_ctxt amd; 36865d0cf0bSBoris Ostrovsky struct xen_pmu_intel_ctxt intel; 36965d0cf0bSBoris Ostrovsky 37065d0cf0bSBoris Ostrovsky /* 37165d0cf0bSBoris Ostrovsky * Padding for contexts (fixed parts only, does not include 37265d0cf0bSBoris Ostrovsky * MSR banks that are specified by offsets) 37365d0cf0bSBoris Ostrovsky */ 37465d0cf0bSBoris Ostrovsky #define XENPMU_CTXT_PAD_SZ 128 37565d0cf0bSBoris Ostrovsky uint8_t pad[XENPMU_CTXT_PAD_SZ]; 37665d0cf0bSBoris Ostrovsky } c; 37765d0cf0bSBoris Ostrovsky }; 37865d0cf0bSBoris Ostrovsky 379bb898558SAl Viro #endif /* !__ASSEMBLY__ */ 380bb898558SAl Viro 381bb898558SAl Viro /* 382bb898558SAl Viro * Prefix forces emulation of some non-trapping instructions. 383bb898558SAl Viro * Currently only CPUID. 384bb898558SAl Viro */ 385b3dc0695SMasami Hiramatsu #include <asm/emulate_prefix.h> 386b3dc0695SMasami Hiramatsu 387b3dc0695SMasami Hiramatsu #define XEN_EMULATE_PREFIX __ASM_FORM(.byte __XEN_EMULATE_PREFIX ;) 388b3dc0695SMasami Hiramatsu #define XEN_CPUID XEN_EMULATE_PREFIX __ASM_FORM(cpuid) 389bb898558SAl Viro 39005e4d316SH. Peter Anvin #endif /* _ASM_X86_XEN_INTERFACE_H */ 391