1 /* 2 * vmx.h: VMX Architecture related definitions 3 * Copyright (c) 2004, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple 16 * Place - Suite 330, Boston, MA 02111-1307 USA. 17 * 18 * A few random additions are: 19 * Copyright (C) 2006 Qumranet 20 * Avi Kivity <avi@qumranet.com> 21 * Yaniv Kamay <yaniv@qumranet.com> 22 * 23 */ 24 #ifndef VMX_H 25 #define VMX_H 26 27 28 #include <linux/bitops.h> 29 #include <linux/types.h> 30 #include <uapi/asm/vmx.h> 31 32 /* 33 * Definitions of Primary Processor-Based VM-Execution Controls. 34 */ 35 #define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004 36 #define CPU_BASED_USE_TSC_OFFSETING 0x00000008 37 #define CPU_BASED_HLT_EXITING 0x00000080 38 #define CPU_BASED_INVLPG_EXITING 0x00000200 39 #define CPU_BASED_MWAIT_EXITING 0x00000400 40 #define CPU_BASED_RDPMC_EXITING 0x00000800 41 #define CPU_BASED_RDTSC_EXITING 0x00001000 42 #define CPU_BASED_CR3_LOAD_EXITING 0x00008000 43 #define CPU_BASED_CR3_STORE_EXITING 0x00010000 44 #define CPU_BASED_CR8_LOAD_EXITING 0x00080000 45 #define CPU_BASED_CR8_STORE_EXITING 0x00100000 46 #define CPU_BASED_TPR_SHADOW 0x00200000 47 #define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000 48 #define CPU_BASED_MOV_DR_EXITING 0x00800000 49 #define CPU_BASED_UNCOND_IO_EXITING 0x01000000 50 #define CPU_BASED_USE_IO_BITMAPS 0x02000000 51 #define CPU_BASED_MONITOR_TRAP_FLAG 0x08000000 52 #define CPU_BASED_USE_MSR_BITMAPS 0x10000000 53 #define CPU_BASED_MONITOR_EXITING 0x20000000 54 #define CPU_BASED_PAUSE_EXITING 0x40000000 55 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000 56 57 #define CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x0401e172 58 59 /* 60 * Definitions of Secondary Processor-Based VM-Execution Controls. 61 */ 62 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 63 #define SECONDARY_EXEC_ENABLE_EPT 0x00000002 64 #define SECONDARY_EXEC_DESC 0x00000004 65 #define SECONDARY_EXEC_RDTSCP 0x00000008 66 #define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010 67 #define SECONDARY_EXEC_ENABLE_VPID 0x00000020 68 #define SECONDARY_EXEC_WBINVD_EXITING 0x00000040 69 #define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080 70 #define SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100 71 #define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200 72 #define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400 73 #define SECONDARY_EXEC_RDRAND_EXITING 0x00000800 74 #define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000 75 #define SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000 76 #define SECONDARY_EXEC_SHADOW_VMCS 0x00004000 77 #define SECONDARY_EXEC_ENCLS_EXITING 0x00008000 78 #define SECONDARY_EXEC_RDSEED_EXITING 0x00010000 79 #define SECONDARY_EXEC_ENABLE_PML 0x00020000 80 #define SECONDARY_EXEC_XSAVES 0x00100000 81 #define SECONDARY_EXEC_TSC_SCALING 0x02000000 82 83 #define PIN_BASED_EXT_INTR_MASK 0x00000001 84 #define PIN_BASED_NMI_EXITING 0x00000008 85 #define PIN_BASED_VIRTUAL_NMIS 0x00000020 86 #define PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040 87 #define PIN_BASED_POSTED_INTR 0x00000080 88 89 #define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x00000016 90 91 #define VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004 92 #define VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200 93 #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000 94 #define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000 95 #define VM_EXIT_SAVE_IA32_PAT 0x00040000 96 #define VM_EXIT_LOAD_IA32_PAT 0x00080000 97 #define VM_EXIT_SAVE_IA32_EFER 0x00100000 98 #define VM_EXIT_LOAD_IA32_EFER 0x00200000 99 #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000 100 #define VM_EXIT_CLEAR_BNDCFGS 0x00800000 101 102 #define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR 0x00036dff 103 104 #define VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004 105 #define VM_ENTRY_IA32E_MODE 0x00000200 106 #define VM_ENTRY_SMM 0x00000400 107 #define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800 108 #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000 109 #define VM_ENTRY_LOAD_IA32_PAT 0x00004000 110 #define VM_ENTRY_LOAD_IA32_EFER 0x00008000 111 #define VM_ENTRY_LOAD_BNDCFGS 0x00010000 112 113 #define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR 0x000011ff 114 115 #define VMX_MISC_PREEMPTION_TIMER_RATE_MASK 0x0000001f 116 #define VMX_MISC_SAVE_EFER_LMA 0x00000020 117 #define VMX_MISC_ACTIVITY_HLT 0x00000040 118 #define VMX_MISC_ZERO_LEN_INS 0x40000000 119 120 /* VMFUNC functions */ 121 #define VMX_VMFUNC_EPTP_SWITCHING 0x00000001 122 #define VMFUNC_EPTP_ENTRIES 512 123 124 static inline u32 vmx_basic_vmcs_revision_id(u64 vmx_basic) 125 { 126 return vmx_basic & GENMASK_ULL(30, 0); 127 } 128 129 static inline u32 vmx_basic_vmcs_size(u64 vmx_basic) 130 { 131 return (vmx_basic & GENMASK_ULL(44, 32)) >> 32; 132 } 133 134 static inline int vmx_misc_preemption_timer_rate(u64 vmx_misc) 135 { 136 return vmx_misc & VMX_MISC_PREEMPTION_TIMER_RATE_MASK; 137 } 138 139 static inline int vmx_misc_cr3_count(u64 vmx_misc) 140 { 141 return (vmx_misc & GENMASK_ULL(24, 16)) >> 16; 142 } 143 144 static inline int vmx_misc_max_msr(u64 vmx_misc) 145 { 146 return (vmx_misc & GENMASK_ULL(27, 25)) >> 25; 147 } 148 149 static inline int vmx_misc_mseg_revid(u64 vmx_misc) 150 { 151 return (vmx_misc & GENMASK_ULL(63, 32)) >> 32; 152 } 153 154 /* VMCS Encodings */ 155 enum vmcs_field { 156 VIRTUAL_PROCESSOR_ID = 0x00000000, 157 POSTED_INTR_NV = 0x00000002, 158 GUEST_ES_SELECTOR = 0x00000800, 159 GUEST_CS_SELECTOR = 0x00000802, 160 GUEST_SS_SELECTOR = 0x00000804, 161 GUEST_DS_SELECTOR = 0x00000806, 162 GUEST_FS_SELECTOR = 0x00000808, 163 GUEST_GS_SELECTOR = 0x0000080a, 164 GUEST_LDTR_SELECTOR = 0x0000080c, 165 GUEST_TR_SELECTOR = 0x0000080e, 166 GUEST_INTR_STATUS = 0x00000810, 167 GUEST_PML_INDEX = 0x00000812, 168 HOST_ES_SELECTOR = 0x00000c00, 169 HOST_CS_SELECTOR = 0x00000c02, 170 HOST_SS_SELECTOR = 0x00000c04, 171 HOST_DS_SELECTOR = 0x00000c06, 172 HOST_FS_SELECTOR = 0x00000c08, 173 HOST_GS_SELECTOR = 0x00000c0a, 174 HOST_TR_SELECTOR = 0x00000c0c, 175 IO_BITMAP_A = 0x00002000, 176 IO_BITMAP_A_HIGH = 0x00002001, 177 IO_BITMAP_B = 0x00002002, 178 IO_BITMAP_B_HIGH = 0x00002003, 179 MSR_BITMAP = 0x00002004, 180 MSR_BITMAP_HIGH = 0x00002005, 181 VM_EXIT_MSR_STORE_ADDR = 0x00002006, 182 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007, 183 VM_EXIT_MSR_LOAD_ADDR = 0x00002008, 184 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009, 185 VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a, 186 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b, 187 PML_ADDRESS = 0x0000200e, 188 PML_ADDRESS_HIGH = 0x0000200f, 189 TSC_OFFSET = 0x00002010, 190 TSC_OFFSET_HIGH = 0x00002011, 191 VIRTUAL_APIC_PAGE_ADDR = 0x00002012, 192 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013, 193 APIC_ACCESS_ADDR = 0x00002014, 194 APIC_ACCESS_ADDR_HIGH = 0x00002015, 195 POSTED_INTR_DESC_ADDR = 0x00002016, 196 POSTED_INTR_DESC_ADDR_HIGH = 0x00002017, 197 VM_FUNCTION_CONTROL = 0x00002018, 198 VM_FUNCTION_CONTROL_HIGH = 0x00002019, 199 EPT_POINTER = 0x0000201a, 200 EPT_POINTER_HIGH = 0x0000201b, 201 EOI_EXIT_BITMAP0 = 0x0000201c, 202 EOI_EXIT_BITMAP0_HIGH = 0x0000201d, 203 EOI_EXIT_BITMAP1 = 0x0000201e, 204 EOI_EXIT_BITMAP1_HIGH = 0x0000201f, 205 EOI_EXIT_BITMAP2 = 0x00002020, 206 EOI_EXIT_BITMAP2_HIGH = 0x00002021, 207 EOI_EXIT_BITMAP3 = 0x00002022, 208 EOI_EXIT_BITMAP3_HIGH = 0x00002023, 209 EPTP_LIST_ADDRESS = 0x00002024, 210 EPTP_LIST_ADDRESS_HIGH = 0x00002025, 211 VMREAD_BITMAP = 0x00002026, 212 VMREAD_BITMAP_HIGH = 0x00002027, 213 VMWRITE_BITMAP = 0x00002028, 214 VMWRITE_BITMAP_HIGH = 0x00002029, 215 XSS_EXIT_BITMAP = 0x0000202C, 216 XSS_EXIT_BITMAP_HIGH = 0x0000202D, 217 ENCLS_EXITING_BITMAP = 0x0000202E, 218 ENCLS_EXITING_BITMAP_HIGH = 0x0000202F, 219 TSC_MULTIPLIER = 0x00002032, 220 TSC_MULTIPLIER_HIGH = 0x00002033, 221 GUEST_PHYSICAL_ADDRESS = 0x00002400, 222 GUEST_PHYSICAL_ADDRESS_HIGH = 0x00002401, 223 VMCS_LINK_POINTER = 0x00002800, 224 VMCS_LINK_POINTER_HIGH = 0x00002801, 225 GUEST_IA32_DEBUGCTL = 0x00002802, 226 GUEST_IA32_DEBUGCTL_HIGH = 0x00002803, 227 GUEST_IA32_PAT = 0x00002804, 228 GUEST_IA32_PAT_HIGH = 0x00002805, 229 GUEST_IA32_EFER = 0x00002806, 230 GUEST_IA32_EFER_HIGH = 0x00002807, 231 GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808, 232 GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809, 233 GUEST_PDPTR0 = 0x0000280a, 234 GUEST_PDPTR0_HIGH = 0x0000280b, 235 GUEST_PDPTR1 = 0x0000280c, 236 GUEST_PDPTR1_HIGH = 0x0000280d, 237 GUEST_PDPTR2 = 0x0000280e, 238 GUEST_PDPTR2_HIGH = 0x0000280f, 239 GUEST_PDPTR3 = 0x00002810, 240 GUEST_PDPTR3_HIGH = 0x00002811, 241 GUEST_BNDCFGS = 0x00002812, 242 GUEST_BNDCFGS_HIGH = 0x00002813, 243 HOST_IA32_PAT = 0x00002c00, 244 HOST_IA32_PAT_HIGH = 0x00002c01, 245 HOST_IA32_EFER = 0x00002c02, 246 HOST_IA32_EFER_HIGH = 0x00002c03, 247 HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04, 248 HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05, 249 PIN_BASED_VM_EXEC_CONTROL = 0x00004000, 250 CPU_BASED_VM_EXEC_CONTROL = 0x00004002, 251 EXCEPTION_BITMAP = 0x00004004, 252 PAGE_FAULT_ERROR_CODE_MASK = 0x00004006, 253 PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008, 254 CR3_TARGET_COUNT = 0x0000400a, 255 VM_EXIT_CONTROLS = 0x0000400c, 256 VM_EXIT_MSR_STORE_COUNT = 0x0000400e, 257 VM_EXIT_MSR_LOAD_COUNT = 0x00004010, 258 VM_ENTRY_CONTROLS = 0x00004012, 259 VM_ENTRY_MSR_LOAD_COUNT = 0x00004014, 260 VM_ENTRY_INTR_INFO_FIELD = 0x00004016, 261 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018, 262 VM_ENTRY_INSTRUCTION_LEN = 0x0000401a, 263 TPR_THRESHOLD = 0x0000401c, 264 SECONDARY_VM_EXEC_CONTROL = 0x0000401e, 265 PLE_GAP = 0x00004020, 266 PLE_WINDOW = 0x00004022, 267 VM_INSTRUCTION_ERROR = 0x00004400, 268 VM_EXIT_REASON = 0x00004402, 269 VM_EXIT_INTR_INFO = 0x00004404, 270 VM_EXIT_INTR_ERROR_CODE = 0x00004406, 271 IDT_VECTORING_INFO_FIELD = 0x00004408, 272 IDT_VECTORING_ERROR_CODE = 0x0000440a, 273 VM_EXIT_INSTRUCTION_LEN = 0x0000440c, 274 VMX_INSTRUCTION_INFO = 0x0000440e, 275 GUEST_ES_LIMIT = 0x00004800, 276 GUEST_CS_LIMIT = 0x00004802, 277 GUEST_SS_LIMIT = 0x00004804, 278 GUEST_DS_LIMIT = 0x00004806, 279 GUEST_FS_LIMIT = 0x00004808, 280 GUEST_GS_LIMIT = 0x0000480a, 281 GUEST_LDTR_LIMIT = 0x0000480c, 282 GUEST_TR_LIMIT = 0x0000480e, 283 GUEST_GDTR_LIMIT = 0x00004810, 284 GUEST_IDTR_LIMIT = 0x00004812, 285 GUEST_ES_AR_BYTES = 0x00004814, 286 GUEST_CS_AR_BYTES = 0x00004816, 287 GUEST_SS_AR_BYTES = 0x00004818, 288 GUEST_DS_AR_BYTES = 0x0000481a, 289 GUEST_FS_AR_BYTES = 0x0000481c, 290 GUEST_GS_AR_BYTES = 0x0000481e, 291 GUEST_LDTR_AR_BYTES = 0x00004820, 292 GUEST_TR_AR_BYTES = 0x00004822, 293 GUEST_INTERRUPTIBILITY_INFO = 0x00004824, 294 GUEST_ACTIVITY_STATE = 0X00004826, 295 GUEST_SYSENTER_CS = 0x0000482A, 296 VMX_PREEMPTION_TIMER_VALUE = 0x0000482E, 297 HOST_IA32_SYSENTER_CS = 0x00004c00, 298 CR0_GUEST_HOST_MASK = 0x00006000, 299 CR4_GUEST_HOST_MASK = 0x00006002, 300 CR0_READ_SHADOW = 0x00006004, 301 CR4_READ_SHADOW = 0x00006006, 302 CR3_TARGET_VALUE0 = 0x00006008, 303 CR3_TARGET_VALUE1 = 0x0000600a, 304 CR3_TARGET_VALUE2 = 0x0000600c, 305 CR3_TARGET_VALUE3 = 0x0000600e, 306 EXIT_QUALIFICATION = 0x00006400, 307 GUEST_LINEAR_ADDRESS = 0x0000640a, 308 GUEST_CR0 = 0x00006800, 309 GUEST_CR3 = 0x00006802, 310 GUEST_CR4 = 0x00006804, 311 GUEST_ES_BASE = 0x00006806, 312 GUEST_CS_BASE = 0x00006808, 313 GUEST_SS_BASE = 0x0000680a, 314 GUEST_DS_BASE = 0x0000680c, 315 GUEST_FS_BASE = 0x0000680e, 316 GUEST_GS_BASE = 0x00006810, 317 GUEST_LDTR_BASE = 0x00006812, 318 GUEST_TR_BASE = 0x00006814, 319 GUEST_GDTR_BASE = 0x00006816, 320 GUEST_IDTR_BASE = 0x00006818, 321 GUEST_DR7 = 0x0000681a, 322 GUEST_RSP = 0x0000681c, 323 GUEST_RIP = 0x0000681e, 324 GUEST_RFLAGS = 0x00006820, 325 GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822, 326 GUEST_SYSENTER_ESP = 0x00006824, 327 GUEST_SYSENTER_EIP = 0x00006826, 328 HOST_CR0 = 0x00006c00, 329 HOST_CR3 = 0x00006c02, 330 HOST_CR4 = 0x00006c04, 331 HOST_FS_BASE = 0x00006c06, 332 HOST_GS_BASE = 0x00006c08, 333 HOST_TR_BASE = 0x00006c0a, 334 HOST_GDTR_BASE = 0x00006c0c, 335 HOST_IDTR_BASE = 0x00006c0e, 336 HOST_IA32_SYSENTER_ESP = 0x00006c10, 337 HOST_IA32_SYSENTER_EIP = 0x00006c12, 338 HOST_RSP = 0x00006c14, 339 HOST_RIP = 0x00006c16, 340 }; 341 342 /* 343 * Interruption-information format 344 */ 345 #define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */ 346 #define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */ 347 #define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */ 348 #define INTR_INFO_UNBLOCK_NMI 0x1000 /* 12 */ 349 #define INTR_INFO_VALID_MASK 0x80000000 /* 31 */ 350 #define INTR_INFO_RESVD_BITS_MASK 0x7ffff000 351 352 #define VECTORING_INFO_VECTOR_MASK INTR_INFO_VECTOR_MASK 353 #define VECTORING_INFO_TYPE_MASK INTR_INFO_INTR_TYPE_MASK 354 #define VECTORING_INFO_DELIVER_CODE_MASK INTR_INFO_DELIVER_CODE_MASK 355 #define VECTORING_INFO_VALID_MASK INTR_INFO_VALID_MASK 356 357 #define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */ 358 #define INTR_TYPE_RESERVED (1 << 8) /* reserved */ 359 #define INTR_TYPE_NMI_INTR (2 << 8) /* NMI */ 360 #define INTR_TYPE_HARD_EXCEPTION (3 << 8) /* processor exception */ 361 #define INTR_TYPE_SOFT_INTR (4 << 8) /* software interrupt */ 362 #define INTR_TYPE_PRIV_SW_EXCEPTION (5 << 8) /* ICE breakpoint - undocumented */ 363 #define INTR_TYPE_SOFT_EXCEPTION (6 << 8) /* software exception */ 364 #define INTR_TYPE_OTHER_EVENT (7 << 8) /* other event */ 365 366 /* GUEST_INTERRUPTIBILITY_INFO flags. */ 367 #define GUEST_INTR_STATE_STI 0x00000001 368 #define GUEST_INTR_STATE_MOV_SS 0x00000002 369 #define GUEST_INTR_STATE_SMI 0x00000004 370 #define GUEST_INTR_STATE_NMI 0x00000008 371 372 /* GUEST_ACTIVITY_STATE flags */ 373 #define GUEST_ACTIVITY_ACTIVE 0 374 #define GUEST_ACTIVITY_HLT 1 375 #define GUEST_ACTIVITY_SHUTDOWN 2 376 #define GUEST_ACTIVITY_WAIT_SIPI 3 377 378 /* 379 * Exit Qualifications for MOV for Control Register Access 380 */ 381 #define CONTROL_REG_ACCESS_NUM 0x7 /* 2:0, number of control reg.*/ 382 #define CONTROL_REG_ACCESS_TYPE 0x30 /* 5:4, access type */ 383 #define CONTROL_REG_ACCESS_REG 0xf00 /* 10:8, general purpose reg. */ 384 #define LMSW_SOURCE_DATA_SHIFT 16 385 #define LMSW_SOURCE_DATA (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */ 386 #define REG_EAX (0 << 8) 387 #define REG_ECX (1 << 8) 388 #define REG_EDX (2 << 8) 389 #define REG_EBX (3 << 8) 390 #define REG_ESP (4 << 8) 391 #define REG_EBP (5 << 8) 392 #define REG_ESI (6 << 8) 393 #define REG_EDI (7 << 8) 394 #define REG_R8 (8 << 8) 395 #define REG_R9 (9 << 8) 396 #define REG_R10 (10 << 8) 397 #define REG_R11 (11 << 8) 398 #define REG_R12 (12 << 8) 399 #define REG_R13 (13 << 8) 400 #define REG_R14 (14 << 8) 401 #define REG_R15 (15 << 8) 402 403 /* 404 * Exit Qualifications for MOV for Debug Register Access 405 */ 406 #define DEBUG_REG_ACCESS_NUM 0x7 /* 2:0, number of debug reg. */ 407 #define DEBUG_REG_ACCESS_TYPE 0x10 /* 4, direction of access */ 408 #define TYPE_MOV_TO_DR (0 << 4) 409 #define TYPE_MOV_FROM_DR (1 << 4) 410 #define DEBUG_REG_ACCESS_REG(eq) (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */ 411 412 413 /* 414 * Exit Qualifications for APIC-Access 415 */ 416 #define APIC_ACCESS_OFFSET 0xfff /* 11:0, offset within the APIC page */ 417 #define APIC_ACCESS_TYPE 0xf000 /* 15:12, access type */ 418 #define TYPE_LINEAR_APIC_INST_READ (0 << 12) 419 #define TYPE_LINEAR_APIC_INST_WRITE (1 << 12) 420 #define TYPE_LINEAR_APIC_INST_FETCH (2 << 12) 421 #define TYPE_LINEAR_APIC_EVENT (3 << 12) 422 #define TYPE_PHYSICAL_APIC_EVENT (10 << 12) 423 #define TYPE_PHYSICAL_APIC_INST (15 << 12) 424 425 /* segment AR in VMCS -- these are different from what LAR reports */ 426 #define VMX_SEGMENT_AR_L_MASK (1 << 13) 427 428 #define VMX_AR_TYPE_ACCESSES_MASK 1 429 #define VMX_AR_TYPE_READABLE_MASK (1 << 1) 430 #define VMX_AR_TYPE_WRITEABLE_MASK (1 << 2) 431 #define VMX_AR_TYPE_CODE_MASK (1 << 3) 432 #define VMX_AR_TYPE_MASK 0x0f 433 #define VMX_AR_TYPE_BUSY_64_TSS 11 434 #define VMX_AR_TYPE_BUSY_32_TSS 11 435 #define VMX_AR_TYPE_BUSY_16_TSS 3 436 #define VMX_AR_TYPE_LDT 2 437 438 #define VMX_AR_UNUSABLE_MASK (1 << 16) 439 #define VMX_AR_S_MASK (1 << 4) 440 #define VMX_AR_P_MASK (1 << 7) 441 #define VMX_AR_L_MASK (1 << 13) 442 #define VMX_AR_DB_MASK (1 << 14) 443 #define VMX_AR_G_MASK (1 << 15) 444 #define VMX_AR_DPL_SHIFT 5 445 #define VMX_AR_DPL(ar) (((ar) >> VMX_AR_DPL_SHIFT) & 3) 446 447 #define VMX_AR_RESERVD_MASK 0xfffe0f00 448 449 #define TSS_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 0) 450 #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 1) 451 #define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 2) 452 453 #define VMX_NR_VPIDS (1 << 16) 454 #define VMX_VPID_EXTENT_INDIVIDUAL_ADDR 0 455 #define VMX_VPID_EXTENT_SINGLE_CONTEXT 1 456 #define VMX_VPID_EXTENT_ALL_CONTEXT 2 457 #define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL 3 458 459 #define VMX_EPT_EXTENT_CONTEXT 1 460 #define VMX_EPT_EXTENT_GLOBAL 2 461 #define VMX_EPT_EXTENT_SHIFT 24 462 463 #define VMX_EPT_EXECUTE_ONLY_BIT (1ull) 464 #define VMX_EPT_PAGE_WALK_4_BIT (1ull << 6) 465 #define VMX_EPT_PAGE_WALK_5_BIT (1ull << 7) 466 #define VMX_EPTP_UC_BIT (1ull << 8) 467 #define VMX_EPTP_WB_BIT (1ull << 14) 468 #define VMX_EPT_2MB_PAGE_BIT (1ull << 16) 469 #define VMX_EPT_1GB_PAGE_BIT (1ull << 17) 470 #define VMX_EPT_INVEPT_BIT (1ull << 20) 471 #define VMX_EPT_AD_BIT (1ull << 21) 472 #define VMX_EPT_EXTENT_CONTEXT_BIT (1ull << 25) 473 #define VMX_EPT_EXTENT_GLOBAL_BIT (1ull << 26) 474 475 #define VMX_VPID_INVVPID_BIT (1ull << 0) /* (32 - 32) */ 476 #define VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT (1ull << 8) /* (40 - 32) */ 477 #define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT (1ull << 9) /* (41 - 32) */ 478 #define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT (1ull << 10) /* (42 - 32) */ 479 #define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT (1ull << 11) /* (43 - 32) */ 480 481 #define VMX_EPT_MT_EPTE_SHIFT 3 482 #define VMX_EPTP_PWL_MASK 0x38ull 483 #define VMX_EPTP_PWL_4 0x18ull 484 #define VMX_EPTP_PWL_5 0x20ull 485 #define VMX_EPTP_AD_ENABLE_BIT (1ull << 6) 486 #define VMX_EPTP_MT_MASK 0x7ull 487 #define VMX_EPTP_MT_WB 0x6ull 488 #define VMX_EPTP_MT_UC 0x0ull 489 #define VMX_EPT_READABLE_MASK 0x1ull 490 #define VMX_EPT_WRITABLE_MASK 0x2ull 491 #define VMX_EPT_EXECUTABLE_MASK 0x4ull 492 #define VMX_EPT_IPAT_BIT (1ull << 6) 493 #define VMX_EPT_ACCESS_BIT (1ull << 8) 494 #define VMX_EPT_DIRTY_BIT (1ull << 9) 495 #define VMX_EPT_RWX_MASK (VMX_EPT_READABLE_MASK | \ 496 VMX_EPT_WRITABLE_MASK | \ 497 VMX_EPT_EXECUTABLE_MASK) 498 #define VMX_EPT_MT_MASK (7ull << VMX_EPT_MT_EPTE_SHIFT) 499 500 /* The mask to use to trigger an EPT Misconfiguration in order to track MMIO */ 501 #define VMX_EPT_MISCONFIG_WX_VALUE (VMX_EPT_WRITABLE_MASK | \ 502 VMX_EPT_EXECUTABLE_MASK) 503 504 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul 505 506 507 #define ASM_VMX_VMCLEAR_RAX ".byte 0x66, 0x0f, 0xc7, 0x30" 508 #define ASM_VMX_VMLAUNCH ".byte 0x0f, 0x01, 0xc2" 509 #define ASM_VMX_VMRESUME ".byte 0x0f, 0x01, 0xc3" 510 #define ASM_VMX_VMPTRLD_RAX ".byte 0x0f, 0xc7, 0x30" 511 #define ASM_VMX_VMREAD_RDX_RAX ".byte 0x0f, 0x78, 0xd0" 512 #define ASM_VMX_VMWRITE_RAX_RDX ".byte 0x0f, 0x79, 0xd0" 513 #define ASM_VMX_VMWRITE_RSP_RDX ".byte 0x0f, 0x79, 0xd4" 514 #define ASM_VMX_VMXOFF ".byte 0x0f, 0x01, 0xc4" 515 #define ASM_VMX_VMXON_RAX ".byte 0xf3, 0x0f, 0xc7, 0x30" 516 #define ASM_VMX_INVEPT ".byte 0x66, 0x0f, 0x38, 0x80, 0x08" 517 #define ASM_VMX_INVVPID ".byte 0x66, 0x0f, 0x38, 0x81, 0x08" 518 519 struct vmx_msr_entry { 520 u32 index; 521 u32 reserved; 522 u64 value; 523 } __aligned(16); 524 525 /* 526 * Exit Qualifications for entry failure during or after loading guest state 527 */ 528 #define ENTRY_FAIL_DEFAULT 0 529 #define ENTRY_FAIL_PDPTE 2 530 #define ENTRY_FAIL_NMI 3 531 #define ENTRY_FAIL_VMCS_LINK_PTR 4 532 533 /* 534 * Exit Qualifications for EPT Violations 535 */ 536 #define EPT_VIOLATION_ACC_READ_BIT 0 537 #define EPT_VIOLATION_ACC_WRITE_BIT 1 538 #define EPT_VIOLATION_ACC_INSTR_BIT 2 539 #define EPT_VIOLATION_READABLE_BIT 3 540 #define EPT_VIOLATION_WRITABLE_BIT 4 541 #define EPT_VIOLATION_EXECUTABLE_BIT 5 542 #define EPT_VIOLATION_GVA_TRANSLATED_BIT 8 543 #define EPT_VIOLATION_ACC_READ (1 << EPT_VIOLATION_ACC_READ_BIT) 544 #define EPT_VIOLATION_ACC_WRITE (1 << EPT_VIOLATION_ACC_WRITE_BIT) 545 #define EPT_VIOLATION_ACC_INSTR (1 << EPT_VIOLATION_ACC_INSTR_BIT) 546 #define EPT_VIOLATION_READABLE (1 << EPT_VIOLATION_READABLE_BIT) 547 #define EPT_VIOLATION_WRITABLE (1 << EPT_VIOLATION_WRITABLE_BIT) 548 #define EPT_VIOLATION_EXECUTABLE (1 << EPT_VIOLATION_EXECUTABLE_BIT) 549 #define EPT_VIOLATION_GVA_TRANSLATED (1 << EPT_VIOLATION_GVA_TRANSLATED_BIT) 550 551 /* 552 * VM-instruction error numbers 553 */ 554 enum vm_instruction_error_number { 555 VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1, 556 VMXERR_VMCLEAR_INVALID_ADDRESS = 2, 557 VMXERR_VMCLEAR_VMXON_POINTER = 3, 558 VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4, 559 VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5, 560 VMXERR_VMRESUME_AFTER_VMXOFF = 6, 561 VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7, 562 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8, 563 VMXERR_VMPTRLD_INVALID_ADDRESS = 9, 564 VMXERR_VMPTRLD_VMXON_POINTER = 10, 565 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11, 566 VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12, 567 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13, 568 VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15, 569 VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16, 570 VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17, 571 VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18, 572 VMXERR_VMCALL_NONCLEAR_VMCS = 19, 573 VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20, 574 VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22, 575 VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23, 576 VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24, 577 VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25, 578 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26, 579 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28, 580 }; 581 582 enum vmx_l1d_flush_state { 583 VMENTER_L1D_FLUSH_AUTO, 584 VMENTER_L1D_FLUSH_NEVER, 585 VMENTER_L1D_FLUSH_COND, 586 VMENTER_L1D_FLUSH_ALWAYS, 587 VMENTER_L1D_FLUSH_EPT_DISABLED, 588 VMENTER_L1D_FLUSH_NOT_REQUIRED, 589 }; 590 591 extern enum vmx_l1d_flush_state l1tf_vmx_mitigation; 592 593 #endif 594