1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * x86 TSC related functions 4 */ 5 #ifndef _ASM_X86_TSC_H 6 #define _ASM_X86_TSC_H 7 8 #include <asm/cpufeature.h> 9 #include <asm/processor.h> 10 #include <asm/msr.h> 11 12 /* 13 * Standard way to access the cycle counter. 14 */ 15 typedef unsigned long long cycles_t; 16 17 extern unsigned int cpu_khz; 18 extern unsigned int tsc_khz; 19 20 extern void disable_TSC(void); 21 22 static inline cycles_t get_cycles(void) 23 { 24 if (!IS_ENABLED(CONFIG_X86_TSC) && 25 !cpu_feature_enabled(X86_FEATURE_TSC)) 26 return 0; 27 return rdtsc(); 28 } 29 #define get_cycles get_cycles 30 31 extern void tsc_early_init(void); 32 extern void tsc_init(void); 33 extern void mark_tsc_unstable(char *reason); 34 extern int unsynchronized_tsc(void); 35 extern int check_tsc_unstable(void); 36 extern void mark_tsc_async_resets(char *reason); 37 extern unsigned long native_calibrate_cpu_early(void); 38 extern unsigned long native_calibrate_tsc(void); 39 extern unsigned long long native_sched_clock_from_tsc(u64 tsc); 40 41 extern int tsc_clocksource_reliable; 42 #ifdef CONFIG_X86_TSC 43 extern bool tsc_async_resets; 44 #else 45 # define tsc_async_resets false 46 #endif 47 48 /* 49 * Boot-time check whether the TSCs are synchronized across 50 * all CPUs/cores: 51 */ 52 #ifdef CONFIG_X86_TSC 53 extern bool tsc_store_and_check_tsc_adjust(bool bootcpu); 54 extern void tsc_verify_tsc_adjust(bool resume); 55 extern void check_tsc_sync_target(void); 56 #else 57 static inline bool tsc_store_and_check_tsc_adjust(bool bootcpu) { return false; } 58 static inline void tsc_verify_tsc_adjust(bool resume) { } 59 static inline void check_tsc_sync_target(void) { } 60 #endif 61 62 extern int notsc_setup(char *); 63 extern void tsc_save_sched_clock_state(void); 64 extern void tsc_restore_sched_clock_state(void); 65 66 unsigned long cpu_khz_from_msr(void); 67 68 #endif /* _ASM_X86_TSC_H */ 69