1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_TLB_H 3 #define _ASM_X86_TLB_H 4 5 #define tlb_start_vma(tlb, vma) do { } while (0) 6 #define tlb_end_vma(tlb, vma) do { } while (0) 7 #define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0) 8 9 #define tlb_flush(tlb) \ 10 { \ 11 if (!tlb->fullmm && !tlb->need_flush_all) \ 12 flush_tlb_mm_range(tlb->mm, tlb->start, tlb->end, 0UL); \ 13 else \ 14 flush_tlb_mm_range(tlb->mm, 0UL, TLB_FLUSH_ALL, 0UL); \ 15 } 16 17 #include <asm-generic/tlb.h> 18 19 /* 20 * While x86 architecture in general requires an IPI to perform TLB 21 * shootdown, enablement code for several hypervisors overrides 22 * .flush_tlb_others hook in pv_mmu_ops and implements it by issuing 23 * a hypercall. To keep software pagetable walkers safe in this case we 24 * switch to RCU based table free (HAVE_RCU_TABLE_FREE). See the comment 25 * below 'ifdef CONFIG_HAVE_RCU_TABLE_FREE' in include/asm-generic/tlb.h 26 * for more details. 27 */ 28 static inline void __tlb_remove_table(void *table) 29 { 30 free_page_and_swap_cache(table); 31 } 32 33 #endif /* _ASM_X86_TLB_H */ 34