1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __SVM_H 3 #define __SVM_H 4 5 #include <uapi/asm/svm.h> 6 #include <uapi/asm/kvm.h> 7 8 #include <hyperv/hvhdk.h> 9 10 /* 11 * 32-bit intercept words in the VMCB Control Area, starting 12 * at Byte offset 000h. 13 */ 14 15 enum intercept_words { 16 INTERCEPT_CR = 0, 17 INTERCEPT_DR, 18 INTERCEPT_EXCEPTION, 19 INTERCEPT_WORD3, 20 INTERCEPT_WORD4, 21 INTERCEPT_WORD5, 22 MAX_INTERCEPT, 23 }; 24 25 enum { 26 /* Byte offset 000h (word 0) */ 27 INTERCEPT_CR0_READ = 0, 28 INTERCEPT_CR3_READ = 3, 29 INTERCEPT_CR4_READ = 4, 30 INTERCEPT_CR8_READ = 8, 31 INTERCEPT_CR0_WRITE = 16, 32 INTERCEPT_CR3_WRITE = 16 + 3, 33 INTERCEPT_CR4_WRITE = 16 + 4, 34 INTERCEPT_CR8_WRITE = 16 + 8, 35 /* Byte offset 004h (word 1) */ 36 INTERCEPT_DR0_READ = 32, 37 INTERCEPT_DR1_READ, 38 INTERCEPT_DR2_READ, 39 INTERCEPT_DR3_READ, 40 INTERCEPT_DR4_READ, 41 INTERCEPT_DR5_READ, 42 INTERCEPT_DR6_READ, 43 INTERCEPT_DR7_READ, 44 INTERCEPT_DR0_WRITE = 48, 45 INTERCEPT_DR1_WRITE, 46 INTERCEPT_DR2_WRITE, 47 INTERCEPT_DR3_WRITE, 48 INTERCEPT_DR4_WRITE, 49 INTERCEPT_DR5_WRITE, 50 INTERCEPT_DR6_WRITE, 51 INTERCEPT_DR7_WRITE, 52 /* Byte offset 008h (word 2) */ 53 INTERCEPT_EXCEPTION_OFFSET = 64, 54 /* Byte offset 00Ch (word 3) */ 55 INTERCEPT_INTR = 96, 56 INTERCEPT_NMI, 57 INTERCEPT_SMI, 58 INTERCEPT_INIT, 59 INTERCEPT_VINTR, 60 INTERCEPT_SELECTIVE_CR0, 61 INTERCEPT_STORE_IDTR, 62 INTERCEPT_STORE_GDTR, 63 INTERCEPT_STORE_LDTR, 64 INTERCEPT_STORE_TR, 65 INTERCEPT_LOAD_IDTR, 66 INTERCEPT_LOAD_GDTR, 67 INTERCEPT_LOAD_LDTR, 68 INTERCEPT_LOAD_TR, 69 INTERCEPT_RDTSC, 70 INTERCEPT_RDPMC, 71 INTERCEPT_PUSHF, 72 INTERCEPT_POPF, 73 INTERCEPT_CPUID, 74 INTERCEPT_RSM, 75 INTERCEPT_IRET, 76 INTERCEPT_INTn, 77 INTERCEPT_INVD, 78 INTERCEPT_PAUSE, 79 INTERCEPT_HLT, 80 INTERCEPT_INVLPG, 81 INTERCEPT_INVLPGA, 82 INTERCEPT_IOIO_PROT, 83 INTERCEPT_MSR_PROT, 84 INTERCEPT_TASK_SWITCH, 85 INTERCEPT_FERR_FREEZE, 86 INTERCEPT_SHUTDOWN, 87 /* Byte offset 010h (word 4) */ 88 INTERCEPT_VMRUN = 128, 89 INTERCEPT_VMMCALL, 90 INTERCEPT_VMLOAD, 91 INTERCEPT_VMSAVE, 92 INTERCEPT_STGI, 93 INTERCEPT_CLGI, 94 INTERCEPT_SKINIT, 95 INTERCEPT_RDTSCP, 96 INTERCEPT_ICEBP, 97 INTERCEPT_WBINVD, 98 INTERCEPT_MONITOR, 99 INTERCEPT_MWAIT, 100 INTERCEPT_MWAIT_COND, 101 INTERCEPT_XSETBV, 102 INTERCEPT_RDPRU, 103 TRAP_EFER_WRITE, 104 TRAP_CR0_WRITE, 105 TRAP_CR1_WRITE, 106 TRAP_CR2_WRITE, 107 TRAP_CR3_WRITE, 108 TRAP_CR4_WRITE, 109 TRAP_CR5_WRITE, 110 TRAP_CR6_WRITE, 111 TRAP_CR7_WRITE, 112 TRAP_CR8_WRITE, 113 /* Byte offset 014h (word 5) */ 114 INTERCEPT_INVLPGB = 160, 115 INTERCEPT_INVLPGB_ILLEGAL, 116 INTERCEPT_INVPCID, 117 INTERCEPT_MCOMMIT, 118 INTERCEPT_TLBSYNC, 119 INTERCEPT_BUSLOCK, 120 INTERCEPT_IDLE_HLT = 166, 121 }; 122 123 124 struct __attribute__ ((__packed__)) vmcb_control_area { 125 u32 intercepts[MAX_INTERCEPT]; 126 u32 reserved_1[15 - MAX_INTERCEPT]; 127 u16 pause_filter_thresh; 128 u16 pause_filter_count; 129 u64 iopm_base_pa; 130 u64 msrpm_base_pa; 131 u64 tsc_offset; 132 u32 asid; 133 u8 tlb_ctl; 134 u8 erap_ctl; 135 u8 reserved_2[2]; 136 u32 int_ctl; 137 u32 int_vector; 138 u32 int_state; 139 u8 reserved_3[4]; 140 u64 exit_code; 141 u64 exit_info_1; 142 u64 exit_info_2; 143 u32 exit_int_info; 144 u32 exit_int_info_err; 145 u64 misc_ctl; 146 u64 avic_vapic_bar; 147 u64 ghcb_gpa; 148 u32 event_inj; 149 u32 event_inj_err; 150 u64 nested_cr3; 151 u64 misc_ctl2; 152 u32 clean; 153 u32 reserved_5; 154 u64 next_rip; 155 u8 insn_len; 156 u8 insn_bytes[15]; 157 u64 avic_backing_page; /* Offset 0xe0 */ 158 u8 reserved_6[8]; /* Offset 0xe8 */ 159 u64 avic_logical_id; /* Offset 0xf0 */ 160 u64 avic_physical_id; /* Offset 0xf8 */ 161 u8 reserved_7[8]; 162 u64 vmsa_pa; /* Used for an SEV-ES guest */ 163 u8 reserved_8[16]; 164 u16 bus_lock_counter; /* Offset 0x120 */ 165 u8 reserved_9[22]; 166 u64 allowed_sev_features; /* Offset 0x138 */ 167 u64 guest_sev_features; /* Offset 0x140 */ 168 u8 reserved_10[664]; 169 /* 170 * Offset 0x3e0, 32 bytes reserved 171 * for use by hypervisor/software. 172 */ 173 union { 174 struct hv_vmcb_enlightenments hv_enlightenments; 175 u8 reserved_sw[32]; 176 }; 177 }; 178 179 180 #define TLB_CONTROL_DO_NOTHING 0 181 #define TLB_CONTROL_FLUSH_ALL_ASID 1 182 #define TLB_CONTROL_FLUSH_ASID 3 183 #define TLB_CONTROL_FLUSH_ASID_LOCAL 7 184 185 #define TLB_CONTROL_MASK GENMASK(2, 0) 186 187 #define ERAP_CONTROL_ALLOW_LARGER_RAP BIT(0) 188 #define ERAP_CONTROL_CLEAR_RAP BIT(1) 189 190 #define V_TPR_MASK 0x0f 191 192 #define V_IRQ_SHIFT 8 193 #define V_IRQ_MASK (1 << V_IRQ_SHIFT) 194 195 #define V_GIF_SHIFT 9 196 #define V_GIF_MASK (1 << V_GIF_SHIFT) 197 198 #define V_NMI_PENDING_SHIFT 11 199 #define V_NMI_PENDING_MASK (1 << V_NMI_PENDING_SHIFT) 200 201 #define V_NMI_BLOCKING_SHIFT 12 202 #define V_NMI_BLOCKING_MASK (1 << V_NMI_BLOCKING_SHIFT) 203 204 #define V_INTR_PRIO_SHIFT 16 205 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT) 206 207 #define V_IGN_TPR_SHIFT 20 208 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT) 209 210 #define V_IRQ_INJECTION_BITS_MASK (V_IRQ_MASK | V_INTR_PRIO_MASK | V_IGN_TPR_MASK) 211 212 #define V_INTR_MASKING_SHIFT 24 213 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT) 214 215 #define V_GIF_ENABLE_SHIFT 25 216 #define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT) 217 218 #define V_NMI_ENABLE_SHIFT 26 219 #define V_NMI_ENABLE_MASK (1 << V_NMI_ENABLE_SHIFT) 220 221 #define AVIC_ENABLE_SHIFT 31 222 #define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT) 223 224 #define X2APIC_MODE_SHIFT 30 225 #define X2APIC_MODE_MASK (1 << X2APIC_MODE_SHIFT) 226 227 #define SVM_INT_VECTOR_MASK GENMASK(7, 0) 228 229 #define SVM_INTERRUPT_SHADOW_MASK BIT_ULL(0) 230 #define SVM_GUEST_INTERRUPT_MASK BIT_ULL(1) 231 232 #define SVM_IOIO_STR_SHIFT 2 233 #define SVM_IOIO_REP_SHIFT 3 234 #define SVM_IOIO_SIZE_SHIFT 4 235 #define SVM_IOIO_ASIZE_SHIFT 7 236 237 #define SVM_IOIO_TYPE_MASK 1 238 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT) 239 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT) 240 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT) 241 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT) 242 243 #define SVM_MISC_ENABLE_NP BIT(0) 244 #define SVM_MISC_ENABLE_SEV BIT(1) 245 #define SVM_MISC_ENABLE_SEV_ES BIT(2) 246 247 #define SVM_MISC2_ENABLE_V_LBR BIT_ULL(0) 248 #define SVM_MISC2_ENABLE_V_VMLOAD_VMSAVE BIT_ULL(1) 249 250 #define SVM_TSC_RATIO_RSVD 0xffffff0000000000ULL 251 #define SVM_TSC_RATIO_MIN 0x0000000000000001ULL 252 #define SVM_TSC_RATIO_MAX 0x000000ffffffffffULL 253 #define SVM_TSC_RATIO_DEFAULT 0x0100000000ULL 254 255 256 /* AVIC */ 257 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFFULL) 258 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31 259 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31) 260 261 /* 262 * GA_LOG_INTR is a synthetic flag that's never propagated to hardware-visible 263 * tables. GA_LOG_INTR is set if the vCPU needs device posted IRQs to generate 264 * GA log interrupts to wake the vCPU (because it's blocking or about to block). 265 */ 266 #define AVIC_PHYSICAL_ID_ENTRY_GA_LOG_INTR BIT_ULL(61) 267 268 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK GENMASK_ULL(11, 0) 269 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK GENMASK_ULL(51, 12) 270 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62) 271 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63) 272 #define AVIC_PHYSICAL_ID_TABLE_SIZE_MASK (0xFFULL) 273 274 #define AVIC_DOORBELL_PHYSICAL_ID_MASK GENMASK_ULL(11, 0) 275 276 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1 277 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0 278 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF 279 280 enum avic_ipi_failure_cause { 281 AVIC_IPI_FAILURE_INVALID_INT_TYPE, 282 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING, 283 AVIC_IPI_FAILURE_INVALID_TARGET, 284 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE, 285 AVIC_IPI_FAILURE_INVALID_IPI_VECTOR, 286 }; 287 288 #define AVIC_PHYSICAL_MAX_INDEX_MASK GENMASK_ULL(11, 0) 289 290 /* 291 * For AVIC, the max index allowed for physical APIC ID table is 0xfe (254), as 292 * 0xff is a broadcast to all CPUs, i.e. can't be targeted individually. 293 */ 294 #define AVIC_MAX_PHYSICAL_ID 0XFEULL 295 296 /* 297 * For x2AVIC, the max index allowed for physical APIC ID table is 0x1ff (511). 298 * With X86_FEATURE_X2AVIC_EXT, the max index is increased to 0xfff (4095). 299 */ 300 #define X2AVIC_MAX_PHYSICAL_ID 0x1FFUL 301 #define X2AVIC_4K_MAX_PHYSICAL_ID 0xFFFUL 302 303 static_assert((AVIC_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) == AVIC_MAX_PHYSICAL_ID); 304 static_assert((X2AVIC_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) == X2AVIC_MAX_PHYSICAL_ID); 305 static_assert((X2AVIC_4K_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) == X2AVIC_4K_MAX_PHYSICAL_ID); 306 307 #define SVM_SEV_FEAT_SNP_ACTIVE BIT(0) 308 #define SVM_SEV_FEAT_RESTRICTED_INJECTION BIT(3) 309 #define SVM_SEV_FEAT_ALTERNATE_INJECTION BIT(4) 310 #define SVM_SEV_FEAT_DEBUG_SWAP BIT(5) 311 #define SVM_SEV_FEAT_SECURE_TSC BIT(9) 312 313 #define VMCB_ALLOWED_SEV_FEATURES_VALID BIT_ULL(63) 314 315 struct vmcb_seg { 316 u16 selector; 317 u16 attrib; 318 u32 limit; 319 u64 base; 320 } __packed; 321 322 /* Save area definition for legacy and SEV-MEM guests */ 323 struct vmcb_save_area { 324 struct vmcb_seg es; 325 struct vmcb_seg cs; 326 struct vmcb_seg ss; 327 struct vmcb_seg ds; 328 struct vmcb_seg fs; 329 struct vmcb_seg gs; 330 struct vmcb_seg gdtr; 331 struct vmcb_seg ldtr; 332 struct vmcb_seg idtr; 333 struct vmcb_seg tr; 334 /* Reserved fields are named following their struct offset */ 335 u8 reserved_0xa0[42]; 336 u8 vmpl; 337 u8 cpl; 338 u8 reserved_0xcc[4]; 339 u64 efer; 340 u8 reserved_0xd8[112]; 341 u64 cr4; 342 u64 cr3; 343 u64 cr0; 344 u64 dr7; 345 u64 dr6; 346 u64 rflags; 347 u64 rip; 348 u8 reserved_0x180[88]; 349 u64 rsp; 350 u64 s_cet; 351 u64 ssp; 352 u64 isst_addr; 353 u64 rax; 354 u64 star; 355 u64 lstar; 356 u64 cstar; 357 u64 sfmask; 358 u64 kernel_gs_base; 359 u64 sysenter_cs; 360 u64 sysenter_esp; 361 u64 sysenter_eip; 362 u64 cr2; 363 u8 reserved_0x248[32]; 364 u64 g_pat; 365 u64 dbgctl; 366 u64 br_from; 367 u64 br_to; 368 u64 last_excp_from; 369 u64 last_excp_to; 370 u8 reserved_0x298[72]; 371 u64 spec_ctrl; /* Guest version of SPEC_CTRL at 0x2E0 */ 372 } __packed; 373 374 /* Save area definition for SEV-ES and SEV-SNP guests */ 375 struct sev_es_save_area { 376 struct vmcb_seg es; 377 struct vmcb_seg cs; 378 struct vmcb_seg ss; 379 struct vmcb_seg ds; 380 struct vmcb_seg fs; 381 struct vmcb_seg gs; 382 struct vmcb_seg gdtr; 383 struct vmcb_seg ldtr; 384 struct vmcb_seg idtr; 385 struct vmcb_seg tr; 386 u64 pl0_ssp; 387 u64 pl1_ssp; 388 u64 pl2_ssp; 389 u64 pl3_ssp; 390 u64 u_cet; 391 u8 reserved_0xc8[2]; 392 u8 vmpl; 393 u8 cpl; 394 u8 reserved_0xcc[4]; 395 u64 efer; 396 u8 reserved_0xd8[104]; 397 u64 xss; 398 u64 cr4; 399 u64 cr3; 400 u64 cr0; 401 u64 dr7; 402 u64 dr6; 403 u64 rflags; 404 u64 rip; 405 u64 dr0; 406 u64 dr1; 407 u64 dr2; 408 u64 dr3; 409 u64 dr0_addr_mask; 410 u64 dr1_addr_mask; 411 u64 dr2_addr_mask; 412 u64 dr3_addr_mask; 413 u8 reserved_0x1c0[24]; 414 u64 rsp; 415 u64 s_cet; 416 u64 ssp; 417 u64 isst_addr; 418 u64 rax; 419 u64 star; 420 u64 lstar; 421 u64 cstar; 422 u64 sfmask; 423 u64 kernel_gs_base; 424 u64 sysenter_cs; 425 u64 sysenter_esp; 426 u64 sysenter_eip; 427 u64 cr2; 428 u8 reserved_0x248[32]; 429 u64 g_pat; 430 u64 dbgctl; 431 u64 br_from; 432 u64 br_to; 433 u64 last_excp_from; 434 u64 last_excp_to; 435 u8 reserved_0x298[80]; 436 u32 pkru; 437 u32 tsc_aux; 438 u64 tsc_scale; 439 u64 tsc_offset; 440 u8 reserved_0x300[8]; 441 u64 rcx; 442 u64 rdx; 443 u64 rbx; 444 u64 reserved_0x320; /* rsp already available at 0x01d8 */ 445 u64 rbp; 446 u64 rsi; 447 u64 rdi; 448 u64 r8; 449 u64 r9; 450 u64 r10; 451 u64 r11; 452 u64 r12; 453 u64 r13; 454 u64 r14; 455 u64 r15; 456 u8 reserved_0x380[16]; 457 u64 guest_exit_info_1; 458 u64 guest_exit_info_2; 459 u64 guest_exit_int_info; 460 u64 guest_nrip; 461 u64 sev_features; 462 u64 vintr_ctrl; 463 u64 guest_exit_code; 464 u64 virtual_tom; 465 u64 tlb_id; 466 u64 pcpu_id; 467 u64 event_inj; 468 u64 xcr0; 469 u8 reserved_0x3f0[16]; 470 471 /* Floating point area */ 472 u64 x87_dp; 473 u32 mxcsr; 474 u16 x87_ftw; 475 u16 x87_fsw; 476 u16 x87_fcw; 477 u16 x87_fop; 478 u16 x87_ds; 479 u16 x87_cs; 480 u64 x87_rip; 481 u8 fpreg_x87[80]; 482 u8 fpreg_xmm[256]; 483 u8 fpreg_ymm[256]; 484 } __packed; 485 486 struct ghcb_save_area { 487 u8 reserved_0x0[203]; 488 u8 cpl; 489 u8 reserved_0xcc[116]; 490 u64 xss; 491 u8 reserved_0x148[24]; 492 u64 dr7; 493 u8 reserved_0x168[16]; 494 u64 rip; 495 u8 reserved_0x180[88]; 496 u64 rsp; 497 u8 reserved_0x1e0[24]; 498 u64 rax; 499 u8 reserved_0x200[264]; 500 u64 rcx; 501 u64 rdx; 502 u64 rbx; 503 u8 reserved_0x320[8]; 504 u64 rbp; 505 u64 rsi; 506 u64 rdi; 507 u64 r8; 508 u64 r9; 509 u64 r10; 510 u64 r11; 511 u64 r12; 512 u64 r13; 513 u64 r14; 514 u64 r15; 515 u8 reserved_0x380[16]; 516 u64 sw_exit_code; 517 u64 sw_exit_info_1; 518 u64 sw_exit_info_2; 519 u64 sw_scratch; 520 u8 reserved_0x3b0[56]; 521 u64 xcr0; 522 u8 valid_bitmap[16]; 523 u64 x87_state_gpa; 524 } __packed; 525 526 #define GHCB_SHARED_BUF_SIZE 2032 527 528 struct ghcb { 529 struct ghcb_save_area save; 530 u8 reserved_save[2048 - sizeof(struct ghcb_save_area)]; 531 532 u8 shared_buffer[GHCB_SHARED_BUF_SIZE]; 533 534 u8 reserved_0xff0[10]; 535 u16 protocol_version; /* negotiated SEV-ES/GHCB protocol version */ 536 u32 ghcb_usage; 537 } __packed; 538 539 struct vmcb { 540 struct vmcb_control_area control; 541 union { 542 struct vmcb_save_area save; 543 544 /* 545 * For SEV-ES VMs, the save area in the VMCB is used only to 546 * save/load host state. Guest state resides in a separate 547 * page, the aptly named VM Save Area (VMSA), that is encrypted 548 * with the guest's private key. 549 */ 550 struct sev_es_save_area host_sev_es_save; 551 }; 552 } __packed; 553 554 #define EXPECTED_VMCB_SAVE_AREA_SIZE 744 555 #define EXPECTED_GHCB_SAVE_AREA_SIZE 1032 556 #define EXPECTED_SEV_ES_SAVE_AREA_SIZE 1648 557 #define EXPECTED_VMCB_CONTROL_AREA_SIZE 1024 558 #define EXPECTED_GHCB_SIZE PAGE_SIZE 559 560 #define BUILD_BUG_RESERVED_OFFSET(x, y) \ 561 ASSERT_STRUCT_OFFSET(struct x, reserved ## _ ## y, y) 562 563 static inline void __unused_size_checks(void) 564 { 565 BUILD_BUG_ON(sizeof(struct vmcb_save_area) != EXPECTED_VMCB_SAVE_AREA_SIZE); 566 BUILD_BUG_ON(sizeof(struct ghcb_save_area) != EXPECTED_GHCB_SAVE_AREA_SIZE); 567 BUILD_BUG_ON(sizeof(struct sev_es_save_area) != EXPECTED_SEV_ES_SAVE_AREA_SIZE); 568 BUILD_BUG_ON(sizeof(struct vmcb_control_area) != EXPECTED_VMCB_CONTROL_AREA_SIZE); 569 BUILD_BUG_ON(offsetof(struct vmcb, save) != EXPECTED_VMCB_CONTROL_AREA_SIZE); 570 BUILD_BUG_ON(sizeof(struct ghcb) != EXPECTED_GHCB_SIZE); 571 572 /* Check offsets of reserved fields */ 573 574 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0xa0); 575 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0xcc); 576 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0xd8); 577 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0x180); 578 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0x248); 579 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0x298); 580 581 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0xc8); 582 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0xcc); 583 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0xd8); 584 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x1c0); 585 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x248); 586 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x298); 587 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x300); 588 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x320); 589 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x380); 590 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x3f0); 591 592 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x0); 593 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0xcc); 594 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x148); 595 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x168); 596 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x180); 597 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x1e0); 598 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x200); 599 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x320); 600 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x380); 601 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x3b0); 602 603 BUILD_BUG_RESERVED_OFFSET(ghcb, 0xff0); 604 } 605 606 #define SVM_CPUID_FUNC 0x8000000a 607 608 #define SVM_SELECTOR_S_SHIFT 4 609 #define SVM_SELECTOR_DPL_SHIFT 5 610 #define SVM_SELECTOR_P_SHIFT 7 611 #define SVM_SELECTOR_AVL_SHIFT 8 612 #define SVM_SELECTOR_L_SHIFT 9 613 #define SVM_SELECTOR_DB_SHIFT 10 614 #define SVM_SELECTOR_G_SHIFT 11 615 616 #define SVM_SELECTOR_TYPE_MASK (0xf) 617 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT) 618 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT) 619 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT) 620 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT) 621 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT) 622 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT) 623 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT) 624 625 #define SVM_SELECTOR_WRITE_MASK (1 << 1) 626 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK 627 #define SVM_SELECTOR_CODE_MASK (1 << 3) 628 629 #define SVM_EVTINJ_VEC_MASK 0xff 630 631 #define SVM_EVTINJ_TYPE_SHIFT 8 632 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT) 633 634 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT) 635 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT) 636 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT) 637 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT) 638 639 #define SVM_EVTINJ_VALID (1 << 31) 640 #define SVM_EVTINJ_VALID_ERR (1 << 11) 641 642 #define SVM_EVTINJ_RESERVED_BITS ~(SVM_EVTINJ_VEC_MASK | SVM_EVTINJ_TYPE_MASK | \ 643 SVM_EVTINJ_VALID_ERR | SVM_EVTINJ_VALID) 644 645 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK 646 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK 647 648 #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR 649 #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI 650 #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT 651 #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT 652 653 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID 654 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR 655 656 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36 657 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38 658 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44 659 660 #define SVM_EXITINFO_REG_MASK 0x0F 661 662 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP) 663 664 /* GHCB Accessor functions */ 665 666 #define GHCB_BITMAP_IDX(field) \ 667 (offsetof(struct ghcb_save_area, field) / sizeof(u64)) 668 669 #define DEFINE_GHCB_ACCESSORS(field) \ 670 static __always_inline bool ghcb_##field##_is_valid(const struct ghcb *ghcb) \ 671 { \ 672 return test_bit(GHCB_BITMAP_IDX(field), \ 673 (unsigned long *)&ghcb->save.valid_bitmap); \ 674 } \ 675 \ 676 static __always_inline u64 ghcb_get_##field(struct ghcb *ghcb) \ 677 { \ 678 return ghcb->save.field; \ 679 } \ 680 \ 681 static __always_inline u64 ghcb_get_##field##_if_valid(struct ghcb *ghcb) \ 682 { \ 683 return ghcb_##field##_is_valid(ghcb) ? ghcb->save.field : 0; \ 684 } \ 685 \ 686 static __always_inline void ghcb_set_##field(struct ghcb *ghcb, u64 value) \ 687 { \ 688 __set_bit(GHCB_BITMAP_IDX(field), \ 689 (unsigned long *)&ghcb->save.valid_bitmap); \ 690 ghcb->save.field = value; \ 691 } 692 693 DEFINE_GHCB_ACCESSORS(cpl) 694 DEFINE_GHCB_ACCESSORS(rip) 695 DEFINE_GHCB_ACCESSORS(rsp) 696 DEFINE_GHCB_ACCESSORS(rax) 697 DEFINE_GHCB_ACCESSORS(rcx) 698 DEFINE_GHCB_ACCESSORS(rdx) 699 DEFINE_GHCB_ACCESSORS(rbx) 700 DEFINE_GHCB_ACCESSORS(rbp) 701 DEFINE_GHCB_ACCESSORS(rsi) 702 DEFINE_GHCB_ACCESSORS(rdi) 703 DEFINE_GHCB_ACCESSORS(r8) 704 DEFINE_GHCB_ACCESSORS(r9) 705 DEFINE_GHCB_ACCESSORS(r10) 706 DEFINE_GHCB_ACCESSORS(r11) 707 DEFINE_GHCB_ACCESSORS(r12) 708 DEFINE_GHCB_ACCESSORS(r13) 709 DEFINE_GHCB_ACCESSORS(r14) 710 DEFINE_GHCB_ACCESSORS(r15) 711 DEFINE_GHCB_ACCESSORS(sw_exit_code) 712 DEFINE_GHCB_ACCESSORS(sw_exit_info_1) 713 DEFINE_GHCB_ACCESSORS(sw_exit_info_2) 714 DEFINE_GHCB_ACCESSORS(sw_scratch) 715 DEFINE_GHCB_ACCESSORS(xcr0) 716 DEFINE_GHCB_ACCESSORS(xss) 717 718 #endif 719