1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_SPECCTRL_H_ 3 #define _ASM_X86_SPECCTRL_H_ 4 5 #include <linux/thread_info.h> 6 #include <asm/nospec-branch.h> 7 #include <asm/msr.h> 8 9 /* 10 * On VMENTER we must preserve whatever view of the SPEC_CTRL MSR 11 * the guest has, while on VMEXIT we restore the host view. This 12 * would be easier if SPEC_CTRL were architecturally maskable or 13 * shadowable for guests but this is not (currently) the case. 14 * Takes the guest view of SPEC_CTRL MSR as a parameter and also 15 * the guest's version of VIRT_SPEC_CTRL, if emulated. 16 */ 17 extern void x86_virt_spec_ctrl(u64 guest_virt_spec_ctrl, bool guest); 18 19 /** 20 * x86_spec_ctrl_set_guest - Set speculation control registers for the guest 21 * @guest_virt_spec_ctrl: The guest controlled bits of MSR_VIRT_SPEC_CTRL 22 * (may get translated to MSR_AMD64_LS_CFG bits) 23 * 24 * Avoids writing to the MSR if the content/bits are the same 25 */ 26 static inline 27 void x86_spec_ctrl_set_guest(u64 guest_virt_spec_ctrl) 28 { 29 x86_virt_spec_ctrl(guest_virt_spec_ctrl, true); 30 } 31 32 /** 33 * x86_spec_ctrl_restore_host - Restore host speculation control registers 34 * @guest_virt_spec_ctrl: The guest controlled bits of MSR_VIRT_SPEC_CTRL 35 * (may get translated to MSR_AMD64_LS_CFG bits) 36 * 37 * Avoids writing to the MSR if the content/bits are the same 38 */ 39 static inline 40 void x86_spec_ctrl_restore_host(u64 guest_virt_spec_ctrl) 41 { 42 x86_virt_spec_ctrl(guest_virt_spec_ctrl, false); 43 } 44 45 /* AMD specific Speculative Store Bypass MSR data */ 46 extern u64 x86_amd_ls_cfg_base; 47 extern u64 x86_amd_ls_cfg_ssbd_mask; 48 49 static inline u64 ssbd_tif_to_spec_ctrl(u64 tifn) 50 { 51 BUILD_BUG_ON(TIF_SSBD < SPEC_CTRL_SSBD_SHIFT); 52 return (tifn & _TIF_SSBD) >> (TIF_SSBD - SPEC_CTRL_SSBD_SHIFT); 53 } 54 55 static inline u64 stibp_tif_to_spec_ctrl(u64 tifn) 56 { 57 BUILD_BUG_ON(TIF_SPEC_IB < SPEC_CTRL_STIBP_SHIFT); 58 return (tifn & _TIF_SPEC_IB) >> (TIF_SPEC_IB - SPEC_CTRL_STIBP_SHIFT); 59 } 60 61 static inline unsigned long ssbd_spec_ctrl_to_tif(u64 spec_ctrl) 62 { 63 BUILD_BUG_ON(TIF_SSBD < SPEC_CTRL_SSBD_SHIFT); 64 return (spec_ctrl & SPEC_CTRL_SSBD) << (TIF_SSBD - SPEC_CTRL_SSBD_SHIFT); 65 } 66 67 static inline unsigned long stibp_spec_ctrl_to_tif(u64 spec_ctrl) 68 { 69 BUILD_BUG_ON(TIF_SPEC_IB < SPEC_CTRL_STIBP_SHIFT); 70 return (spec_ctrl & SPEC_CTRL_STIBP) << (TIF_SPEC_IB - SPEC_CTRL_STIBP_SHIFT); 71 } 72 73 static inline u64 ssbd_tif_to_amd_ls_cfg(u64 tifn) 74 { 75 return (tifn & _TIF_SSBD) ? x86_amd_ls_cfg_ssbd_mask : 0ULL; 76 } 77 78 /* 79 * This can be used in noinstr functions & should only be called in bare 80 * metal context. 81 */ 82 static __always_inline void __update_spec_ctrl(u64 val) 83 { 84 __this_cpu_write(x86_spec_ctrl_current, val); 85 native_wrmsrq(MSR_IA32_SPEC_CTRL, val); 86 } 87 88 #ifdef CONFIG_SMP 89 extern void speculative_store_bypass_ht_init(void); 90 #else 91 static inline void speculative_store_bypass_ht_init(void) { } 92 #endif 93 94 extern void speculation_ctrl_update(unsigned long tif); 95 extern void speculation_ctrl_update_current(void); 96 97 extern bool itlb_multihit_kvm_mitigation; 98 99 #endif 100