1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * AMD SEV header common between the guest and the hypervisor. 4 * 5 * Author: Brijesh Singh <brijesh.singh@amd.com> 6 */ 7 8 #ifndef __ASM_X86_SEV_COMMON_H 9 #define __ASM_X86_SEV_COMMON_H 10 11 #define GHCB_MSR_INFO_POS 0 12 #define GHCB_DATA_LOW 12 13 #define GHCB_MSR_INFO_MASK (BIT_ULL(GHCB_DATA_LOW) - 1) 14 15 #define GHCB_DATA(v) \ 16 (((unsigned long)(v) & ~GHCB_MSR_INFO_MASK) >> GHCB_DATA_LOW) 17 18 /* SEV Information Request/Response */ 19 #define GHCB_MSR_SEV_INFO_RESP 0x001 20 #define GHCB_MSR_SEV_INFO_REQ 0x002 21 22 #define GHCB_MSR_SEV_INFO(_max, _min, _cbit) \ 23 /* GHCBData[63:48] */ \ 24 ((((_max) & 0xffff) << 48) | \ 25 /* GHCBData[47:32] */ \ 26 (((_min) & 0xffff) << 32) | \ 27 /* GHCBData[31:24] */ \ 28 (((_cbit) & 0xff) << 24) | \ 29 GHCB_MSR_SEV_INFO_RESP) 30 31 #define GHCB_MSR_INFO(v) ((v) & 0xfffUL) 32 #define GHCB_MSR_PROTO_MAX(v) (((v) >> 48) & 0xffff) 33 #define GHCB_MSR_PROTO_MIN(v) (((v) >> 32) & 0xffff) 34 35 /* CPUID Request/Response */ 36 #define GHCB_MSR_CPUID_REQ 0x004 37 #define GHCB_MSR_CPUID_RESP 0x005 38 #define GHCB_MSR_CPUID_FUNC_POS 32 39 #define GHCB_MSR_CPUID_FUNC_MASK 0xffffffff 40 #define GHCB_MSR_CPUID_VALUE_POS 32 41 #define GHCB_MSR_CPUID_VALUE_MASK 0xffffffff 42 #define GHCB_MSR_CPUID_REG_POS 30 43 #define GHCB_MSR_CPUID_REG_MASK 0x3 44 #define GHCB_CPUID_REQ_EAX 0 45 #define GHCB_CPUID_REQ_EBX 1 46 #define GHCB_CPUID_REQ_ECX 2 47 #define GHCB_CPUID_REQ_EDX 3 48 #define GHCB_CPUID_REQ(fn, reg) \ 49 /* GHCBData[11:0] */ \ 50 (GHCB_MSR_CPUID_REQ | \ 51 /* GHCBData[31:12] */ \ 52 (((unsigned long)(reg) & 0x3) << 30) | \ 53 /* GHCBData[63:32] */ \ 54 (((unsigned long)fn) << 32)) 55 56 /* AP Reset Hold */ 57 #define GHCB_MSR_AP_RESET_HOLD_REQ 0x006 58 #define GHCB_MSR_AP_RESET_HOLD_RESP 0x007 59 #define GHCB_MSR_AP_RESET_HOLD_RESULT_POS 12 60 #define GHCB_MSR_AP_RESET_HOLD_RESULT_MASK GENMASK_ULL(51, 0) 61 62 /* GHCB GPA Register */ 63 #define GHCB_MSR_REG_GPA_REQ 0x012 64 #define GHCB_MSR_REG_GPA_REQ_VAL(v) \ 65 /* GHCBData[63:12] */ \ 66 (((u64)((v) & GENMASK_ULL(51, 0)) << 12) | \ 67 /* GHCBData[11:0] */ \ 68 GHCB_MSR_REG_GPA_REQ) 69 70 #define GHCB_MSR_REG_GPA_RESP 0x013 71 #define GHCB_MSR_REG_GPA_RESP_VAL(v) \ 72 /* GHCBData[63:12] */ \ 73 (((u64)(v) & GENMASK_ULL(63, 12)) >> 12) 74 75 /* 76 * SNP Page State Change Operation 77 * 78 * GHCBData[55:52] - Page operation: 79 * 0x0001 Page assignment, Private 80 * 0x0002 Page assignment, Shared 81 */ 82 enum psc_op { 83 SNP_PAGE_STATE_PRIVATE = 1, 84 SNP_PAGE_STATE_SHARED, 85 }; 86 87 #define GHCB_MSR_PSC_REQ 0x014 88 #define GHCB_MSR_PSC_REQ_GFN(gfn, op) \ 89 /* GHCBData[55:52] */ \ 90 (((u64)((op) & 0xf) << 52) | \ 91 /* GHCBData[51:12] */ \ 92 ((u64)((gfn) & GENMASK_ULL(39, 0)) << 12) | \ 93 /* GHCBData[11:0] */ \ 94 GHCB_MSR_PSC_REQ) 95 96 #define GHCB_MSR_PSC_RESP 0x015 97 #define GHCB_MSR_PSC_RESP_VAL(val) \ 98 /* GHCBData[63:32] */ \ 99 (((u64)(val) & GENMASK_ULL(63, 32)) >> 32) 100 101 /* GHCB Run at VMPL Request/Response */ 102 #define GHCB_MSR_VMPL_REQ 0x016 103 #define GHCB_MSR_VMPL_REQ_LEVEL(v) \ 104 /* GHCBData[39:32] */ \ 105 (((u64)(v) & GENMASK_ULL(7, 0) << 32) | \ 106 /* GHCBDdata[11:0] */ \ 107 GHCB_MSR_VMPL_REQ) 108 109 #define GHCB_MSR_VMPL_RESP 0x017 110 #define GHCB_MSR_VMPL_RESP_VAL(v) \ 111 /* GHCBData[63:32] */ \ 112 (((u64)(v) & GENMASK_ULL(63, 32)) >> 32) 113 114 /* GHCB Hypervisor Feature Request/Response */ 115 #define GHCB_MSR_HV_FT_REQ 0x080 116 #define GHCB_MSR_HV_FT_RESP 0x081 117 #define GHCB_MSR_HV_FT_POS 12 118 #define GHCB_MSR_HV_FT_MASK GENMASK_ULL(51, 0) 119 #define GHCB_MSR_HV_FT_RESP_VAL(v) \ 120 /* GHCBData[63:12] */ \ 121 (((u64)(v) & GENMASK_ULL(63, 12)) >> 12) 122 123 #define GHCB_HV_FT_SNP BIT_ULL(0) 124 #define GHCB_HV_FT_SNP_AP_CREATION BIT_ULL(1) 125 #define GHCB_HV_FT_SNP_MULTI_VMPL BIT_ULL(5) 126 127 /* 128 * SNP Page State Change NAE event 129 * The VMGEXIT_PSC_MAX_ENTRY determines the size of the PSC structure, which 130 * is a local stack variable in set_pages_state(). Do not increase this value 131 * without evaluating the impact to stack usage. 132 */ 133 #define VMGEXIT_PSC_MAX_ENTRY 64 134 135 struct psc_hdr { 136 u16 cur_entry; 137 u16 end_entry; 138 u32 reserved; 139 } __packed; 140 141 struct psc_entry { 142 u64 cur_page : 12, 143 gfn : 40, 144 operation : 4, 145 pagesize : 1, 146 reserved : 7; 147 } __packed; 148 149 struct snp_psc_desc { 150 struct psc_hdr hdr; 151 struct psc_entry entries[VMGEXIT_PSC_MAX_ENTRY]; 152 } __packed; 153 154 #define GHCB_MSR_TERM_REQ 0x100 155 #define GHCB_MSR_TERM_REASON_SET_POS 12 156 #define GHCB_MSR_TERM_REASON_SET_MASK 0xf 157 #define GHCB_MSR_TERM_REASON_POS 16 158 #define GHCB_MSR_TERM_REASON_MASK 0xff 159 160 #define GHCB_SEV_TERM_REASON(reason_set, reason_val) \ 161 /* GHCBData[15:12] */ \ 162 (((((u64)reason_set) & 0xf) << 12) | \ 163 /* GHCBData[23:16] */ \ 164 ((((u64)reason_val) & 0xff) << 16)) 165 166 /* Error codes from reason set 0 */ 167 #define SEV_TERM_SET_GEN 0 168 #define GHCB_SEV_ES_GEN_REQ 0 169 #define GHCB_SEV_ES_PROT_UNSUPPORTED 1 170 #define GHCB_SNP_UNSUPPORTED 2 171 172 /* Linux-specific reason codes (used with reason set 1) */ 173 #define SEV_TERM_SET_LINUX 1 174 #define GHCB_TERM_REGISTER 0 /* GHCB GPA registration failure */ 175 #define GHCB_TERM_PSC 1 /* Page State Change failure */ 176 #define GHCB_TERM_PVALIDATE 2 /* Pvalidate failure */ 177 #define GHCB_TERM_NOT_VMPL0 3 /* SNP guest is not running at VMPL-0 */ 178 #define GHCB_TERM_CPUID 4 /* CPUID-validation failure */ 179 #define GHCB_TERM_CPUID_HV 5 /* CPUID failure during hypervisor fallback */ 180 #define GHCB_TERM_SECRETS_PAGE 6 /* Secrets page failure */ 181 #define GHCB_TERM_NO_SVSM 7 /* SVSM is not advertised in the secrets page */ 182 #define GHCB_TERM_SVSM_VMPL0 8 /* SVSM is present but has set VMPL to 0 */ 183 #define GHCB_TERM_SVSM_CAA 9 /* SVSM is present but CAA is not page aligned */ 184 185 #define GHCB_RESP_CODE(v) ((v) & GHCB_MSR_INFO_MASK) 186 187 /* 188 * Error codes related to GHCB input that can be communicated back to the guest 189 * by setting the lower 32-bits of the GHCB SW_EXITINFO1 field to 2. 190 */ 191 #define GHCB_ERR_NOT_REGISTERED 1 192 #define GHCB_ERR_INVALID_USAGE 2 193 #define GHCB_ERR_INVALID_SCRATCH_AREA 3 194 #define GHCB_ERR_MISSING_INPUT 4 195 #define GHCB_ERR_INVALID_INPUT 5 196 #define GHCB_ERR_INVALID_EVENT 6 197 198 #endif 199