1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * AMD SEV header common between the guest and the hypervisor. 4 * 5 * Author: Brijesh Singh <brijesh.singh@amd.com> 6 */ 7 8 #ifndef __ASM_X86_SEV_COMMON_H 9 #define __ASM_X86_SEV_COMMON_H 10 11 #define GHCB_MSR_INFO_POS 0 12 #define GHCB_DATA_LOW 12 13 #define GHCB_MSR_INFO_MASK (BIT_ULL(GHCB_DATA_LOW) - 1) 14 15 #define GHCB_DATA(v) \ 16 (((unsigned long)(v) & ~GHCB_MSR_INFO_MASK) >> GHCB_DATA_LOW) 17 18 /* SEV Information Request/Response */ 19 #define GHCB_MSR_SEV_INFO_RESP 0x001 20 #define GHCB_MSR_SEV_INFO_REQ 0x002 21 22 #define GHCB_MSR_SEV_INFO(_max, _min, _cbit) \ 23 /* GHCBData[63:48] */ \ 24 ((((_max) & 0xffff) << 48) | \ 25 /* GHCBData[47:32] */ \ 26 (((_min) & 0xffff) << 32) | \ 27 /* GHCBData[31:24] */ \ 28 (((_cbit) & 0xff) << 24) | \ 29 GHCB_MSR_SEV_INFO_RESP) 30 31 #define GHCB_MSR_INFO(v) ((v) & 0xfffUL) 32 #define GHCB_MSR_PROTO_MAX(v) (((v) >> 48) & 0xffff) 33 #define GHCB_MSR_PROTO_MIN(v) (((v) >> 32) & 0xffff) 34 35 /* CPUID Request/Response */ 36 #define GHCB_MSR_CPUID_REQ 0x004 37 #define GHCB_MSR_CPUID_RESP 0x005 38 #define GHCB_MSR_CPUID_FUNC_POS 32 39 #define GHCB_MSR_CPUID_FUNC_MASK 0xffffffff 40 #define GHCB_MSR_CPUID_VALUE_POS 32 41 #define GHCB_MSR_CPUID_VALUE_MASK 0xffffffff 42 #define GHCB_MSR_CPUID_REG_POS 30 43 #define GHCB_MSR_CPUID_REG_MASK 0x3 44 #define GHCB_CPUID_REQ_EAX 0 45 #define GHCB_CPUID_REQ_EBX 1 46 #define GHCB_CPUID_REQ_ECX 2 47 #define GHCB_CPUID_REQ_EDX 3 48 #define GHCB_CPUID_REQ(fn, reg) \ 49 /* GHCBData[11:0] */ \ 50 (GHCB_MSR_CPUID_REQ | \ 51 /* GHCBData[31:12] */ \ 52 (((unsigned long)(reg) & 0x3) << 30) | \ 53 /* GHCBData[63:32] */ \ 54 (((unsigned long)fn) << 32)) 55 56 /* AP Reset Hold */ 57 #define GHCB_MSR_AP_RESET_HOLD_REQ 0x006 58 #define GHCB_MSR_AP_RESET_HOLD_RESP 0x007 59 #define GHCB_MSR_AP_RESET_HOLD_RESULT_POS 12 60 #define GHCB_MSR_AP_RESET_HOLD_RESULT_MASK GENMASK_ULL(51, 0) 61 62 /* Preferred GHCB GPA Request */ 63 #define GHCB_MSR_PREF_GPA_REQ 0x010 64 #define GHCB_MSR_GPA_VALUE_POS 12 65 #define GHCB_MSR_GPA_VALUE_MASK GENMASK_ULL(51, 0) 66 67 #define GHCB_MSR_PREF_GPA_RESP 0x011 68 #define GHCB_MSR_PREF_GPA_NONE 0xfffffffffffff 69 70 /* GHCB GPA Register */ 71 #define GHCB_MSR_REG_GPA_REQ 0x012 72 #define GHCB_MSR_REG_GPA_REQ_VAL(v) \ 73 /* GHCBData[63:12] */ \ 74 (((u64)((v) & GENMASK_ULL(51, 0)) << 12) | \ 75 /* GHCBData[11:0] */ \ 76 GHCB_MSR_REG_GPA_REQ) 77 78 #define GHCB_MSR_REG_GPA_RESP 0x013 79 #define GHCB_MSR_REG_GPA_RESP_VAL(v) \ 80 /* GHCBData[63:12] */ \ 81 (((u64)(v) & GENMASK_ULL(63, 12)) >> 12) 82 83 /* 84 * SNP Page State Change Operation 85 * 86 * GHCBData[55:52] - Page operation: 87 * 0x0001 Page assignment, Private 88 * 0x0002 Page assignment, Shared 89 */ 90 enum psc_op { 91 SNP_PAGE_STATE_PRIVATE = 1, 92 SNP_PAGE_STATE_SHARED, 93 }; 94 95 #define GHCB_MSR_PSC_REQ 0x014 96 #define GHCB_MSR_PSC_REQ_GFN(gfn, op) \ 97 /* GHCBData[55:52] */ \ 98 (((u64)((op) & 0xf) << 52) | \ 99 /* GHCBData[51:12] */ \ 100 ((u64)((gfn) & GENMASK_ULL(39, 0)) << 12) | \ 101 /* GHCBData[11:0] */ \ 102 GHCB_MSR_PSC_REQ) 103 104 #define GHCB_MSR_PSC_REQ_TO_GFN(msr) (((msr) & GENMASK_ULL(51, 12)) >> 12) 105 #define GHCB_MSR_PSC_REQ_TO_OP(msr) (((msr) & GENMASK_ULL(55, 52)) >> 52) 106 107 #define GHCB_MSR_PSC_RESP 0x015 108 #define GHCB_MSR_PSC_RESP_VAL(val) \ 109 /* GHCBData[63:32] */ \ 110 (((u64)(val) & GENMASK_ULL(63, 32)) >> 32) 111 112 /* Set highest bit as a generic error response */ 113 #define GHCB_MSR_PSC_RESP_ERROR (BIT_ULL(63) | GHCB_MSR_PSC_RESP) 114 115 /* GHCB Hypervisor Feature Request/Response */ 116 #define GHCB_MSR_HV_FT_REQ 0x080 117 #define GHCB_MSR_HV_FT_RESP 0x081 118 #define GHCB_MSR_HV_FT_POS 12 119 #define GHCB_MSR_HV_FT_MASK GENMASK_ULL(51, 0) 120 #define GHCB_MSR_HV_FT_RESP_VAL(v) \ 121 /* GHCBData[63:12] */ \ 122 (((u64)(v) & GENMASK_ULL(63, 12)) >> 12) 123 124 #define GHCB_HV_FT_SNP BIT_ULL(0) 125 #define GHCB_HV_FT_SNP_AP_CREATION BIT_ULL(1) 126 127 /* 128 * SNP Page State Change NAE event 129 * The VMGEXIT_PSC_MAX_ENTRY determines the size of the PSC structure, which 130 * is a local stack variable in set_pages_state(). Do not increase this value 131 * without evaluating the impact to stack usage. 132 * 133 * Use VMGEXIT_PSC_MAX_COUNT in cases where the actual GHCB-defined max value 134 * is needed, such as when processing GHCB requests on the hypervisor side. 135 */ 136 #define VMGEXIT_PSC_MAX_ENTRY 64 137 #define VMGEXIT_PSC_MAX_COUNT 253 138 139 #define VMGEXIT_PSC_ERROR_GENERIC (0x100UL << 32) 140 #define VMGEXIT_PSC_ERROR_INVALID_HDR ((1UL << 32) | 1) 141 #define VMGEXIT_PSC_ERROR_INVALID_ENTRY ((1UL << 32) | 2) 142 143 #define VMGEXIT_PSC_OP_PRIVATE 1 144 #define VMGEXIT_PSC_OP_SHARED 2 145 146 struct psc_hdr { 147 u16 cur_entry; 148 u16 end_entry; 149 u32 reserved; 150 } __packed; 151 152 struct psc_entry { 153 u64 cur_page : 12, 154 gfn : 40, 155 operation : 4, 156 pagesize : 1, 157 reserved : 7; 158 } __packed; 159 160 struct snp_psc_desc { 161 struct psc_hdr hdr; 162 struct psc_entry entries[VMGEXIT_PSC_MAX_ENTRY]; 163 } __packed; 164 165 #define GHCB_MSR_TERM_REQ 0x100 166 #define GHCB_MSR_TERM_REASON_SET_POS 12 167 #define GHCB_MSR_TERM_REASON_SET_MASK 0xf 168 #define GHCB_MSR_TERM_REASON_POS 16 169 #define GHCB_MSR_TERM_REASON_MASK 0xff 170 171 #define GHCB_SEV_TERM_REASON(reason_set, reason_val) \ 172 /* GHCBData[15:12] */ \ 173 (((((u64)reason_set) & 0xf) << 12) | \ 174 /* GHCBData[23:16] */ \ 175 ((((u64)reason_val) & 0xff) << 16)) 176 177 /* Error codes from reason set 0 */ 178 #define SEV_TERM_SET_GEN 0 179 #define GHCB_SEV_ES_GEN_REQ 0 180 #define GHCB_SEV_ES_PROT_UNSUPPORTED 1 181 #define GHCB_SNP_UNSUPPORTED 2 182 183 /* Linux-specific reason codes (used with reason set 1) */ 184 #define SEV_TERM_SET_LINUX 1 185 #define GHCB_TERM_REGISTER 0 /* GHCB GPA registration failure */ 186 #define GHCB_TERM_PSC 1 /* Page State Change failure */ 187 #define GHCB_TERM_PVALIDATE 2 /* Pvalidate failure */ 188 #define GHCB_TERM_NOT_VMPL0 3 /* SNP guest is not running at VMPL-0 */ 189 #define GHCB_TERM_CPUID 4 /* CPUID-validation failure */ 190 #define GHCB_TERM_CPUID_HV 5 /* CPUID failure during hypervisor fallback */ 191 192 #define GHCB_RESP_CODE(v) ((v) & GHCB_MSR_INFO_MASK) 193 194 /* 195 * Error codes related to GHCB input that can be communicated back to the guest 196 * by setting the lower 32-bits of the GHCB SW_EXITINFO1 field to 2. 197 */ 198 #define GHCB_ERR_NOT_REGISTERED 1 199 #define GHCB_ERR_INVALID_USAGE 2 200 #define GHCB_ERR_INVALID_SCRATCH_AREA 3 201 #define GHCB_ERR_MISSING_INPUT 4 202 #define GHCB_ERR_INVALID_INPUT 5 203 #define GHCB_ERR_INVALID_EVENT 6 204 205 #endif 206