11965aae3SH. Peter Anvin #ifndef _ASM_X86_SEGMENT_H 21965aae3SH. Peter Anvin #define _ASM_X86_SEGMENT_H 3bb898558SAl Viro 4bb898558SAl Viro /* Constructor for a conventional segment GDT (or LDT) entry */ 5bb898558SAl Viro /* This is a macro so it can be used in initializers */ 6bb898558SAl Viro #define GDT_ENTRY(flags, base, limit) \ 7bb898558SAl Viro ((((base) & 0xff000000ULL) << (56-24)) | \ 8bb898558SAl Viro (((flags) & 0x0000f0ffULL) << 40) | \ 9bb898558SAl Viro (((limit) & 0x000f0000ULL) << (48-16)) | \ 10bb898558SAl Viro (((base) & 0x00ffffffULL) << 16) | \ 11bb898558SAl Viro (((limit) & 0x0000ffffULL))) 12bb898558SAl Viro 13bb898558SAl Viro /* Simple and small GDT entries for booting only */ 14bb898558SAl Viro 15bb898558SAl Viro #define GDT_ENTRY_BOOT_CS 2 16bb898558SAl Viro #define __BOOT_CS (GDT_ENTRY_BOOT_CS * 8) 17bb898558SAl Viro 18bb898558SAl Viro #define GDT_ENTRY_BOOT_DS (GDT_ENTRY_BOOT_CS + 1) 19bb898558SAl Viro #define __BOOT_DS (GDT_ENTRY_BOOT_DS * 8) 20bb898558SAl Viro 21bb898558SAl Viro #define GDT_ENTRY_BOOT_TSS (GDT_ENTRY_BOOT_CS + 2) 22bb898558SAl Viro #define __BOOT_TSS (GDT_ENTRY_BOOT_TSS * 8) 23bb898558SAl Viro 24bb898558SAl Viro #ifdef CONFIG_X86_32 25bb898558SAl Viro /* 26bb898558SAl Viro * The layout of the per-CPU GDT under Linux: 27bb898558SAl Viro * 28bb898558SAl Viro * 0 - null 29bb898558SAl Viro * 1 - reserved 30bb898558SAl Viro * 2 - reserved 31bb898558SAl Viro * 3 - reserved 32bb898558SAl Viro * 33bb898558SAl Viro * 4 - unused <==== new cacheline 34bb898558SAl Viro * 5 - unused 35bb898558SAl Viro * 36bb898558SAl Viro * ------- start of TLS (Thread-Local Storage) segments: 37bb898558SAl Viro * 38bb898558SAl Viro * 6 - TLS segment #1 [ glibc's TLS segment ] 39bb898558SAl Viro * 7 - TLS segment #2 [ Wine's %fs Win32 segment ] 40bb898558SAl Viro * 8 - TLS segment #3 41bb898558SAl Viro * 9 - reserved 42bb898558SAl Viro * 10 - reserved 43bb898558SAl Viro * 11 - reserved 44bb898558SAl Viro * 45bb898558SAl Viro * ------- start of kernel segments: 46bb898558SAl Viro * 47bb898558SAl Viro * 12 - kernel code segment <==== new cacheline 48bb898558SAl Viro * 13 - kernel data segment 49bb898558SAl Viro * 14 - default user CS 50bb898558SAl Viro * 15 - default user DS 51bb898558SAl Viro * 16 - TSS 52bb898558SAl Viro * 17 - LDT 53bb898558SAl Viro * 18 - PNPBIOS support (16->32 gate) 54bb898558SAl Viro * 19 - PNPBIOS support 55bb898558SAl Viro * 20 - PNPBIOS support 56bb898558SAl Viro * 21 - PNPBIOS support 57bb898558SAl Viro * 22 - PNPBIOS support 58bb898558SAl Viro * 23 - APM BIOS support 59bb898558SAl Viro * 24 - APM BIOS support 60bb898558SAl Viro * 25 - APM BIOS support 61bb898558SAl Viro * 62bb898558SAl Viro * 26 - ESPFIX small SS 63bb898558SAl Viro * 27 - per-cpu [ offset to per-cpu data area ] 64*60a5317fSTejun Heo * 28 - stack_canary-20 [ for stack protector ] 65bb898558SAl Viro * 29 - unused 66bb898558SAl Viro * 30 - unused 67bb898558SAl Viro * 31 - TSS for double fault handler 68bb898558SAl Viro */ 69bb898558SAl Viro #define GDT_ENTRY_TLS_MIN 6 70bb898558SAl Viro #define GDT_ENTRY_TLS_MAX (GDT_ENTRY_TLS_MIN + GDT_ENTRY_TLS_ENTRIES - 1) 71bb898558SAl Viro 72bb898558SAl Viro #define GDT_ENTRY_DEFAULT_USER_CS 14 73bb898558SAl Viro 74bb898558SAl Viro #define GDT_ENTRY_DEFAULT_USER_DS 15 75bb898558SAl Viro 76bb898558SAl Viro #define GDT_ENTRY_KERNEL_BASE 12 77bb898558SAl Viro 78bb898558SAl Viro #define GDT_ENTRY_KERNEL_CS (GDT_ENTRY_KERNEL_BASE + 0) 79bb898558SAl Viro 80bb898558SAl Viro #define GDT_ENTRY_KERNEL_DS (GDT_ENTRY_KERNEL_BASE + 1) 81bb898558SAl Viro 82bb898558SAl Viro #define GDT_ENTRY_TSS (GDT_ENTRY_KERNEL_BASE + 4) 83bb898558SAl Viro #define GDT_ENTRY_LDT (GDT_ENTRY_KERNEL_BASE + 5) 84bb898558SAl Viro 85bb898558SAl Viro #define GDT_ENTRY_PNPBIOS_BASE (GDT_ENTRY_KERNEL_BASE + 6) 86bb898558SAl Viro #define GDT_ENTRY_APMBIOS_BASE (GDT_ENTRY_KERNEL_BASE + 11) 87bb898558SAl Viro 88bb898558SAl Viro #define GDT_ENTRY_ESPFIX_SS (GDT_ENTRY_KERNEL_BASE + 14) 89bb898558SAl Viro #define __ESPFIX_SS (GDT_ENTRY_ESPFIX_SS * 8) 90bb898558SAl Viro 91bb898558SAl Viro #define GDT_ENTRY_PERCPU (GDT_ENTRY_KERNEL_BASE + 15) 92bb898558SAl Viro #ifdef CONFIG_SMP 93bb898558SAl Viro #define __KERNEL_PERCPU (GDT_ENTRY_PERCPU * 8) 94bb898558SAl Viro #else 95bb898558SAl Viro #define __KERNEL_PERCPU 0 96bb898558SAl Viro #endif 97bb898558SAl Viro 98*60a5317fSTejun Heo #define GDT_ENTRY_STACK_CANARY (GDT_ENTRY_KERNEL_BASE + 16) 99*60a5317fSTejun Heo #ifdef CONFIG_CC_STACKPROTECTOR 100*60a5317fSTejun Heo #define __KERNEL_STACK_CANARY (GDT_ENTRY_STACK_CANARY * 8) 101*60a5317fSTejun Heo #else 102*60a5317fSTejun Heo #define __KERNEL_STACK_CANARY 0 103*60a5317fSTejun Heo #endif 104*60a5317fSTejun Heo 105bb898558SAl Viro #define GDT_ENTRY_DOUBLEFAULT_TSS 31 106bb898558SAl Viro 107bb898558SAl Viro /* 108bb898558SAl Viro * The GDT has 32 entries 109bb898558SAl Viro */ 110bb898558SAl Viro #define GDT_ENTRIES 32 111bb898558SAl Viro 112bb898558SAl Viro /* The PnP BIOS entries in the GDT */ 113bb898558SAl Viro #define GDT_ENTRY_PNPBIOS_CS32 (GDT_ENTRY_PNPBIOS_BASE + 0) 114bb898558SAl Viro #define GDT_ENTRY_PNPBIOS_CS16 (GDT_ENTRY_PNPBIOS_BASE + 1) 115bb898558SAl Viro #define GDT_ENTRY_PNPBIOS_DS (GDT_ENTRY_PNPBIOS_BASE + 2) 116bb898558SAl Viro #define GDT_ENTRY_PNPBIOS_TS1 (GDT_ENTRY_PNPBIOS_BASE + 3) 117bb898558SAl Viro #define GDT_ENTRY_PNPBIOS_TS2 (GDT_ENTRY_PNPBIOS_BASE + 4) 118bb898558SAl Viro 119bb898558SAl Viro /* The PnP BIOS selectors */ 120bb898558SAl Viro #define PNP_CS32 (GDT_ENTRY_PNPBIOS_CS32 * 8) /* segment for calling fn */ 121bb898558SAl Viro #define PNP_CS16 (GDT_ENTRY_PNPBIOS_CS16 * 8) /* code segment for BIOS */ 122bb898558SAl Viro #define PNP_DS (GDT_ENTRY_PNPBIOS_DS * 8) /* data segment for BIOS */ 123bb898558SAl Viro #define PNP_TS1 (GDT_ENTRY_PNPBIOS_TS1 * 8) /* transfer data segment */ 124bb898558SAl Viro #define PNP_TS2 (GDT_ENTRY_PNPBIOS_TS2 * 8) /* another data segment */ 125bb898558SAl Viro 126bb898558SAl Viro /* Bottom two bits of selector give the ring privilege level */ 127bb898558SAl Viro #define SEGMENT_RPL_MASK 0x3 128bb898558SAl Viro /* Bit 2 is table indicator (LDT/GDT) */ 129bb898558SAl Viro #define SEGMENT_TI_MASK 0x4 130bb898558SAl Viro 131bb898558SAl Viro /* User mode is privilege level 3 */ 132bb898558SAl Viro #define USER_RPL 0x3 133bb898558SAl Viro /* LDT segment has TI set, GDT has it cleared */ 134bb898558SAl Viro #define SEGMENT_LDT 0x4 135bb898558SAl Viro #define SEGMENT_GDT 0x0 136bb898558SAl Viro 137bb898558SAl Viro /* 138bb898558SAl Viro * Matching rules for certain types of segments. 139bb898558SAl Viro */ 140bb898558SAl Viro 141bb898558SAl Viro /* Matches PNP_CS32 and PNP_CS16 (they must be consecutive) */ 142bb898558SAl Viro #define SEGMENT_IS_PNP_CODE(x) (((x) & 0xf4) == GDT_ENTRY_PNPBIOS_BASE * 8) 143bb898558SAl Viro 144bb898558SAl Viro 145bb898558SAl Viro #else 146bb898558SAl Viro #include <asm/cache.h> 147bb898558SAl Viro 148bb898558SAl Viro #define GDT_ENTRY_KERNEL32_CS 1 149bb898558SAl Viro #define GDT_ENTRY_KERNEL_CS 2 150bb898558SAl Viro #define GDT_ENTRY_KERNEL_DS 3 151bb898558SAl Viro 152bb898558SAl Viro #define __KERNEL32_CS (GDT_ENTRY_KERNEL32_CS * 8) 153bb898558SAl Viro 154bb898558SAl Viro /* 155bb898558SAl Viro * we cannot use the same code segment descriptor for user and kernel 156bb898558SAl Viro * -- not even in the long flat mode, because of different DPL /kkeil 157bb898558SAl Viro * The segment offset needs to contain a RPL. Grr. -AK 158bb898558SAl Viro * GDT layout to get 64bit syscall right (sysret hardcodes gdt offsets) 159bb898558SAl Viro */ 160bb898558SAl Viro #define GDT_ENTRY_DEFAULT_USER32_CS 4 161bb898558SAl Viro #define GDT_ENTRY_DEFAULT_USER_DS 5 162bb898558SAl Viro #define GDT_ENTRY_DEFAULT_USER_CS 6 163bb898558SAl Viro #define __USER32_CS (GDT_ENTRY_DEFAULT_USER32_CS * 8 + 3) 164bb898558SAl Viro #define __USER32_DS __USER_DS 165bb898558SAl Viro 166bb898558SAl Viro #define GDT_ENTRY_TSS 8 /* needs two entries */ 167bb898558SAl Viro #define GDT_ENTRY_LDT 10 /* needs two entries */ 168bb898558SAl Viro #define GDT_ENTRY_TLS_MIN 12 169bb898558SAl Viro #define GDT_ENTRY_TLS_MAX 14 170bb898558SAl Viro 171bb898558SAl Viro #define GDT_ENTRY_PER_CPU 15 /* Abused to load per CPU data from limit */ 172bb898558SAl Viro #define __PER_CPU_SEG (GDT_ENTRY_PER_CPU * 8 + 3) 173bb898558SAl Viro 174bb898558SAl Viro /* TLS indexes for 64bit - hardcoded in arch_prctl */ 175bb898558SAl Viro #define FS_TLS 0 176bb898558SAl Viro #define GS_TLS 1 177bb898558SAl Viro 178bb898558SAl Viro #define GS_TLS_SEL ((GDT_ENTRY_TLS_MIN+GS_TLS)*8 + 3) 179bb898558SAl Viro #define FS_TLS_SEL ((GDT_ENTRY_TLS_MIN+FS_TLS)*8 + 3) 180bb898558SAl Viro 181bb898558SAl Viro #define GDT_ENTRIES 16 182bb898558SAl Viro 183bb898558SAl Viro #endif 184bb898558SAl Viro 185bb898558SAl Viro #define __KERNEL_CS (GDT_ENTRY_KERNEL_CS * 8) 186bb898558SAl Viro #define __KERNEL_DS (GDT_ENTRY_KERNEL_DS * 8) 187bb898558SAl Viro #define __USER_DS (GDT_ENTRY_DEFAULT_USER_DS* 8 + 3) 188bb898558SAl Viro #define __USER_CS (GDT_ENTRY_DEFAULT_USER_CS* 8 + 3) 189bb898558SAl Viro #ifndef CONFIG_PARAVIRT 190bb898558SAl Viro #define get_kernel_rpl() 0 191bb898558SAl Viro #endif 192bb898558SAl Viro 193bb898558SAl Viro /* User mode is privilege level 3 */ 194bb898558SAl Viro #define USER_RPL 0x3 195bb898558SAl Viro /* LDT segment has TI set, GDT has it cleared */ 196bb898558SAl Viro #define SEGMENT_LDT 0x4 197bb898558SAl Viro #define SEGMENT_GDT 0x0 198bb898558SAl Viro 199bb898558SAl Viro /* Bottom two bits of selector give the ring privilege level */ 200bb898558SAl Viro #define SEGMENT_RPL_MASK 0x3 201bb898558SAl Viro /* Bit 2 is table indicator (LDT/GDT) */ 202bb898558SAl Viro #define SEGMENT_TI_MASK 0x4 203bb898558SAl Viro 204bb898558SAl Viro #define IDT_ENTRIES 256 205bb898558SAl Viro #define NUM_EXCEPTION_VECTORS 32 206bb898558SAl Viro #define GDT_SIZE (GDT_ENTRIES * 8) 207bb898558SAl Viro #define GDT_ENTRY_TLS_ENTRIES 3 208bb898558SAl Viro #define TLS_SIZE (GDT_ENTRY_TLS_ENTRIES * 8) 209bb898558SAl Viro 210bb898558SAl Viro #ifdef __KERNEL__ 211bb898558SAl Viro #ifndef __ASSEMBLY__ 212bb898558SAl Viro extern const char early_idt_handlers[NUM_EXCEPTION_VECTORS][10]; 213bb898558SAl Viro #endif 214bb898558SAl Viro #endif 215bb898558SAl Viro 2161965aae3SH. Peter Anvin #endif /* _ASM_X86_SEGMENT_H */ 217