1 #ifndef _ASM_X86_PROCESSOR_H 2 #define _ASM_X86_PROCESSOR_H 3 4 #include <asm/processor-flags.h> 5 6 /* Forward declaration, a strange C thing */ 7 struct task_struct; 8 struct mm_struct; 9 10 #include <asm/vm86.h> 11 #include <asm/math_emu.h> 12 #include <asm/segment.h> 13 #include <asm/types.h> 14 #include <asm/sigcontext.h> 15 #include <asm/current.h> 16 #include <asm/cpufeature.h> 17 #include <asm/page.h> 18 #include <asm/pgtable_types.h> 19 #include <asm/percpu.h> 20 #include <asm/msr.h> 21 #include <asm/desc_defs.h> 22 #include <asm/nops.h> 23 #include <asm/special_insns.h> 24 25 #include <linux/personality.h> 26 #include <linux/cpumask.h> 27 #include <linux/cache.h> 28 #include <linux/threads.h> 29 #include <linux/math64.h> 30 #include <linux/init.h> 31 #include <linux/err.h> 32 #include <linux/irqflags.h> 33 34 /* 35 * We handle most unaligned accesses in hardware. On the other hand 36 * unaligned DMA can be quite expensive on some Nehalem processors. 37 * 38 * Based on this we disable the IP header alignment in network drivers. 39 */ 40 #define NET_IP_ALIGN 0 41 42 #define HBP_NUM 4 43 /* 44 * Default implementation of macro that returns current 45 * instruction pointer ("program counter"). 46 */ 47 static inline void *current_text_addr(void) 48 { 49 void *pc; 50 51 asm volatile("mov $1f, %0; 1:":"=r" (pc)); 52 53 return pc; 54 } 55 56 #ifdef CONFIG_X86_VSMP 57 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 58 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 59 #else 60 # define ARCH_MIN_TASKALIGN 16 61 # define ARCH_MIN_MMSTRUCT_ALIGN 0 62 #endif 63 64 enum tlb_infos { 65 ENTRIES, 66 NR_INFO 67 }; 68 69 extern u16 __read_mostly tlb_lli_4k[NR_INFO]; 70 extern u16 __read_mostly tlb_lli_2m[NR_INFO]; 71 extern u16 __read_mostly tlb_lli_4m[NR_INFO]; 72 extern u16 __read_mostly tlb_lld_4k[NR_INFO]; 73 extern u16 __read_mostly tlb_lld_2m[NR_INFO]; 74 extern u16 __read_mostly tlb_lld_4m[NR_INFO]; 75 extern s8 __read_mostly tlb_flushall_shift; 76 77 /* 78 * CPU type and hardware bug flags. Kept separately for each CPU. 79 * Members of this structure are referenced in head.S, so think twice 80 * before touching them. [mj] 81 */ 82 83 struct cpuinfo_x86 { 84 __u8 x86; /* CPU family */ 85 __u8 x86_vendor; /* CPU vendor */ 86 __u8 x86_model; 87 __u8 x86_mask; 88 #ifdef CONFIG_X86_32 89 char wp_works_ok; /* It doesn't on 386's */ 90 91 /* Problems on some 486Dx4's and old 386's: */ 92 char hard_math; 93 char rfu; 94 char fdiv_bug; 95 char f00f_bug; 96 char coma_bug; 97 char pad0; 98 #else 99 /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 100 int x86_tlbsize; 101 #endif 102 __u8 x86_virt_bits; 103 __u8 x86_phys_bits; 104 /* CPUID returned core id bits: */ 105 __u8 x86_coreid_bits; 106 /* Max extended CPUID function supported: */ 107 __u32 extended_cpuid_level; 108 /* Maximum supported CPUID level, -1=no CPUID: */ 109 int cpuid_level; 110 __u32 x86_capability[NCAPINTS]; 111 char x86_vendor_id[16]; 112 char x86_model_id[64]; 113 /* in KB - valid for CPUS which support this call: */ 114 int x86_cache_size; 115 int x86_cache_alignment; /* In bytes */ 116 int x86_power; 117 unsigned long loops_per_jiffy; 118 /* cpuid returned max cores value: */ 119 u16 x86_max_cores; 120 u16 apicid; 121 u16 initial_apicid; 122 u16 x86_clflush_size; 123 /* number of cores as seen by the OS: */ 124 u16 booted_cores; 125 /* Physical processor id: */ 126 u16 phys_proc_id; 127 /* Core id: */ 128 u16 cpu_core_id; 129 /* Compute unit id */ 130 u8 compute_unit_id; 131 /* Index into per_cpu list: */ 132 u16 cpu_index; 133 u32 microcode; 134 } __attribute__((__aligned__(SMP_CACHE_BYTES))); 135 136 #define X86_VENDOR_INTEL 0 137 #define X86_VENDOR_CYRIX 1 138 #define X86_VENDOR_AMD 2 139 #define X86_VENDOR_UMC 3 140 #define X86_VENDOR_CENTAUR 5 141 #define X86_VENDOR_TRANSMETA 7 142 #define X86_VENDOR_NSC 8 143 #define X86_VENDOR_NUM 9 144 145 #define X86_VENDOR_UNKNOWN 0xff 146 147 /* 148 * capabilities of CPUs 149 */ 150 extern struct cpuinfo_x86 boot_cpu_data; 151 extern struct cpuinfo_x86 new_cpu_data; 152 153 extern struct tss_struct doublefault_tss; 154 extern __u32 cpu_caps_cleared[NCAPINTS]; 155 extern __u32 cpu_caps_set[NCAPINTS]; 156 157 #ifdef CONFIG_SMP 158 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); 159 #define cpu_data(cpu) per_cpu(cpu_info, cpu) 160 #else 161 #define cpu_info boot_cpu_data 162 #define cpu_data(cpu) boot_cpu_data 163 #endif 164 165 extern const struct seq_operations cpuinfo_op; 166 167 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 168 169 extern void cpu_detect(struct cpuinfo_x86 *c); 170 171 extern void early_cpu_init(void); 172 extern void identify_boot_cpu(void); 173 extern void identify_secondary_cpu(struct cpuinfo_x86 *); 174 extern void print_cpu_info(struct cpuinfo_x86 *); 175 void print_cpu_msr(struct cpuinfo_x86 *); 176 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); 177 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); 178 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); 179 180 extern void detect_extended_topology(struct cpuinfo_x86 *c); 181 extern void detect_ht(struct cpuinfo_x86 *c); 182 183 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, 184 unsigned int *ecx, unsigned int *edx) 185 { 186 /* ecx is often an input as well as an output. */ 187 asm volatile("cpuid" 188 : "=a" (*eax), 189 "=b" (*ebx), 190 "=c" (*ecx), 191 "=d" (*edx) 192 : "0" (*eax), "2" (*ecx) 193 : "memory"); 194 } 195 196 static inline void load_cr3(pgd_t *pgdir) 197 { 198 write_cr3(__pa(pgdir)); 199 } 200 201 #ifdef CONFIG_X86_32 202 /* This is the TSS defined by the hardware. */ 203 struct x86_hw_tss { 204 unsigned short back_link, __blh; 205 unsigned long sp0; 206 unsigned short ss0, __ss0h; 207 unsigned long sp1; 208 /* ss1 caches MSR_IA32_SYSENTER_CS: */ 209 unsigned short ss1, __ss1h; 210 unsigned long sp2; 211 unsigned short ss2, __ss2h; 212 unsigned long __cr3; 213 unsigned long ip; 214 unsigned long flags; 215 unsigned long ax; 216 unsigned long cx; 217 unsigned long dx; 218 unsigned long bx; 219 unsigned long sp; 220 unsigned long bp; 221 unsigned long si; 222 unsigned long di; 223 unsigned short es, __esh; 224 unsigned short cs, __csh; 225 unsigned short ss, __ssh; 226 unsigned short ds, __dsh; 227 unsigned short fs, __fsh; 228 unsigned short gs, __gsh; 229 unsigned short ldt, __ldth; 230 unsigned short trace; 231 unsigned short io_bitmap_base; 232 233 } __attribute__((packed)); 234 #else 235 struct x86_hw_tss { 236 u32 reserved1; 237 u64 sp0; 238 u64 sp1; 239 u64 sp2; 240 u64 reserved2; 241 u64 ist[7]; 242 u32 reserved3; 243 u32 reserved4; 244 u16 reserved5; 245 u16 io_bitmap_base; 246 247 } __attribute__((packed)) ____cacheline_aligned; 248 #endif 249 250 /* 251 * IO-bitmap sizes: 252 */ 253 #define IO_BITMAP_BITS 65536 254 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) 255 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) 256 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap) 257 #define INVALID_IO_BITMAP_OFFSET 0x8000 258 259 struct tss_struct { 260 /* 261 * The hardware state: 262 */ 263 struct x86_hw_tss x86_tss; 264 265 /* 266 * The extra 1 is there because the CPU will access an 267 * additional byte beyond the end of the IO permission 268 * bitmap. The extra byte must be all 1 bits, and must 269 * be within the limit. 270 */ 271 unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; 272 273 /* 274 * .. and then another 0x100 bytes for the emergency kernel stack: 275 */ 276 unsigned long stack[64]; 277 278 } ____cacheline_aligned; 279 280 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss); 281 282 /* 283 * Save the original ist values for checking stack pointers during debugging 284 */ 285 struct orig_ist { 286 unsigned long ist[7]; 287 }; 288 289 #define MXCSR_DEFAULT 0x1f80 290 291 struct i387_fsave_struct { 292 u32 cwd; /* FPU Control Word */ 293 u32 swd; /* FPU Status Word */ 294 u32 twd; /* FPU Tag Word */ 295 u32 fip; /* FPU IP Offset */ 296 u32 fcs; /* FPU IP Selector */ 297 u32 foo; /* FPU Operand Pointer Offset */ 298 u32 fos; /* FPU Operand Pointer Selector */ 299 300 /* 8*10 bytes for each FP-reg = 80 bytes: */ 301 u32 st_space[20]; 302 303 /* Software status information [not touched by FSAVE ]: */ 304 u32 status; 305 }; 306 307 struct i387_fxsave_struct { 308 u16 cwd; /* Control Word */ 309 u16 swd; /* Status Word */ 310 u16 twd; /* Tag Word */ 311 u16 fop; /* Last Instruction Opcode */ 312 union { 313 struct { 314 u64 rip; /* Instruction Pointer */ 315 u64 rdp; /* Data Pointer */ 316 }; 317 struct { 318 u32 fip; /* FPU IP Offset */ 319 u32 fcs; /* FPU IP Selector */ 320 u32 foo; /* FPU Operand Offset */ 321 u32 fos; /* FPU Operand Selector */ 322 }; 323 }; 324 u32 mxcsr; /* MXCSR Register State */ 325 u32 mxcsr_mask; /* MXCSR Mask */ 326 327 /* 8*16 bytes for each FP-reg = 128 bytes: */ 328 u32 st_space[32]; 329 330 /* 16*16 bytes for each XMM-reg = 256 bytes: */ 331 u32 xmm_space[64]; 332 333 u32 padding[12]; 334 335 union { 336 u32 padding1[12]; 337 u32 sw_reserved[12]; 338 }; 339 340 } __attribute__((aligned(16))); 341 342 struct i387_soft_struct { 343 u32 cwd; 344 u32 swd; 345 u32 twd; 346 u32 fip; 347 u32 fcs; 348 u32 foo; 349 u32 fos; 350 /* 8*10 bytes for each FP-reg = 80 bytes: */ 351 u32 st_space[20]; 352 u8 ftop; 353 u8 changed; 354 u8 lookahead; 355 u8 no_update; 356 u8 rm; 357 u8 alimit; 358 struct math_emu_info *info; 359 u32 entry_eip; 360 }; 361 362 struct ymmh_struct { 363 /* 16 * 16 bytes for each YMMH-reg = 256 bytes */ 364 u32 ymmh_space[64]; 365 }; 366 367 struct xsave_hdr_struct { 368 u64 xstate_bv; 369 u64 reserved1[2]; 370 u64 reserved2[5]; 371 } __attribute__((packed)); 372 373 struct xsave_struct { 374 struct i387_fxsave_struct i387; 375 struct xsave_hdr_struct xsave_hdr; 376 struct ymmh_struct ymmh; 377 /* new processor state extensions will go here */ 378 } __attribute__ ((packed, aligned (64))); 379 380 union thread_xstate { 381 struct i387_fsave_struct fsave; 382 struct i387_fxsave_struct fxsave; 383 struct i387_soft_struct soft; 384 struct xsave_struct xsave; 385 }; 386 387 struct fpu { 388 unsigned int last_cpu; 389 unsigned int has_fpu; 390 union thread_xstate *state; 391 }; 392 393 #ifdef CONFIG_X86_64 394 DECLARE_PER_CPU(struct orig_ist, orig_ist); 395 396 union irq_stack_union { 397 char irq_stack[IRQ_STACK_SIZE]; 398 /* 399 * GCC hardcodes the stack canary as %gs:40. Since the 400 * irq_stack is the object at %gs:0, we reserve the bottom 401 * 48 bytes of the irq stack for the canary. 402 */ 403 struct { 404 char gs_base[40]; 405 unsigned long stack_canary; 406 }; 407 }; 408 409 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union); 410 DECLARE_INIT_PER_CPU(irq_stack_union); 411 412 DECLARE_PER_CPU(char *, irq_stack_ptr); 413 DECLARE_PER_CPU(unsigned int, irq_count); 414 extern asmlinkage void ignore_sysret(void); 415 #else /* X86_64 */ 416 #ifdef CONFIG_CC_STACKPROTECTOR 417 /* 418 * Make sure stack canary segment base is cached-aligned: 419 * "For Intel Atom processors, avoid non zero segment base address 420 * that is not aligned to cache line boundary at all cost." 421 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.) 422 */ 423 struct stack_canary { 424 char __pad[20]; /* canary at %gs:20 */ 425 unsigned long canary; 426 }; 427 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 428 #endif 429 #endif /* X86_64 */ 430 431 extern unsigned int xstate_size; 432 extern void free_thread_xstate(struct task_struct *); 433 extern struct kmem_cache *task_xstate_cachep; 434 435 struct perf_event; 436 437 struct thread_struct { 438 /* Cached TLS descriptors: */ 439 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 440 unsigned long sp0; 441 unsigned long sp; 442 #ifdef CONFIG_X86_32 443 unsigned long sysenter_cs; 444 #else 445 unsigned long usersp; /* Copy from PDA */ 446 unsigned short es; 447 unsigned short ds; 448 unsigned short fsindex; 449 unsigned short gsindex; 450 #endif 451 #ifdef CONFIG_X86_32 452 unsigned long ip; 453 #endif 454 #ifdef CONFIG_X86_64 455 unsigned long fs; 456 #endif 457 unsigned long gs; 458 /* Save middle states of ptrace breakpoints */ 459 struct perf_event *ptrace_bps[HBP_NUM]; 460 /* Debug status used for traps, single steps, etc... */ 461 unsigned long debugreg6; 462 /* Keep track of the exact dr7 value set by the user */ 463 unsigned long ptrace_dr7; 464 /* Fault info: */ 465 unsigned long cr2; 466 unsigned long trap_nr; 467 unsigned long error_code; 468 /* floating point and extended processor state */ 469 struct fpu fpu; 470 #ifdef CONFIG_X86_32 471 /* Virtual 86 mode info */ 472 struct vm86_struct __user *vm86_info; 473 unsigned long screen_bitmap; 474 unsigned long v86flags; 475 unsigned long v86mask; 476 unsigned long saved_sp0; 477 unsigned int saved_fs; 478 unsigned int saved_gs; 479 #endif 480 /* IO permissions: */ 481 unsigned long *io_bitmap_ptr; 482 unsigned long iopl; 483 /* Max allowed port in the bitmap, in bytes: */ 484 unsigned io_bitmap_max; 485 }; 486 487 /* 488 * Set IOPL bits in EFLAGS from given mask 489 */ 490 static inline void native_set_iopl_mask(unsigned mask) 491 { 492 #ifdef CONFIG_X86_32 493 unsigned int reg; 494 495 asm volatile ("pushfl;" 496 "popl %0;" 497 "andl %1, %0;" 498 "orl %2, %0;" 499 "pushl %0;" 500 "popfl" 501 : "=&r" (reg) 502 : "i" (~X86_EFLAGS_IOPL), "r" (mask)); 503 #endif 504 } 505 506 static inline void 507 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread) 508 { 509 tss->x86_tss.sp0 = thread->sp0; 510 #ifdef CONFIG_X86_32 511 /* Only happens when SEP is enabled, no need to test "SEP"arately: */ 512 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) { 513 tss->x86_tss.ss1 = thread->sysenter_cs; 514 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); 515 } 516 #endif 517 } 518 519 static inline void native_swapgs(void) 520 { 521 #ifdef CONFIG_X86_64 522 asm volatile("swapgs" ::: "memory"); 523 #endif 524 } 525 526 #ifdef CONFIG_PARAVIRT 527 #include <asm/paravirt.h> 528 #else 529 #define __cpuid native_cpuid 530 #define paravirt_enabled() 0 531 532 static inline void load_sp0(struct tss_struct *tss, 533 struct thread_struct *thread) 534 { 535 native_load_sp0(tss, thread); 536 } 537 538 #define set_iopl_mask native_set_iopl_mask 539 #endif /* CONFIG_PARAVIRT */ 540 541 /* 542 * Save the cr4 feature set we're using (ie 543 * Pentium 4MB enable and PPro Global page 544 * enable), so that any CPU's that boot up 545 * after us can get the correct flags. 546 */ 547 extern unsigned long mmu_cr4_features; 548 extern u32 *trampoline_cr4_features; 549 550 static inline void set_in_cr4(unsigned long mask) 551 { 552 unsigned long cr4; 553 554 mmu_cr4_features |= mask; 555 if (trampoline_cr4_features) 556 *trampoline_cr4_features = mmu_cr4_features; 557 cr4 = read_cr4(); 558 cr4 |= mask; 559 write_cr4(cr4); 560 } 561 562 static inline void clear_in_cr4(unsigned long mask) 563 { 564 unsigned long cr4; 565 566 mmu_cr4_features &= ~mask; 567 if (trampoline_cr4_features) 568 *trampoline_cr4_features = mmu_cr4_features; 569 cr4 = read_cr4(); 570 cr4 &= ~mask; 571 write_cr4(cr4); 572 } 573 574 typedef struct { 575 unsigned long seg; 576 } mm_segment_t; 577 578 579 /* Free all resources held by a thread. */ 580 extern void release_thread(struct task_struct *); 581 582 unsigned long get_wchan(struct task_struct *p); 583 584 /* 585 * Generic CPUID function 586 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx 587 * resulting in stale register contents being returned. 588 */ 589 static inline void cpuid(unsigned int op, 590 unsigned int *eax, unsigned int *ebx, 591 unsigned int *ecx, unsigned int *edx) 592 { 593 *eax = op; 594 *ecx = 0; 595 __cpuid(eax, ebx, ecx, edx); 596 } 597 598 /* Some CPUID calls want 'count' to be placed in ecx */ 599 static inline void cpuid_count(unsigned int op, int count, 600 unsigned int *eax, unsigned int *ebx, 601 unsigned int *ecx, unsigned int *edx) 602 { 603 *eax = op; 604 *ecx = count; 605 __cpuid(eax, ebx, ecx, edx); 606 } 607 608 /* 609 * CPUID functions returning a single datum 610 */ 611 static inline unsigned int cpuid_eax(unsigned int op) 612 { 613 unsigned int eax, ebx, ecx, edx; 614 615 cpuid(op, &eax, &ebx, &ecx, &edx); 616 617 return eax; 618 } 619 620 static inline unsigned int cpuid_ebx(unsigned int op) 621 { 622 unsigned int eax, ebx, ecx, edx; 623 624 cpuid(op, &eax, &ebx, &ecx, &edx); 625 626 return ebx; 627 } 628 629 static inline unsigned int cpuid_ecx(unsigned int op) 630 { 631 unsigned int eax, ebx, ecx, edx; 632 633 cpuid(op, &eax, &ebx, &ecx, &edx); 634 635 return ecx; 636 } 637 638 static inline unsigned int cpuid_edx(unsigned int op) 639 { 640 unsigned int eax, ebx, ecx, edx; 641 642 cpuid(op, &eax, &ebx, &ecx, &edx); 643 644 return edx; 645 } 646 647 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ 648 static inline void rep_nop(void) 649 { 650 asm volatile("rep; nop" ::: "memory"); 651 } 652 653 static inline void cpu_relax(void) 654 { 655 rep_nop(); 656 } 657 658 /* Stop speculative execution and prefetching of modified code. */ 659 static inline void sync_core(void) 660 { 661 int tmp; 662 663 #ifdef CONFIG_M486 664 /* 665 * Do a CPUID if available, otherwise do a jump. The jump 666 * can conveniently enough be the jump around CPUID. 667 */ 668 asm volatile("cmpl %2,%1\n\t" 669 "jl 1f\n\t" 670 "cpuid\n" 671 "1:" 672 : "=a" (tmp) 673 : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1) 674 : "ebx", "ecx", "edx", "memory"); 675 #else 676 /* 677 * CPUID is a barrier to speculative execution. 678 * Prefetched instructions are automatically 679 * invalidated when modified. 680 */ 681 asm volatile("cpuid" 682 : "=a" (tmp) 683 : "0" (1) 684 : "ebx", "ecx", "edx", "memory"); 685 #endif 686 } 687 688 static inline void __monitor(const void *eax, unsigned long ecx, 689 unsigned long edx) 690 { 691 /* "monitor %eax, %ecx, %edx;" */ 692 asm volatile(".byte 0x0f, 0x01, 0xc8;" 693 :: "a" (eax), "c" (ecx), "d"(edx)); 694 } 695 696 static inline void __mwait(unsigned long eax, unsigned long ecx) 697 { 698 /* "mwait %eax, %ecx;" */ 699 asm volatile(".byte 0x0f, 0x01, 0xc9;" 700 :: "a" (eax), "c" (ecx)); 701 } 702 703 static inline void __sti_mwait(unsigned long eax, unsigned long ecx) 704 { 705 trace_hardirqs_on(); 706 /* "mwait %eax, %ecx;" */ 707 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;" 708 :: "a" (eax), "c" (ecx)); 709 } 710 711 extern void select_idle_routine(const struct cpuinfo_x86 *c); 712 extern void init_amd_e400_c1e_mask(void); 713 714 extern unsigned long boot_option_idle_override; 715 extern bool amd_e400_c1e_detected; 716 717 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, 718 IDLE_POLL}; 719 720 extern void enable_sep_cpu(void); 721 extern int sysenter_setup(void); 722 723 extern void early_trap_init(void); 724 725 /* Defined in head.S */ 726 extern struct desc_ptr early_gdt_descr; 727 728 extern void cpu_set_gdt(int); 729 extern void switch_to_new_gdt(int); 730 extern void load_percpu_segment(int); 731 extern void cpu_init(void); 732 733 static inline unsigned long get_debugctlmsr(void) 734 { 735 unsigned long debugctlmsr = 0; 736 737 #ifndef CONFIG_X86_DEBUGCTLMSR 738 if (boot_cpu_data.x86 < 6) 739 return 0; 740 #endif 741 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 742 743 return debugctlmsr; 744 } 745 746 static inline void update_debugctlmsr(unsigned long debugctlmsr) 747 { 748 #ifndef CONFIG_X86_DEBUGCTLMSR 749 if (boot_cpu_data.x86 < 6) 750 return; 751 #endif 752 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 753 } 754 755 extern void set_task_blockstep(struct task_struct *task, bool on); 756 757 /* 758 * from system description table in BIOS. Mostly for MCA use, but 759 * others may find it useful: 760 */ 761 extern unsigned int machine_id; 762 extern unsigned int machine_submodel_id; 763 extern unsigned int BIOS_revision; 764 765 /* Boot loader type from the setup header: */ 766 extern int bootloader_type; 767 extern int bootloader_version; 768 769 extern char ignore_fpu_irq; 770 771 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 772 #define ARCH_HAS_PREFETCHW 773 #define ARCH_HAS_SPINLOCK_PREFETCH 774 775 #ifdef CONFIG_X86_32 776 # define BASE_PREFETCH ASM_NOP4 777 # define ARCH_HAS_PREFETCH 778 #else 779 # define BASE_PREFETCH "prefetcht0 (%1)" 780 #endif 781 782 /* 783 * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 784 * 785 * It's not worth to care about 3dnow prefetches for the K6 786 * because they are microcoded there and very slow. 787 */ 788 static inline void prefetch(const void *x) 789 { 790 alternative_input(BASE_PREFETCH, 791 "prefetchnta (%1)", 792 X86_FEATURE_XMM, 793 "r" (x)); 794 } 795 796 /* 797 * 3dnow prefetch to get an exclusive cache line. 798 * Useful for spinlocks to avoid one state transition in the 799 * cache coherency protocol: 800 */ 801 static inline void prefetchw(const void *x) 802 { 803 alternative_input(BASE_PREFETCH, 804 "prefetchw (%1)", 805 X86_FEATURE_3DNOW, 806 "r" (x)); 807 } 808 809 static inline void spin_lock_prefetch(const void *x) 810 { 811 prefetchw(x); 812 } 813 814 #ifdef CONFIG_X86_32 815 /* 816 * User space process size: 3GB (default). 817 */ 818 #define TASK_SIZE PAGE_OFFSET 819 #define TASK_SIZE_MAX TASK_SIZE 820 #define STACK_TOP TASK_SIZE 821 #define STACK_TOP_MAX STACK_TOP 822 823 #define INIT_THREAD { \ 824 .sp0 = sizeof(init_stack) + (long)&init_stack, \ 825 .vm86_info = NULL, \ 826 .sysenter_cs = __KERNEL_CS, \ 827 .io_bitmap_ptr = NULL, \ 828 } 829 830 /* 831 * Note that the .io_bitmap member must be extra-big. This is because 832 * the CPU will access an additional byte beyond the end of the IO 833 * permission bitmap. The extra byte must be all 1 bits, and must 834 * be within the limit. 835 */ 836 #define INIT_TSS { \ 837 .x86_tss = { \ 838 .sp0 = sizeof(init_stack) + (long)&init_stack, \ 839 .ss0 = __KERNEL_DS, \ 840 .ss1 = __KERNEL_CS, \ 841 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \ 842 }, \ 843 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \ 844 } 845 846 extern unsigned long thread_saved_pc(struct task_struct *tsk); 847 848 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long)) 849 #define KSTK_TOP(info) \ 850 ({ \ 851 unsigned long *__ptr = (unsigned long *)(info); \ 852 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \ 853 }) 854 855 /* 856 * The below -8 is to reserve 8 bytes on top of the ring0 stack. 857 * This is necessary to guarantee that the entire "struct pt_regs" 858 * is accessible even if the CPU haven't stored the SS/ESP registers 859 * on the stack (interrupt gate does not save these registers 860 * when switching to the same priv ring). 861 * Therefore beware: accessing the ss/esp fields of the 862 * "struct pt_regs" is possible, but they may contain the 863 * completely wrong values. 864 */ 865 #define task_pt_regs(task) \ 866 ({ \ 867 struct pt_regs *__regs__; \ 868 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \ 869 __regs__ - 1; \ 870 }) 871 872 #define KSTK_ESP(task) (task_pt_regs(task)->sp) 873 874 #else 875 /* 876 * User space process size. 47bits minus one guard page. 877 */ 878 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE) 879 880 /* This decides where the kernel will search for a free chunk of vm 881 * space during mmap's. 882 */ 883 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ 884 0xc0000000 : 0xFFFFe000) 885 886 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \ 887 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 888 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \ 889 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 890 891 #define STACK_TOP TASK_SIZE 892 #define STACK_TOP_MAX TASK_SIZE_MAX 893 894 #define INIT_THREAD { \ 895 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \ 896 } 897 898 #define INIT_TSS { \ 899 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \ 900 } 901 902 /* 903 * Return saved PC of a blocked thread. 904 * What is this good for? it will be always the scheduler or ret_from_fork. 905 */ 906 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8)) 907 908 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1) 909 extern unsigned long KSTK_ESP(struct task_struct *task); 910 911 /* 912 * User space RSP while inside the SYSCALL fast path 913 */ 914 DECLARE_PER_CPU(unsigned long, old_rsp); 915 916 #endif /* CONFIG_X86_64 */ 917 918 extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 919 unsigned long new_sp); 920 921 /* 922 * This decides where the kernel will search for a free chunk of vm 923 * space during mmap's. 924 */ 925 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) 926 927 #define KSTK_EIP(task) (task_pt_regs(task)->ip) 928 929 /* Get/set a process' ability to use the timestamp counter instruction */ 930 #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 931 #define SET_TSC_CTL(val) set_tsc_mode((val)) 932 933 extern int get_tsc_mode(unsigned long adr); 934 extern int set_tsc_mode(unsigned int val); 935 936 extern u16 amd_get_nb_id(int cpu); 937 938 struct aperfmperf { 939 u64 aperf, mperf; 940 }; 941 942 static inline void get_aperfmperf(struct aperfmperf *am) 943 { 944 WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_APERFMPERF)); 945 946 rdmsrl(MSR_IA32_APERF, am->aperf); 947 rdmsrl(MSR_IA32_MPERF, am->mperf); 948 } 949 950 #define APERFMPERF_SHIFT 10 951 952 static inline 953 unsigned long calc_aperfmperf_ratio(struct aperfmperf *old, 954 struct aperfmperf *new) 955 { 956 u64 aperf = new->aperf - old->aperf; 957 u64 mperf = new->mperf - old->mperf; 958 unsigned long ratio = aperf; 959 960 mperf >>= APERFMPERF_SHIFT; 961 if (mperf) 962 ratio = div64_u64(aperf, mperf); 963 964 return ratio; 965 } 966 967 /* 968 * AMD errata checking 969 */ 970 #ifdef CONFIG_CPU_SUP_AMD 971 extern const int amd_erratum_383[]; 972 extern const int amd_erratum_400[]; 973 extern bool cpu_has_amd_erratum(const int *); 974 975 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } 976 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } 977 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ 978 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) 979 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) 980 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) 981 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) 982 983 #else 984 #define cpu_has_amd_erratum(x) (false) 985 #endif /* CONFIG_CPU_SUP_AMD */ 986 987 extern unsigned long arch_align_stack(unsigned long sp); 988 extern void free_init_pages(char *what, unsigned long begin, unsigned long end); 989 990 void default_idle(void); 991 #ifdef CONFIG_XEN 992 bool xen_set_default_idle(void); 993 #else 994 #define xen_set_default_idle 0 995 #endif 996 997 void stop_this_cpu(void *dummy); 998 999 #endif /* _ASM_X86_PROCESSOR_H */ 1000